Abstract
Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.
Highlights
Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable, while system scaling enabled by the Moore’s law is facing challenges due to the scarcity of resources such as power and interconnect bandwidth
The avalanche breakdown is a very fast and gated diode pulsed into breakdown can show subthreshold slopes much lower than 60 mV/dec [7], and exhibits lower off-state current compared with a conventional MOSFET [8]
While we found the potential of GAA devices has not been fully discovered, by introducing a core-Insulator into conventional GAA devices, the off-state current is expected to be further lowered, which makes it more suitable for fabricating low-power devices
Summary
Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable, while system scaling enabled by the Moore’s law is facing challenges due to the scarcity of resources such as power and interconnect bandwidth. By introducing new physical mechanics into CMOS devices, researchers are able to lower the subthreshold slope of transistors and reduce the leaking current of whole system. These types of devices include Impact Ionization MOS (IMOS) [5] and Tunnel Field Effect Transistors (TFET) [6]. Because of the presence of Core–Insulator, the off-state current is lowered by more than two times, and it shows better subthreshold characteristics We believe that this newly proposed structure can be a promising candidate of future low-power and energy-efficient CMOS devices
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