Complementary Metal-oxide-semiconductor Fabrication Process Research Articles

Scalable photonic integrated circuits for high-fidelity light control

Advances in laser technology have driven discoveries in atomic, molecular, and optical (AMO) physics and emerging applications, from quantum computers with cold atoms or ions, to quantum networks with solid-state color centers. This progress is motivating the development of a new generation of optical control systems that can manipulate the light field with high fidelity at wavelengths relevant for AMO applications. These systems are characterized by criteria: (C1) operation at a design wavelength of choice in the visible (VIS) or near-infrared (IR) spectrum, (C2) a scalable platform that can support large channel counts, (C3) high-intensity modulation extinction and (C4) repeatability compatible with low gate errors, and (C5) fast switching times. Here, we provide a pathway to address these challenges by introducing an atom control architecture based on VIS-IR photonic integrated circuit (PIC) technology. Based on a complementary metal–oxide–semiconductor fabrication process, this atom-control PIC (APIC) technology can meet system requirements (C1)–(C5). As a proof of concept, we demonstrate a 16-channel silicon-nitride-based APIC with (5.8±0.4)ns response times and >30dB extinction ratio at a wavelength of 780 nm.

Inverse design of a binary waveguide crossing by the particle swarm optimization algorithm

This paper describes the inverse design of the particle swarm optimization algorithm combined with the three-dimensional finite-difference time-domain simulation to design a waveguide crossing that resembles a binary code. The device consists of 15 × 15 air holes in a 220-nm silicon slab on a 3-μm-thick SiO2 substrate with one input port and three output waveguide ports. The designed device has a small footprint of 4μm2 and a short simulation time of 1.7 h. In the wavelength range of 1.5–1.6μm, the device has insertion loss IL<0.85 dB and crosstalk XT<−14.5 dB. This device tolerates air hole-position disordering of ηp=23%, and hole-radius disordering of ηr=35%, so it is appropriate to use in the complementary metal–oxide–semiconductor fabrication process. The paper also proposes integrated interconnections that contain 2 × 2 waveguide crossings and have IL<2.9 dB and XT<−13 dB, and 3 × 3 waveguide crossings that have IL<5 and XT<−12.5 dB.

Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition

Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/oC.

Electrical Characteristics of Nanoelectromechanical Relay with Multi-Domain HfO2-Based Ferroelectric Materials

Since the discovery of ferroelectricity in HfO2-based materials which are comparable to the complementary metal-oxide–semiconductor (CMOS) fabrication process—a negative capacitance effect in the HfO2-based materials has been actively studied. Owing to nonuniform polarization-switching (which is originated from the polycrystalline structures of HfO2-based ferroelectric materials), the formation of multi-domains in the HfO2-based materials is inevitable. In previous studies, perovskite-based ferroelectric materials (which is not compatible to CMOS fabrication process) were utilized to improve the electrical properties of a nanoelectromechanical (NEM) relay. In this study, the effects of a multi-domain HfO2-based ferroelectric material on the electrical characteristics of an NEM relay were theoretically examined. Specifically, the number of domains, domain inhomogeneity and ferroelectric thickness of the multi-domain ferroelectric material were modulated and subsequently, its corresponding results were discussed. It was observed that the switching voltage variation was decreased with increasing the number of domains and decreasing domain inhomogeneity. In addition, the switching voltage was decreased with increasing ferroelectric thickness, owing to enhanced voltage amplification.

Spike-driven threshold-based learning with memristive synapses and neuromorphic silicon neurons

Biologically plausible neuromorphic computing systems are attracting considerable attention due to their low latency, massively parallel information processing abilities, and their high energy efficiency. To achieve these features neuromorphic silicon neuron circuits need to be integrated with plastic synapse circuits capable of on-line learning and storage of synaptic weights. Within this context, memristive devices play a key role thanks to their non-volatility, scalability, and compatibility with the complementary metal–oxide–semiconductor fabrication process. However, neuro-memristive systems are still facing difficult challenges for implementing efficient learning protocols. Here, we propose and demonstrate in hardware a spike-driven threshold-based learning rule which goes beyond conventional spike-timing dependent plasticity mechanisms, by also taking into account the neuron membrane potential and its firing rate. The mixed memristive–neuromorphic system we demonstrate comprises an oxide-based memristive synapse device placed between two silicon neurons implemented on a neuromorphic chip that comprises the proper interfacing and spike-based learning circuits designed to drive the memristive elements. We show how the system is able to emulate in real-time weight dependent post-synaptic activity and drive synaptic weight updates at the memristive synapse level following the spike-driven learning rule presented. We validate this spike-based learning mechanism with experimental results and quantify the system performance with basic learning experiments.

Integration of crystalline orientated γ-Al2O3 films and complementary metal–oxide–semiconductor circuits on Si(1 0 0) substrate

In this paper, integration of crystalline orientated γ-Al2O3 films and complementary metal–oxide–semiconductor (CMOS) circuits on Si(100) substrate was reported. In this integration processes, crystalline γ-Al2O3 films need to be preserved their crystallinity during high temperature annealing processes of CMOS fabrication in order to prevent surface condition changes. The γ-Al2O3 films grown on Si substrates are annealed in the CMOS fabrication process conditions, drive-in annealing at 1150°C in O2 atmosphere and wet annealing 1000°C in H2O vapor atmosphere. Reflection high energy electron diffraction (RHEED) and x-ray diffraction (XRD) were used to characterize the crystallinity of γ-Al2O3 films after the annealing processes. Surface conditions of the films are analyzed and observed with X-ray photoelectron spectroscopy (XPS) and scanning electron microscope (SEM). As a result, RHEED patterns of the γ-Al2O3 films indicated that wet oxidation annealing was a critical process severally inferior surface condition of crystalline γ-Al2O3 films. XRD, XPS, and SEM investigation unveiled further details of the crystallinity changes on γ-Al2O3 films for each process. These results indicated passivation films were required to integrate γ-Al2O3 films with CMOS fabrication process. Therefore we proposed and introduced Si3N4/TEOS passivation films on γ-Al2O3 films in CMOS fabrication processes. At last, MOSFETs on γ-Al2O3 integrated Si(100) substrate were fabricated and characterized. The designed characteristics of MOSFETs were obtained on γ-Al2O3 integrated Si substrate.

CMOS-Compatible Polarization Splitter for 3-D Silicon Photonic Integrated Circuits

To achieve intra-chip three-dimensional (3-D) integration of silicon photonic circuits, we design a polarization beam splitter based on complementary metal-oxide-semiconductor (CMOS) platform. With the aid of the polarization-dependent nature of the center waveguide in a three-port directional coupler, the device separates the TM- and TE-polarization modes onto different layers of 3-D silicon photonic circuits. Numerical simulations with a full vectorial beam propagation method exhibit that we can obtain a 10 μm-long polarization splitter with extinction ratio better than 20 dB on the entire C-band. The optical device without the vertical offset can serve as a horizontal polarization splitter with nearly the same optical characteristics. We conclude that the proposed polarization beam splitter is compatible not only with the CMOS structure but also with the CMOS fabrication process.

Design of Low Power Integrated CMOS Potentiometric Biosensor for Direct Electronic Detection of DNA Hybridization

The purpose of this research is to design a low power integrated complementary metal oxide semiconductor (CMOS) detection circuit for charge-modulated field-effect transistor (CMFET) and it is used for the detection of deoxyribonucleic acid (DNA) hybridization. With the available CMOS technology, it allows the realization of complete systems which integrate the sensing units and transducing elements in the same device. Point-of-care (POC) testing device is a device that allows anyone to operate anywhere and obtain immediate results. One of the important features of POC device is low power consumption because it is normally battery-operated. The power consumption of the proposed integrated CMOS detection circuit requires only 14.87 mW. The detection circuit will amplify the electrical signal that comes from the CMFET to a specified level in order to improve the recording characteristics of the biosensor. Self-cascode topology was used in the drain follower circuit in order to reduce the channel length modulation effect. The proposed detection circuit was designed with 0.18µm Silterra CMOS fabrication process and simulated under Cadence Simulation Tool.

A Dual-Gate Field-Effect Transistor for Label-Free Electrical Detection of Avian Influenza

A dual-gate silicon nanowire field-effect transistor (FET) fabricated on a bulk substrate is designed to perform label-free electrical detection of the avian influenza antibody. A region of a FET channel that is conventionally covered by a gate electrode is intentionally left open in the dual-gate configuration, to provide a binding site for biological species. As a result, the channel potential at this open area is affected by the polarity and charge of the biological species that binds to the opened channel. The proposed device can be used as a biosensor by comparing its electrical characteristics before and after exposing the device to biological species of interest. This detection mechanism is verified using numerical simulation and by attaching charged polyelectrolytes (PAH and PSS) to the opened channel. Additionally, the avian influenza antibody is successfully detected without a labeling step using the proposed dual-gate FET. As a biomedical diagnostic tool, the proposed biosensor offers the advantages of label-free detection capability, low-cost compatibility with the complementary metal–oxide semiconductor fabrication process, and a read-out system for on-chip integration.

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.

Multifunctional Field-Effect Transistor for High-Density Integrated Circuits

A multifunctional field-effect transistor (FET) for the manufacturing of high-density integrated circuits (ICs) has been developed and fabricated. Furthermore, an extensive numerical device simulation campaign has been carried out in order to characterize the new structure. Such device is a metal-oxide-semiconductor (MOS) FET that simultaneously performs the functions of two traditional FETs (an n-channel MOS and a p-channel MOS), working as one or as the other according to the voltage applied to the gate's terminal. Combinational and sequential circuits employing the new technology introduce, with respect to the standard complementary MOS (CMOS) ones, a drastic reduction of both the required device number and the parasitic capacitances. This leads to a significant increase in the circuit's speed. Furthermore, the ICs obtained with these transistors are fully compatible with the standard CMOS technology and fabrication process.

Modeling and Characterization of CMOS-Fabricated Capacitive Micromachined Ultrasound Transducers

This paper describes the fabrication, characterization, and modeling of complementary metal-oxide-semiconductor (CMOS)-compatible capacitive micromachined ultrasound transducers (CMUTs). The transducers are fabricated using the interconnect and dielectric layers from a standard CMOS fabrication process. Unlike previous efforts toward integrating CMUTs with CMOS electronics, this process adds no microelectromechanical systems-related steps to the CMOS process and requires no critical lithography steps after the CMOS process is complete. Efficient computational models of the transducers were produced through the combined use of finite-element analysis and lumped-element modeling. A method for improved computation of the electrostatic coupling and environmental loading is presented without the need for multiple finite-element computations. Through the use of laser Doppler velocimetry, transient impulse response and steady-state frequency sweep tests were performed. These measurements are compared to the results predicted by the models. The performance characteristics were compared experimentally through changes in the applied bias voltage, device diameter, and medium properties (air, vacuum, oil, and water). Sparse clusters of up to 33 elements were tested in transmit mode in a water tank, achieving a center frequency of 3.5 MHz, a fractional bandwidth of 32%-44%, and pressure amplitudes of 181-184 dB re 1 μPa <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> at 15 mm from the transducer on axis.

Characterization of imaging performance of a large-area CMOS active-pixel detector for low-energy X-ray imaging

Abstract We report the imaging characteristics of the recently developed large-area complementary metal-oxide-semiconductor (CMOS) active-pixel detector for low-energy digital X-ray imaging applications. The detector consists of a scintillator to convert X-ray into light and a photodiode pixel array made by the CMOS fabrication process to convert light into charge signals. Between two layers, we introduce a fiber-optic faceplate (FOP) to avoid direct absorption of X-ray photons in the photodiode array. A single pixel is composed of a photodiode and three transistors, and the pixel pitch is 96 μm. The imaging characteristics of the detector have been investigated in terms of modulation-transfer function (MTF), noise-power spectrum (NPS), and detective quantum efficiency (DQE). From the measured results, the MTF at the Nyquist frequency is about 20% and the DQE around zero-spatial frequency is about 40%. Simple cascaded linear-systems analysis has showed that the FOP prevents direct absorption of X-ray photons within the CMOS photodiode array, leading to a lower NPS and consequently improved DQE especially at high spatial frequencies.

Colorimetric porous photonic bandgap sensors with integrated CMOS color detectors

In this paper, the development of a novel colorimetric sensor system based on the integration of complementary metal-oxide-semiconductor (CMOS) color detectors with a modified porous polymeric photonic bandgap sensor is reported. The color detector integrated circuit IC is implemented with AMI (AMI Semiconductor) 1.5 /spl mu/m technology, a standard CMOS fabrication process available at MOSIS (http://www.mosis.org). The color detectors are based on the spectral responses of buried double junctions (BDjs) and stacked triple junctions (STJs); the ratio of the photocurrents at the junctions provides spectral information. Both types of color detectors are characterized with a monochromator, and the results are compared. The BDJ color detector is used with a porous photonic bandgap reflection grating whose reflection spectra shifts as a function of the concentration of vapor analyte present. The experimental results verify that the color change of the photonic crystal can be detected and correlated to the change in analyte concentration. The entire system is compact and low power.

A Complementary Metal-Oxide-Semiconductor Vision Chip for Edge and Motion Detection with a Function for Output Offset Cancellation

We have designed and fabricated a complementary metal-oxide-semiconductor (CMOS) vision chip by modeling cells of the human retina as hardware that are involved in edge and motion detection. There are several fluctuation factors which affect the characteristics of metal-oxide-semiconductor field effect transistors (MOSFETs) through the CMOS fabrication process and this effect appears as the output offset of the vision chip, which is composed of pixel arrays and readout circuits. The vision chip which detects edge and motion information from an input image is used for the input stage of other systems. Therefore, the output offset of the vision chip determines the efficiency of the entire system. In order to eliminate the offset at the output stage, we designed a vision chip utilizing the correlated double sampling (CDS) technique. The chip has been fabricated using a 0.6 μm standard CMOS process. With reliable output characteristics, this chip can be used at the input stage for various applications. © 2005 The Optical Society of Japan

Fabrication of microbridges in standard complementary metal oxide semiconductor technology

Complementary metal oxide semiconductor (CMOS) technology is one of the leading fabrication technologies of the semiconductor integrated-circuit industry. We have discovered features inherent in the standard CMOS fabrication process that lend themselves to the manufacturing of micromechanical structures for sensor applications. In this paper we present an unconventional layout design methodology that allows us to exploit the standard CMOS process for producing microbridges. Two types of microbridges, bare polysilicon microbridges and sandwiched oxide microbridges, have been manufactured by first implementing a special layout design in an industrial digital CMOS process, followed by a postprocessing etching step.