Complementary Metal Oxide Semiconductor Devices Research Articles

A review of emerging trends in photonic deep learning accelerators

Deep learning has revolutionized many sectors of industry and daily life, but as application scale increases, performing training and inference with large models on massive datasets is increasingly unsustainable on existing hardware. Highly parallelized hardware like Graphics Processing Units (GPUs) are now widely used to improve speed over conventional Central Processing Units (CPUs). However, Complementary Metal-oxide Semiconductor (CMOS) devices suffer from fundamental limitations relying on metallic interconnects which impose inherent constraints on bandwidth, latency, and energy efficiency. Indeed, by 2026, the projected global electricity consumption of data centers fueled by CMOS chips is expected to increase by an amount equivalent to the annual usage of an additional European country. Silicon Photonics (SiPh) devices are emerging as a promising energy-efficient CMOS-compatible alternative to electronic deep learning accelerators, using light to compute as well as communicate. In this review, we examine the prospects of photonic computing as an emerging solution for acceleration in deep learning applications. We present an overview of the photonic computing landscape, then focus in detail on SiPh integrated circuit (PIC) accelerators designed for different neural network models and applications deep learning. We categorize different devices based on their use cases and operating principles to assess relative strengths, present open challenges, and identify new directions for further research.

P/N-Type Conversion of 2D MoTe2 Controlled by Top Gate Engineering for Logic Circuits.

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) are regarded as promising materials for next-generation logic circuits. Top gate field-effect transistors (FETs) have independent gate control ability and can be fabricated directly on TMDC materials without a transfer process. Therefore, it has the merits of device reliability and complementary metal-oxide semiconductor (CMOS) process compatibility, which are demanded in practical circuit-level integration. However, the fabrication of the top gate FET involves depositing an insulating dielectric layer and a gate electrode in sequence on the TMDC channel material, which may affect the device performance. Insightfully investigating the influences of different top-gate-deposition methods on the electrical properties of the TMDC channel and further harnessing these influences to realize a homogeneous CMOS device on an identical 2D TMDC platform are with practice significance. In this work, p/n-type controllable top gate FET arrays based on 2H-MoTe2 are fabricated by using different top-gate-deposition methods. The electron-beam evaporation (EBE) of top metal gate exhibits an obvious n-doping effect on the 2H-MoTe2 channel and converts it from p-type to n-type, whereas the thermal evaporation of top gate affects little to the channel. High-resolution transmission electron microscopy (HR-TEM) analysis reveals that the high-energy metal atoms from the EBE process can penetrate through the 30 nm gate dielectric layers (including 10 nm Al2O3 seeding layer), leading to multiple atomic defects in both MoTe2 and the interface between MoTe2 and Al2O3. Furthermore, by utilizing the top gate engineering, a large-scale double-top-gate MoTe2 homogeneous CMOS inverter array is fabricated. The CMOS inverters exhibit clear logic swing, negligible hysteresis, and high device yield (∼93%), indicating high device reliability and stability. Notably, the fabrication process is facile, free from transfer procedure, and compatible with traditional silicon technology. This work promotes the application of 2D TMDCs in nanoelectronics integration.

Electrical Polarity Modulation in V-Doped Monolayer WS2 for Homogeneous CMOS Inverters.

As demand for higher integration density and smaller devices grows, silicon-based complementary metal-oxide-semiconductor (CMOS) devices will soon reach their ultimate limits. 2D transition metal dichalcogenides (TMDs) semiconductors, known for excellent electrical performance and stable atomic structure, are seen as promising materials for future integrated circuits. However, controlled and reliable doping of 2D TMDs, a key step for creating homogeneous CMOS logic components, remains a challenge. In this study, a continuous electrical polarity modulation of monolayer WS2 from intrinsic n-type to ambipolar, then to p-type, and ultimately to a quasi-metallic state is achieved simply by introducing controllable amounts of vanadium (V) atoms into the WS2 lattice as p-type dopants during chemical vapor deposition (CVD). The achievement of purely p-type field-effect transistors (FETs) is particularly noteworthy based on the 4.7 at% V-doped monolayer WS2, demonstrating a remarkable on/off current ratio of 105. Expanding on this triumph, the first initial prototype of ultrathin homogeneous CMOS inverters based on monolayer WS2 is being constructed. These outcomes validate the feasibility of constructing homogeneous CMOS devices through the atomic doping process of 2D materials, marking a significant milestone for the future development of integrated circuits.

Performance improvements in complementary metal oxide semiconductor devices and circuits based on fin field-effect transistors using 3-nm ferroelectric Hf0.5Zr0.5O2

In this work, a conventional HfO2 gate dielectric layer is replaced with a 3-nm ferroelectric (Fe) HZO layer in the gate stacks of advanced fin field-effect transistors (FinFETs). Fe-induced characteristics, e.g., negative drain induced barrier lowering (N-DIBL) and negative differential resistance (NDR), are clearly observed for both p- and n-type HZO-based FinFETs. These characteristics are attributed to the enhanced ferroelectricity of the 3-nm hafnium zirconium oxide (HZO) film, caused by Al doping from the TiAlC capping layer. This mechanism is verified for capacitors with structures similar to the FinFETs. Owing to the enhanced ferroelectricity and N-DIBL phenomenon, the drain current (IDS) of the HZO-FinFETs is greater than that of HfO2-FinFETs and obtained at a lower operating voltage. Accordingly, circuits based on HZO-FinFET achieve higher performance than those based on HfO2-FinFET at a low voltage drain (VDD), which indicates the application feasibility of the HZO-FinFETs in the ultra-low power integrated circuits.Graphical abstract

Calculating and analyzing time delay in zigzag graphene nanoscrolls based complementary metal-oxide-semiconductors

Graphene Nano Scrolls (GNSs) and Zigzag graphene nanoscrolls (ZGNSs) are semi-one-dimensional materials with exceptional electrical and optical properties, making them attractive to be used in nanoelectronics and complementary metal–oxide–semiconductor (CMOS) technology. With in CMOS device technology, time delay is a crucial issue in the design and implementation of CMOS based ZGNSs. Current paper focus is on ZGNSs application in the channel area of metal–oxide–semiconductor field-effect transistors (MOSFETs) in CMOS technology. We studied analytically, the importance of different parameters on time delay reduction, resulting in faster switching and higher frequency in integrated circuits (ICs). The results of this research demonstrates that, the ZGNS-based CMOS proves considerable variations in the current due to the geometrical parameters, such as chirality number, channel length, and nanoscroll length which can be engineered to produce faster ICs.

Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology

Designing a power efficient and high-speed static random-access memory (SRAM) cell with improved noise stability using traditional complementary metal oxide semiconductor (CMOS) devices is an arduous task. Owing to balanced electrical properties of graphene nanoribbon field-effect transistor (GNRFET), its capability to realize high performance SRAM cells need a keen exploration. This article proposes an 11-transistor GNRFET SRAM cell which deploys hybrid inverter scheme. The hybrid inverter scheme encompasses two distinct inverters, based on stacked transistors and Schmitt trigger (ST) techniques. The simulations conducted using 16 nm GNRFET model in HSPICE simulator show that proposed SRAM cell has write power, hold power, read power, write static noise margin, hold static noise margin, read static noise margin, write delay and read delay of 0.445 nW, 0.978 µW, 1.8 nW, 225 mV, 222.8 mV, 225.1 mV, 24 pS and 49.6 pS, respectively. The results obtained for proposed SRAM cell have been found to be encouraging in contrast to previously reported SRAM cells implemented using 16 nm GNRFET model. Besides this, the effect of variation in various parameters of GNRFET on performance of proposed SRAM cell has been investigated in this article. The outstanding performance results of SRAM makes its suitable for developing high performance memories devices for biomedical digital gadgets, internet of things (IoT), artificial intelligence (AI) and smart agricultural applications.

Investigating the physical mechanism of ion-slicing in AlN and hetero-integrating AlN thin film on Si(100) substrate

Heterogeneously integrating the monocrystal AlN thin films on Si(100) substrates by ion-slicing technique provides a promising high-quality material platform to achieve the monolithic integration of Silicon-based CMOS (Complementary Metal Oxide Semiconductor) and high-performance III-nitride devices. Single crystalline AlN bulk materials implanted by hydrogen ions (H+) were used to elucidate the physical mechanism of the blistering formation in hydrogen implanted AlN with different annealing process. XTEM characterization was performed to reveal the formation of H-induced microcracks which eventually leads to the layer splitting. Using the ion-slicing technique, the AlN thin films were capitally transferred to Si(100) substrate. The crystal quality and the microstructure of the transferred AlN thin film were characterized thoroughly, indicating its exceptional crystal quality with the full width at half maximum (FWHM) for (002) XRC as low as 93.6 arcsec.

VO2 memristor-based frequency converter with in-situ synthesize and mix for wireless internet-of-things

Wireless internet-of-things (WIoT) with data acquisition sensors are evolving rapidly and the demand for transmission efficiency is growing rapidly. Frequency converter that synthesizes signals at different frequencies and mixes them with sensor datastreams is a key component for efficient wireless transmission. However, existing frequency converters employ separate synthesize and mix circuits with complex digital and analog circuits using complementary metal-oxide semiconductor (CMOS) devices, naturally incurring excessive latency and energy consumption. Here we report a highly uniform and calibratable VO2 memristor oscillator, based on which we build memristor-based frequency converter using 8×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ imes$$\\end{document}8 VO2 array that can realize in-situ frequency synthesize and mix with help of compact periphery circuits. We investigate the self-oscillation based on negative differential resistance of VO2 memristors and the programmability with different driving currents and calibration resistances, demonstrating capabilities of such frequency converter for in-situ frequency synthesize and mix for 2 ~ 8 channels with frequencies up to 48 kHz for low frequency transmission link. When transmitting classical sensor data (acoustic, vision and spatial) in an end-to-end WIoT experimental setup, our VO2-based memristive frequency converter presents up to 1.45× ~ 1.94× power enhancement with only 0.02 ~ 0.21 dB performance degradations compared with conventional CMOS-based frequency converter. This work highlights the potential in solving frequency converter’s speed and energy efficiency problems in WIoT using high crystalline quality epitaxially grown VO2 and calibratable VO2-based oscillator array, revealing a promising direction for next-generation WIoT system design.

Contacts at the Nanoscale and for Nanomaterials.

Contact scaling is a major challenge in nano complementary metal-oxide-semiconductor (CMOS) technology, as the surface roughness, contact size, film thicknesses, and undoped substrate become more problematic as the technology shrinks to the nanometer range. These factors increase the contact resistance and the nonlinearity of the current-voltage characteristics, which could limit the benefits of the further downsizing of CMOS devices. This review discusses issues related to the contact size reduction of nano CMOS technology and the validity of the Schottky junction model at the nanoscale. The difficulties, such as the limited doping level and choices of metal for band alignment, Fermi-level pinning, and van der Waals gap, in achieving transparent ohmic contacts with emerging two-dimensional materials are also examined. Finally, various methods for improving ohmic contacts' characteristics, such as two-dimensional/metal van der Waals contacts and hybrid contacts, junction doping technology, phase and bandgap modification effects, buffer layers, are highlighted.

Dopant Engineering of Hafnia-Based Ferroelectrics for Long Data Retention and High Thermal Stability.

Hafnia-based ferroelectrics have gained much attention because they can be used in highly scaled, advanced complementary metal-oxide semiconductor (CMOS) memory devices. However, thermal stability should be considered when integrating hafnia-based ferroelectric transistors in advanced CMOS devices, as they can be exposed to high-temperature processes. This work proposed that doping of Al in hafnia-based ferroelectric material can lead to high thermal stability. A ferroelectric capacitor based on Al-doped hafnia, which can be used for one-transistor-one-capacitor applications, exhibits stable operation even after annealing at 900°C. Moreover, it demonstrates that the ferroelectric transistors based on Al-doped hafnia for one-transistor applications, such as ferroelectric NAND, retain their memory states for 10 years at 100°C. This study presents a practical method to achieve thermally stable ferroelectric memories capable of enduring high-temperature processes and operation conditions.

Electrical manipulation of a single electron spin in CMOS using a micromagnet and spin-valley coupling

For semiconductor spin qubits, complementary-metal-oxide-semiconductor (CMOS) technology is a promising candidate for reliable and scalable fabrication. Making the direct leap from academic fabrication to qubits fully fabricated by industrial CMOS standards is difficult without intermediate solutions. With a flexible back-end-of-line (BEOL), functionalities such as micromagnets or superconducting circuits can be added in a post-CMOS process to study the physics of these devices or achieve proofs-of-concept. Once the process is established, it can be incorporated in the foundry-compatible process flow. Here, we study a single electron spin qubit in a CMOS device with a micromagnet integrated in the flexible BEOL. We exploit the synthetic spin orbit coupling (SOC) to control the qubit via electric fields and we investigate the spin-valley physics in the presence of SOC where we show an enhancement of the Rabi frequency at the spin-valley hotspot. Finally, we probe the high frequency noise in the system using dynamical decoupling pulse sequences and demonstrate that charge noise dominates the qubit decoherence in this range.

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

Research on reliability of complementary metal oxide semiconductor integrated circuit

Complementary metal oxide semiconductor (CMOS) devices are an important part of integrated circuit (IC), but in the application process, it has many reliability problems, such as negative-bias temperature instability (NBTI), electromigration (EM), time-dependent gate oxide breakdown (TDDB), hot carrier injection (HCI), etc. These reliability problems can affect the threshold voltage and mobility of the device. In order to improve the reliability of integrated circuits, these reliability problems are systematically studied in this paper.

Fabrication of Ultrasmall Si Encapsulated in Silicon Dioxide and Silicon Nitride as Alternative to Impurity Doping

Further miniaturization of complementary metal oxide semiconductor devices based on impurity‐doped semiconductors is limited due to statistical fluctuation of the impurity concentration in very small volumes and dopant deactivation, increasing the resistance and power consumption. Based on density functional theory calculations and backed by experimental data, the nanoscale electronic structure shift induced by anions at surfaces (NESSIAS) has been described recently. It explains the structure shift of low‐doped single‐crystalline Si nanowells (Si‐NWs) with thicknesses ≤3 nm embedded in SiO2 (Si3N4) toward n‐type (p‐type) behavior. The influence of the anions is on the scale of a few nanometers, allowing for very steep p–n junctions without the drawbacks of impurity doping. The process to fabricate crystalline silicon (c‐Si) NWs embedded in SiO2 and Si3N4, starting with silicon on insulator (SOI) across 15 × 15 mm2 samples, is described. Four possible methods to fabricate Si‐NWs by thinning down single‐crystalline top‐Si of an SOI substrate are evaluated in terms of reproducibility and surface roughness.

On the Working Mechanisms of Molecules-Based Van der Waals Dielectrics.

Sb2 O3 molecules offer unprecedented opportunities for the integration of a van der Waals (vdW) dielectric and a 2D vdW semiconductor. However, the working mechanisms underlying molecules-based vdW dielectrics remain unclear. Here, the working mechanisms of Sb2 O3 and two Sb2 O3 -like molecules (As2 O3 and Bi2 O3 ) as dielectrics are systematically investigated by combining first-principles calculations and gate leakage current theories. It is revealed that molecules-based vdW dielectrics have a considerable advantage over conventional dielectric materials: defects hardly affect their insulating properties. This shows that it is unnecessary to synthesize high-quality crystals in practical applications, which has been a long-standing challenge for conventional dielectric materials. Further analysis reveals that a large thermionic-emission current renders Sb2 O3 difficult to simultaneously satisfy the requirements of dielectric layers in p-MOS and n-MOS, which hinders its application for complementary metal-oxide-semiconductor (CMOS) devices. Remarkably, it is found that As2 O3 can serve as a dielectric for both p-MOS and n-MOS. This work not only lays a theoretical foundation for the application of molecules-based vdW dielectrics, but also offers an unprecedentedly competitive dielectric (i.e., As2 O3 ) for 2D vdW semiconductors-based CMOS devices, thus having profound implications for future semiconductor industry.

Solution-Processed 2D Transition Metal Dichalcogenides: Materials to CMOS Electronics

ConspectusTwo-dimensional (2D) semiconducting transition metal dichalcogenides (TMDs) have demonstrated exceptional potential as materials for future complementary metal-oxide-semiconductor (CMOS) technology. This is primarily because of their atomic thickness and excellent electrical and mechanical properties. With advancements in fabrication technology, electronic devices based on 2D TMD materials have rapidly progressed from isolated units for scientific experimentation to integrated circuits with practical applications. Among the different production methods, the solution-processing of 2D TMD nanomaterial dispersions offers the distinct advantages of low-temperature processing and cost-effective manufacturing for large-scale flexible and wearable electronics. A wide range of 2D nanoflake inks with versatile electronic properties can be assembled into atomic-thick thin films with dangling-bond-free van der Waals interfaces between adjacent nanoflakes. Furthermore, direct printing techniques can easily integrate multifunctional devices, such as n-type and p-type transistors, into CMOS devices and more complex integrated circuits. Despite these benefits and previous accomplishments, the field of solution-processed CMOS electronics using 2D TMD semiconducting materials is in its early stages of development and requires further research. One of the current challenges is the production of scalable and high-purity 2D semiconductor mono- and few layers with large lateral sizes and narrow thickness distribution. The field-effect mobility of solution-processed 2D TMD transistors remains lower than that of the transistors manufactured using mechanical exfoliation and chemical vapor deposition methods. In particular, limited research has been conducted on solution-processed p-type 2D TMD transistors. As a result, solution-processed CMOS devices using n-type and p-type 2D TMD transistors are scarce. In this Account, we provide an overview of the recent progress in the field of solution-processed CMOS electronics employing 2D TMD materials. First, we introduce the basic liquid exfoliation methods, such as sonication-assisted exfoliation and molecular intercalation methods, that are commonly utilized to prepare 2D TMD dispersions. In addition, we discuss the production of monolayer 2D materials, which serve as the building blocks for fabricating atomic-thick thin films. Subsequently, we review the typical techniques for depositing 2D inks, including spin coating, drop casting, and inkjet printing. Furthermore, we outline the thin-film patterning process for each technique, which is crucial for integrating multifunctional materials in CMOS devices. Subsequently, we focus on the recent advancements in solution-processed 2D TMD transistors. Furthermore, we explore the various factors that can improve the performance of the devices with regard to charge transport and charge traps. Afterward, we highlight notable applications of solution-processed CMOS technology, such as logic circuits and ring oscillators. Finally, we provide an overview of the challenges and opportunities in the development of solution-processed 2D materials and the integration of multifunctional devices for the advancement of CMOS electronics. This Account aims to provide a comprehensive guide for readers, offering both a broad overview and an in-depth insight into solution-processed 2D material-based electronics, covering a wide range of topics from the preparation of 2D TMD ink to device fabrication and CMOS applications. Therefore, this Account is expected to drive further progress and advancements in this field and promote the realization of practical applications.

Control of Carrier Polarity and Schottky Barriers in Layered PdSe2 Field-Effect Transistors

Palladium diselenide (PdSe2) has been discovered as an intriguing two-dimensional (2D) semiconductor for its unique pentagonal crystalline structure, electrical and optical anisotropy, thickness-modulated band gap, robust air stability, and high carrier mobility, demonstrating great potential in field-effect transistors (FETs), photodetectors, and thermoelectric devices. Controlling the carrier polarity and electrical contact Schottky barriers is of great significance for realizing high-performance PdSe2 optoelectronic devices. Here, by combining work-function measurement and electrical transport, we observe a thickness-modulated carrier polarity transition in layered PdSe2 FETs from n-type unipolar to intrinsic ambipolar and p-type unipolar behavior by simply varying the number of layers of PdSe2. Due to the weak Fermi-level pinning in few-layer PdSe2, n-type and ambipolar FETs are achieved by contacting PdSe2 to Sc, Ti, and Pd electrodes, respectively. The Schottky barrier heights are determined by temperature-dependent transport, showing a 15 meV barrier for the Sc contact at the electron side and 62 and 93 meV barriers for Ti and Pd contacts, both at the hole side, respectively. We further demonstrate ozone-treatment-induced hole doping in PdSe2, which effectively converts the PdSe2 FETs from n-type to p-type. The doping is robust in the ambient environment over 3 months. In-plane homojunction on a PdSe2 flake is realized by selective ozone doping, demonstrating typical diode rectifying behavior. The ability to control the carrier polarity and Schottky barriers in layered PdSe2 makes this 2D semiconductor highly feasible for complementary metal-oxide semiconductor device integration and high-performance photodetectors based on atomically thin p–n junctions.

Design and Implementation of CNFET SRAM Cells by Using Multi-Threshold Technique

This paper presents a CNFET (Carbon Nano-tube FET) based MT (Multi-Threshold)-SRAM (Static Random Access Memory) design based on the leakage reduction mechanism. A multi-threshold logic is employed for reducing the leakage current during read/write operations. Here, the multi-threshold technique is used to insert the high threshold sleep control to the low threshold circuit. The insertion is performed in a serial manner. The high threshold transistors are very useful for deriving the low sub-threshold current. Meanwhile, the low threshold transistors are promising for improving the circuit performance. The high-low threshold transistor pairs are used to change the channel length by modifying the oxide thickness of the transistors. The overall implementation of the Multi-threshold-based SRAM cells are implemented with the help of CNFET in-order to avoid the short channel effect, mobility degradation which is occurred while considering the channel length below 32 nm in CMOS (Complementary Metal Oxide Semiconductor) devices. The paper clearly represents the performance improvement of the proposed SRAM cells with above-mentioned technologies.

Effect of ammonium halide salts on wet chemical nanoscale etching and polishing of InGaAs surfaces for advanced CMOS devices

Wet surface treatment of InGaAs is crucial for high-performance complementary metal-oxide semiconductor (CMOS) devices as it reduces material loss and oxide formation in the InGaAs layer. In this present study, the surface chemistries of In0.53Ga0.47As during wet chemical etching and the chemical-mechanical planarization (CMP) process in acidic (HCl/H2O2/H2O mixture) and alkaline (NH4OH/H2O2/H2O mixture) solutions were investigated. Elemental oxide formation, surface termination, and stoichiometry after the chemical etching/CMP process were investigated through X-ray photoelectron spectroscopy and atomic force microscopy. In wet chemical etching, the dissolution of the InGaAs elemental oxide was more prominent in acidic HCl mixture solutions compared to alkaline NH4OH mixture solutions. It was observed that the overall surface etching was more aggressive in acidic solution, whereas the alkaline solution provided higher surface roughness (Ra, ∼7.19 nm, scanning area of 5 μm × 5 μm) due to the lower dissolution capacity of indium oxide. The effects of the oxidizer and the slurry pH on the removal rate, Ra, and surface contamination were evaluated after the InGaAs CMP process. A high removal rate (∼110 nm/min) and considerably lower surface contamination were obtained using an alkaline slurry (pH 10). A novel InGaAs CMP slurry is developed by adding different ammonium halide salts to the alkaline slurry for improving surface roughness and removal rate. The addition of ammonium halide salts to an alkaline slurry was very effective in achieving a higher removal rate (∼175 nm/min) and smoother surface (Ra < 0.6 nm) with lower contamination during the InGaAs CMP process.

Organic Memristor with Synaptic Plasticity for Neuromorphic Computing Applications

Memristors have been considered to be more efficient than traditional Complementary Metal Oxide Semiconductor (CMOS) devices in implementing artificial synapses, which are fundamental yet very critical components of neurons as well as neural networks. Compared with inorganic counterparts, organic memristors have many advantages, including low-cost, easy manufacture, high mechanical flexibility, and biocompatibility, making them applicable in more scenarios. Here, we present an organic memristor based on an ethyl viologen diperchlorate [EV(ClO4)]2/triphenylamine-containing polymer (BTPA-F) redox system. The device with bilayer structure organic materials as the resistive switching layer (RSL) exhibits memristive behaviors and excellent long-term synaptic plasticity. Additionally, the device's conductance states can be precisely modulated by consecutively applying voltage pulses between the top and bottom electrodes. A three-layer perception neural network with in situ computing enabled was then constructed utilizing the proposed memristor and trained on the basis of the device's synaptic plasticity characteristics and conductance modulation rules. Recognition accuracies of 97.3% and 90% were achieved, respectively, for the raw and 20% noisy handwritten digits images from the Modified National Institute of Standards and Technology (MNIST) dataset, demonstrating the feasibility and applicability of implementing neuromorphic computing applications utilizing the proposed organic memristor.