Complementary Metal Oxide Semiconductor Devices Research Articles

Low-Energy Protons—Where and Why “Rare Events” Matter

Failures (or upsets) of complementary metal-oxide-semiconductor (CMOS) devices, due to direct ionization from protons, were first predicted in 1982 and subsequently realized in 2007 for low-energy (1 MeV) protons (LEPs). For terrestrial applications, secondary LEPs, generated during collision events, may cause upsets, especially in cells far away from the initial strike location than their heavier spallation-fragment cousins. However, direct ionization may be more important in space and high-altitude environments due to the large flux of primary high-energy protons impinging on nearby spacecraft (and local device) shielding. In this article, a brief review of the relevant literature will be followed by a discussion of the sensitivity to direct ionization of typical CMOS devices. It will be shown that a significant number of LEPs are generated by cosmic radiation spallation events, suggesting that track structures and exact device hit locations need to be understood and effectively modeled, especially for modern devices. Also, the rate of multiple cell upsets, and hence multiple bit upsets, in these environments will be explored, with possible mitigation techniques discussed. The published work on muons and delta electrons, in addition to LEPs, will be reviewed as potential single-event upset (SEU) sources with the future scaling of CMOS devices.

Reconfigurable logic and neuromorphic circuits based on electrically tunable two-dimensional homojunctions

Reconfigurable logic and neuromorphic devices are crucial for the development of high-performance computing. However, creating reconfigurable devices based on conventional complementary metal–oxide–semiconductor technology is challenging due to the limited field-effect characteristics of the fundamental silicon devices. Here we show that a homojunction device made from two-dimensional tungsten diselenide can exhibit diverse field-effect characteristics controlled by polarity combinations of the gate and drain voltage inputs. These electrically tunable devices can achieve reconfigurable multifunctional logic and neuromorphic capabilities. With the same logic circuit, we demonstrate a 2:1 multiplexer, D-latch and 1-bit full adder and subtractor. These functions exhibit a full-swing output voltage and the same supply and signal voltage, which suggests that the devices could be cascaded to create complex circuits. We also show that synaptic circuits based on only three homojunction devices can achieve reconfigurable spiking-timing-dependent plasticity and pulse-tunable synaptic potentiation or depression characteristics; the same function using complementary metal–oxide–semiconductor devices would require more than ten transistors. A homojunction device made from two-dimensional tungsten diselenide can be used to create circuits that exhibit multifunctional logic and neuromorphic capabilities with simpler designs than conventional silicon-based systems.

Thin film deposition research and its impact on microelectronics scaling

Throughout his career, Dr. Stephen Rossnagel and his co-workers have had a profound influence on thin film deposition. His seminal work includes the development of reactive, collimated, and ionized methods of DC and RF magnetron sputtering, as well as plasma-enhanced atomic layer deposition. Most importantly, his contributions have been widely adopted within the microelectronics community in its efforts to produce finer layers with increased uniformity and functionality. While applications span a very broad range, from complementary metal oxide semiconductor device metallization to DNA sensing, Dr. Rossnagel has also conducted fundamental investigations into microstructural effects on electronic scattering. In this manuscript, the authors will highlight some of Steve’s contributions to these areas and their continued relevance to current and future microelectronic device scaling.

Design for High Reliability of CMOS IC With Tolerance on Total Ionizing Dose Effect

As the standard complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) generates a leakage current due to ionizing radiation reacting with silicon in a radiological environment, radiation hardening of CMOS devices is being actively investigated. If a radiation-tolerant IC (RTIC) is designed, it is very important to examine the design possibility of an application specific IC (ASIC) that uses a radiation-tolerant MOS field-effect transistor (MOSFET). This study developed a new RTIC design using an I-gate structure that is more effective in terms of time, cost, and reliability than the existing RTMOSFET. Because an RTIC with an I-gate structure can be fabricated via the usual full-custom IC design process, it can be produced after its reliability is ensured based on post-layout simulation results, which are obtained by layout parasitic extraction (LPE). To realize the possibility of such fabrication, radiation-tolerant digital and analog ICs were designed and fabricated in the standard 0.18- $\mu \text{m}$ CMOS process, and an irradiation test was conducted up to a total dose of approximately 2 Mrad. Accordingly, the radiation damage in the standard IC and the radiation tolerance of the RTIC were identified. Consequently, we have proposed and verified an efficient radiation-tolerant ASIC design solution.

Progress on Germanium–Tin Nanoscale Alloys

Group IV alloys have attracted interest in the drive to create Si compatible, direct bandgap materials for implementation in complementary metal oxide semiconductor (CMOS) and beyond CMOS devices. ...

Complementary Metal‐Oxide Semiconductor and Memristive Hardware for Neuromorphic Computing

The ever‐increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes inspiration from the highly parallel, low‐power, high‐speed, and noise‐tolerant computing capabilities of the brain, may provide such a shift. Many researchers from across academia and industry have been studying materials, devices, circuits, and systems, to implement some of the functions of networks of neurons and synapses to develop neuromorphic computing platforms. These platforms are being designed using various hardware technologies, including the well‐established complementary metal‐oxide semiconductor (CMOS), and emerging memristive technologies such as SiOx‐based memristors. Herein, recent progress in CMOS, SiOx‐based memristive, and mixed CMOS‐memristive hardware for neuromorphic systems is highlighted. New and published results from various devices are provided that are developed to replicate selected functions of neurons, synapses, and simple spiking networks. It is shown that the CMOS and memristive devices are assembled in different neuromorphic learning platforms to perform simple cognitive tasks such as classification of spike rate‐based patterns or handwritten digits. Herein, it is envisioned that what is demonstrated is useful to the unconventional computing research community by providing insights into advances in neuromorphic hardware technologies.

Improving the Stability of R2R Printed 1‐Bit Code Generator through Spin‐Coated Multilayer‐Encapsulation Method

AbstractRoll‐to‐roll (R2R) printed electronic devices have great advantages for developing large scale flexible and disposable devices when compared to current Si‐based technology. For practical realization of these advantages, however, R2R printed devices need to surmount device functionality limitations, most urgently high‐power dissipation and poor device stability. To resolve both imperative challenges at once, herein, an all R2R printed complementary metal‐oxide‐semiconductor (CMOS) 1‐bit code generator with spin‐coated multilayer encapsulation method is developed. In order to print CMOS devices by an all‐R2R gravure printing method, electrical amphoteric property of the single walled carbon nanotube (SWCNT) is utilized to fabricate both p‐type and n‐type SWCNT based thin film transistors (TFTs). In addition, printable encapsulating polymeric materials (CYTOP and FG‐3650) are developed to effectively prevent H2O permeation. The resulting CMOS 1‐bit code generator is able to continuously operate for 2 h under ambient conditions without any variation in output voltage and frequency.

Curing of Aged Gate Dielectric by the Self-Heating Effect in MOSFETs

Gate dielectric damage caused by both internal and external stresses is becoming worse because of aggressive complementary metal-oxide-semiconductor (CMOS) scaling. However, conventional technologies for damage reduction using thermal annealing during fabrication have some limitations. As a result, there is a growing demand for technologies that will cure CMOS damage as a new paradigm for improving long-term reliability. This review paper reexamines self-recovery technologies, which are fully compatible with CMOS fabrication. Although self-heating has long been considered an unwanted operating side effect, it can also be favorably utilized to cure damage. Generated Joule heat arising from device operation can uniformly anneal the gate dielectric and effectively recover damage in various devices, such as conventional logic, memory, and aerospace CMOS devices, as well as thin-film transistors for displays.

Single-event-upset effect simulation of HfO<sub>2</sub>-based ferroelectric field effect transistor read and write circuits

Ferroelectric field effect transistor (FeFET) is a promising memory cell for space application. The FeFET can achieve non-destructive reading, and has the advantages of simple structure and high integration. Ferroelectric thin film’s size effect, retention performance and radiation resistance of ferroelectric thin films directly determine the performances of FeFET devices. The HfO<sub>2</sub> is widely used as a dielectric in complementary metal oxide semiconductor (CMOS) device and can solve the common integration problems for ferroelectric materials due to its CMOS compatibility. When the HfO<sub>2</sub>-based FeFETs are applied to aerospace electronics, the effects of various radiation particles need to be considered. The HfO<sub>2</sub>-based FeFET memory is still in the experimental stage, and there are no products of HfO<sub>2</sub>-based FeFET chips available from the market, so it is difficult to carry out experimental research on its single particle effect In the case of lacking the finished products of HfO<sub>2</sub>-based FeFET devices, using the device-hybrid simulation method to study the HfO<sub>2</sub>-based FeFET single-particle effect is a necessary and feasible content for the research on HfO<sub>2</sub>-based FeFET single-particle effects. In this paper, the device-circuit simulation method is used to build a read-write circuit of HfO<sub>2</sub>-based ferroelectric field-effect transistor. The change of read and write data after a single particle is incident on a ferroelectric field effect transistor memory cell and a sensitive node of a peripheral sense amplifier is studied, and the internal mechanism of read and write data fluctuation is analyzed. The results show that when high-energy particles enter into the drain of the ferroelectric memory cell in the read-write circuit, the memory cells in the “0” state generate electron-hole pairs, which accumulate inside the device, causing the gate electric field strength and ferroelectricity to increase, and the memory cell in the “1” state has a large fluctuation in the output transient pulse voltage signal due to the charge injection of the source, indicating that the ferroelectric memory cell has a good performance against particle flipping; when high-energy particles enter into the amplifier’s sensitive node, a collection current is generated, causing the amplifier in the state of reading “0” to turn on, and the output data to fluctuate. Owing to the fluctuation time being only 0.4 ns, the data does not have single-particle flipping energy under normal readout, and the HfO<sub>2</sub>-based FeFET read-write circuit has excellent resistance to single particles. When two beams of high-energy particles act on the drain of a ferroelectric memory cell successively in a time interval of 0.5 ns, the output data signal fluctuates more than in the case of a single beam of high-energy particles, and the final output voltage difference in the reading and writing “1” state becomes smaller.

Charge trapping analysis in sputtered BixSe1-x based accumulation-mode FETs

Topological materials have attracted a lot of attention in the field of beyond Complementary Metal Oxide Semiconductor (CMOS) devices. Topological Insulators (TI) have been proposed for future high electron mobility field effect transistor (FET) devices that make the physics of operation and especially the oxide-film interface extremely crucial to understand. The effects of the gate voltage on the charge trapping in TI-based FET devices are reported in this work. Sputtered BixSe1-x was chosen as the TI material. The interfacial chemistry was characterized using X-ray photoelectron spectroscopy (XPS), which shows a presence of Mg2+ and oxygen impurities. A unique hysteresis behavior was found for the gate transfer characteristics, with respect to the gate voltage. This was attributed to the charge trapping in the gate oxide and across the SiO2/BixSe1-x interface. We simulated the effects of charge fluctuations on the resistivity of the film. These devices operate under accumulation mode rather inversion mode. Application of positive gate voltage results in accumulation of electrons in the “n-type” BixSe1-x layer resulting in an increase of conductivity. In order to explain the drain current-gate voltage behavior, we used a simple polynomial model to describe the change in the device characteristics due to charge traps. The model was fitted with our experimental results. We further analyzed the gate leakage current, which showed a good match with trap-assisted tunneling (TAT) process that was used to derive trap parameters. The obtained trap parameters show the presence of ultra-deep charge traps contributing to the hysteretic behavior.

Memristive and CMOS Devices for Neuromorphic Computing.

Neuromorphic computing has emerged as one of the most promising paradigms to overcome the limitations of von Neumann architecture of conventional digital processors. The aim of neuromorphic computing is to faithfully reproduce the computing processes in the human brain, thus paralleling its outstanding energy efficiency and compactness. Toward this goal, however, some major challenges have to be faced. Since the brain processes information by high-density neural networks with ultra-low power consumption, novel device concepts combining high scalability, low-power operation, and advanced computing functionality must be developed. This work provides an overview of the most promising device concepts in neuromorphic computing including complementary metal-oxide semiconductor (CMOS) and memristive technologies. First, the physics and operation of CMOS-based floating-gate memory devices in artificial neural networks will be addressed. Then, several memristive concepts will be reviewed and discussed for applications in deep neural network and spiking neural network architectures. Finally, the main technology challenges and perspectives of neuromorphic computing will be discussed.

High-Speed Imaging Using CMOS Image Sensor With Quasi Pixel-Wise Exposure

Several recent studies on compressive video sensing realized scene capture beyond the fundamental trade-off limit between spatial resolution and temporal resolution using random space-time sampling. However, most of these studies obtained results for higher-frame-rate video that was produced in simulation experiments or using an optically simulated random sampling camera, because there are currently no commercially available image sensors with random exposure or sampling capabilities. We fabricated a prototype complementary metal-oxide-semiconductor (CMOS) image sensor with quasi pixel-wise exposure timing that can realize nonuniform space-time sampling. The prototype sensor resets exposures independently by columns and fixes these exposures by rows for each 8 × 8-pixel block. This CMOS sensor is not fully controllable the pixels and has line-dependent control, but offers greater flexibility when compared with regular CMOS or charge-coupled device sensors with global or rolling shutters. We propose a method of realizing pseudo-random sampling for high-speed video acquisition that uses the flexibility of the CMOS sensor. We reconstruct the high-speed video sequence from images produced in pseudo-random sampling using a pre-learned decoder.

Impacts of NBTI and hot-carrier stress on silicon nanowire transistor characteristics

Following the downscaling road map for planar metal–oxide–semiconductor field-effect transistors, non-planar (three-dimensional) multiple-gate architectures are becoming essential for the ultimate scaling of complementary metal–oxide–semiconductor devices. Gate-all-around (nanowire) field-effect transistors have proven to be the most suitable below-22 nm technology nodes. Hence the reliability of these devices is of great concern. Negative-bias temperature instability (NBTI) and hot-carrier degradation (HCD) are the key device reliability issues that exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) under direct-current and alternating-current stress were investigated. When stressed, the NBTI behavior in SNWTs showed fast initial degradation, quick degradation saturation and then a special recovery behavior. Along with that, the effects of hot-carrier stress on n-channel SNWTs were studied. Due to the surrounded gate structure, it was observed that the effects of HCD were significant in the nanowire transistors.

TEM investigations of gate-all-around nanowire devices

Vertically stacked gate-all-around nanowires (GAA NWs) are considered a promising architecture for ultimately scaled complementary metal oxide semiconductor devices. These are the natural evolution of the fin-shaped field effect transistor (finFET) design and enable a better electrostatic control and a higher drive current per footprint w.r.t. previous architectures. Transmission electron microscopy (TEM) analysis is employed in the development stages of these devices to investigate morphology, material diffusion, oxidation and strain in order to achieve the desired nanowires shape and size and the required performances. Nano beam diffraction and geometric phase analysis of high-resolution scanning TEM (STEM) images are used in this work to evaluate strain at the nm-scale along the nanowires at different steps of the fabrication process. Initially strained Ge layers, in the early stages of the GAA NWs fabrication, relax after the fin-reveal and source/drain etching process steps. Strain is then restored after source/drain epitaxial deposition and maintained till the NWs release. TEM analyses of these structures are particularly challenging due to the dimensions of the GAA NWs which are smaller than the thickness of a typical TEM specimen. This generates artifacts due to different materials and multiple structures overlapping in projection in TEM images. To avoid these issues, several TEM lamellae at different positions in the device and/or 3D imaging STEM/energy dispersive spectroscopy tomography are employed.

Wafer-scalable, aligned carbon nanotube transistors operating at frequencies of over 100 GHz

Wireless device technology operating in the millimetre-wave regime (30 to 300 GHz) increasingly needs to offer both high performance and a high level of integration with complementary metal–oxide–semiconductor (CMOS) technology. Aligned carbon nanotubes are proposed as an alternative to III–V technologies in such applications because of their highly linear signal amplification and compatibility with CMOS. Here we report the wafer-scalable fabrication of aligned carbon nanotube field-effect transistors operating at gigahertz frequencies. The devices have gate lengths of 110 nm and are capable, in distinct devices, of an extrinsic cutoff frequency and maximum frequency of oscillation of over 100 GHz, which surpasses the 90 GHz cutoff frequency of radio-frequency CMOS devices with gate lengths of 100 nm and is close to the performance of GaAs technology. Our devices also offer good linearity, with distinct devices capable of a peak output third-order intercept point of 26.5 dB when normalized to the 1 dB compression power, and 10.4 dB when normalized to d.c. power. Radio-frequency transistors made from aligned carbon nanotubes offer high linearity and an extrinsic cutoff frequency of over 100 GHz.

(Bi0.2Sb0.8)2Te3 based dynamic synapses with programmable spatio-temporal dynamics

Neuromorphic computing has recently emerged as a promising paradigm to overcome the von-Neumann bottleneck and enable orders of magnitude improvement in bandwidth and energy efficiency. However, existing complementary metal-oxide-semiconductor (CMOS) digital devices, the building block of our computing system, are fundamentally different from the analog synapses, the building block of the biological neural network—rendering the hardware implementation of the artificial neural networks (ANNs) not scalable in terms of area and power, with existing CMOS devices. In addition, the spatiotemporal dynamic, a crucial component for cognitive functions in the neural network, has been difficult to replicate with CMOS devices. Here, we present the first topological insulator (TI) based electrochemical synapse with programmable spatiotemporal dynamics, where long-term and short-term plasticity in the TI synapse are achieved through the charge transfer doping and ionic gating effects, respectively. We also demonstrate basic neuronal functions such as potentiation/depression and paired-pulse facilitation with high precision (>500 states per device), as well as a linear and symmetric weight update. We envision that the dynamic TI synapse, which shows promising scaling potential in terms of energy and speed, can lead to the hardware acceleration of truly neurorealistic ANNs with superior cognitive capabilities and excellent energy efficiency.

Double Negative Differential Transconductance Characteristic: From Device to Circuit Application toward Quaternary Inverter

AbstractMulti‐valued logic (MVL) computing, which uses more than three logical states, is a promising future technology for handling huge amounts of data in the forthcoming “big data” era. The feasibility of MVL computing depends on the development of new concept devices/circuits beyond the complementary metal oxide semiconductor (CMOS) technology. This is because many CMOS devices are required to implement basic MVL functions, such as multilevel NOT, AND, and OR. In this study, a novel MVL device is reported with a complementarily controllable potential well, featuring the negative differential transconductance (NDT) phenomenon. This NDT device implemented on the WS2–graphene–WSe2 van der Waals heterostructure is evolved to a double‐NDT device operating on the basis of two consecutive NDT phenomena via structural engineering and parallel device configuration. This double‐NDT device is intensively analyzed via atomic force microscopy, kelvin probe force microscopy, Raman spectroscopy, and temperature‐dependent electrical measurement to gain a detailed understanding of its operating mechanism. Finally, the operation of a quaternary inverter configured with the double‐peak NDT device and a p‐channel transistor through Cadence circuit simulation is theoretically demonstrated.

(Invited) Reaction of Aqueous Tetramethylammonium Sulfide on SiGe(100) 25% as a Function of pH

Large improvements in the performance of CMOS (complementary metal oxide semiconductor) devices are possible with nonplanar architectures, such as finFET (fin field effect transistors) and NW-FET (nanowire field effect transistors), combined with semiconductors that have higher charge mobilities than Si. Silicon germanium (SiGe) alloys are especially useful channel materials because the carrier mobility and bandgap can be tuned by changing the percentage of Ge. Integrating SiGe into CMOS technology requires an understanding of the similarities and differences between the way Si and Ge react. Tetramethylammonium sulfide (TMAS) is an aprotic source of sulfide ions (S2-). Clean SiGe(100) 25% reacted with aqueous TMAS ([(CH3)4N]2S) forming covalent Ge-S bonds based on x-ray photoelectron spectroscopy (XPS). Lowering the pH of the solution by adding aqueous HF and HCl increased the S coverage. The highest S/elemental Ge molar ratio of 0.158 was calculated based on XPS data after treatment in TMAS at a pH of 2.0-2.5. The Ge-S bond is broken and S start to desorb from the surface at 450 K based on temperature programmed desorption spectroscopy. During TMAS solution treatment, the SiGe 25% surface was oxidized, as shown by the increased O/Si molar ratio calculated from XPS data compared to a control surface. Reducing the pH of the aqueous TMAS solution reduces the amount of oxide that forms. The surface oxidation is likely due to the formation of oxidizing species in solution such as thiosulfate (S2O3 2-). The comproportionation between thiosulfate and sulfide at lower pH can explain the reason for less surface oxidation when the surface is treated with the low pH TMAS solution.

Novel design of reversible priority encoder in quantum dot cellular automata based on Toffoli gate and Feynman gate

In accordance with Moore’s law, the size of complementary metal oxide semiconductor (CMOS)-based devices keep shrinking to augment the density on the chip. This scaling influences the execution of CMOS device due to several constraints like energy dissipation and synchronization of different components of the device. In non-reversible logic gates, power loss is the major concerned. Interest in reversible logic-based circuit design is increased as it offers reduced heat dissipation. Quantum dot cellular automata (QCA) is the possible implementation platform for reversible circuits. An encoder is an important component of memory, for address decoding and encoding. In this article, reversible logic-based architecture of 4 to 2 and 8 to 3 priority encoder is proposed and implemented on QCA platform. To design the encoder circuit, a new QCA layout of Feynman gate and Toffoli gate has been employed. The proposed layout of Feynman gate and Toffoli gate outshines the existing state-of-the-art designs. Quantum cost and circuit cost estimation of those encoder circuits are also performed. QCADesigner tool has been used to validate the performance of the proposed QCA reversible encoders.

Effects of post-metallisation annealing on surface–interfacial and electrical properties of HfO2/Ge stacks modified in situ with SiO2 interfacial layer

The effects of post-metallisation annealing (PMA) at 400 °C for 30 min in an NH3 ambient on the interfacial and electrical properties of a structure consisting of a Ge substrate coated with HfO2 by atomic layer deposition with a 3-nm-thick SiO2 interfacial layer formed in situ by a sputtering technique were evaluated. X-ray diffraction and x-ray photoelectron spectroscopy analyses confirmed the crystallinity of HfO2 and chemical bonding of the HfO2/SiO2/Ge interface before and after the annealing. Clear stretch-free distinct capacitance–voltage curves were observed for the sample after the PMA. According to the electrical measurements, the sample after the PMA exhibited a large dielectric constant (k ̃ 17), low interface trap density (Dit = 1.8 × 1012 cm2 eV−1), and small oxide charge (Qeff = 2.54 × 1012 cm2 eV−1). The gate leakage current of the PMA device determined using the current–voltage curve was approximately 0.1 × 10−4 A cm−2 at Vg+ = +1 V. These results suggest that the SiO2 interfacial layer formed in situ and NH3−PMA significantly improved the structural, interfacial, and electrical characteristics of the HfO2/Ge stacks for future Ge-based complementary metal–oxide–semiconductor device applications.