Complementary Logic Inverter Research Articles

Transistor Sizing for Bias-Stress Instability Compensation in Inkjet-Printed Organic Complementary Inverters

We present a design approach to maintain a stable voltage transfer characteristic in inkjet-printed complementary organic thin-film transistor logic inverters via device sizing. We use transistor-level design to help achieve stable logic gates, so that performance is less dependent on processing conditions and materials properties that are difficult to control for inkjet-printed electronics. Despite bias-stress instability in the individual p- and n-type transistors, a stable inverter switching threshold is achieved by equalizing the magnitudes of positive and negative threshold voltage shifts. Following a typical sizing approach for complementary logic, a p- to n-transistor transconductance ratio of 0.25 places the inverter switching threshold near the center of the voltage supply range. However, we show through calculations and measured results that a ratio closer to 2.5 prevents rapid shift of the switching threshold, which is equally important for reliable inverter operation. Furthermore, we provide a design approach to size digital logic gates with arbitrary probability of output states.

(Invited) Low-Voltage Complementary Electronics from Ion Gel-Gated Vertical Van Der Waals Heterostructures

Isolation of ultrathin layered materials with disparate electronic properties has prompted their integration into van der Waals heterostructures with unique properties for electronics. By employing ion gel dielectrics, we demonstrate here low-voltage complementary circuits comprised of n-type and p-type van der Waals heterojunction vertical field-effect transistors (VFETs). The n-type and p-type VFETs were fabricated from MoS2 and WSe2 layers on graphene, respectively, with gating achieved by a top ion gel dielectric. Due to the high specific capacitance of the ion gel dielectric, the work function of the underlying graphene and consequently the energy barrier for charge injection into the MoS2 and WSe2 layers are widely tuned at low operating voltages. The resulting VFETs possess high on-state current densities (> 3000 A cm-2) and on/off current ratios (> 104) in a narrow voltage window (< 3 V). In addition to enhancing VFET device metrics at reduced operating voltages, the high specific capacitance of the ion gel dielectric allows unprecedented regimes of charge transport to be accessed including p-channel phenomena in graphene-MoS2 vertical heterostructures. Furthermore, since the ion gel-gated VFETs possess low threshold voltages, a low-power complementary logic inverter is demonstrated using n-type and p-type VFETs. Overall, these results demonstrate the feasibility of vertical van der Waals heterostructures for high-performance, low-voltage electronics.

Investigation of InP/In0.65Ga0.35As metamorphic p-channel doped-channel field-effect transistor

In this article, the device mechanism and characteristics of InP/InGaAs metamorphic p-channel field-effect transistor (FET), which has a high indium mole fraction of InGaAs channel, grown on the GaAs substrate is demonstrated. The device was fabricated on the top of the InxGa1−xP graded metamorphic buffer layer, and the In0.65Ga0.35As pseudomorphic channel was employed to elevate the transistor performance. For the p-type FET, due to the considerably large valence band discontinuity at InP/In0.65Ga0.35As heterojunction and a relatively thin as well as heavily doped pseudomorphic In0.65Ga0.35As channel between two undoped InP layers, a maximum extrinsic transconductance of 27.3 mS/mm and a maximum saturation current density of −54.3 mA/mm are obtained. Consequently, the studied metamorphic FET is suitable for the development in signal amplification, integrated circuits, and low supply-voltage complementary logic inverters.

Erratum: “High gain, low noise, fully complementary logic inverter based on bi-layer WSe2 field effect transistors” [Appl. Phys. Lett. 105, 083511 (2014)

Erratum: “High gain, low noise, fully complementary logic inverter based on bi-layer WSe2 field effect transistors” [Appl. Phys. Lett. <b>105</b>, 083511 (2014)

Symmetric complementary logic inverter using integrated black phosphorus and MoS2 transistors

The operation of an integrated two-dimensional complementary metal–oxide–semiconductor inverter with well-matched input/output voltages is reported. The circuit combines a few-layer MoS2 n-MOSFET and a black phosphorus (BP) p-MOSFET fabricated using a common local backgate electrode with thin (20 nm) HfO2 gate dielectric. The constituent devices have linear threshold voltages of −0.8 V and +0.8 V and produce peak transconductances of 16 μS μm−1 and 41 μS μm−1 for the MoS2 n-MOSFET and BP p-MOSFET, respectively. The inverter shows a voltage gain of 3.5 at a supply voltage, VDD = 2.5 V, and has peak switching current of 108 μA and off-state current of 8.4 μA (2.4 μA) at VIN = 0 (VIN = 2.5 V). In addition, the inverter has voltage gain greater than unity for VDD ≥ 0.5 V, has open butterfly curves for VDD ≥ 1 V, and achieves static noise margin over 500 mV at VDD = 2.5 V. The voltage gain was found to be insensitive to temperature between 270 and 340 K, and AC large and small-signal operation was demonstrated at frequencies up to 100 kHz. The demonstration of a complementary 2D inverter which operates in a symmetric voltage window suitable for driving a subsequent logic stage is a significant step forward in developing practical applications for devices based upon 2D materials.

Low Power Consumption Complementary Inverters with n-MoS2 and p-WSe2 Dichalcogenide Nanosheets on Glass for Logic and Light-Emitting Diode Circuits.

Two-dimensional (2D) semiconductor materials with discrete bandgap become important because of their interesting physical properties and potentials toward future nanoscale electronics. Many 2D-based field effect transistors (FETs) have thus been reported. Several attempts to fabricate 2D complementary (CMOS) logic inverters have been made too. However, those CMOS devices seldom showed the most important advantage of typical CMOS: low power consumption. Here, we adopted p-WSe2 and n-MoS2 nanosheets separately for the channels of bottom-gate-patterned FETs, to fabricate 2D dichalcogenide-based hetero-CMOS inverters on the same glass substrate. Our hetero-CMOS inverters with electrically isolated FETs demonstrate novel and superior device performances of a maximum voltage gain as ∼27, sub-nanowatt power consumption, almost ideal noise margin approaching 0.5VDD (supply voltage, VDD=5 V) with a transition voltage of 2.3 V, and ∼800 μs for switching delay. Moreover, our glass-substrate CMOS device nicely performed digital logic (NOT, OR, and AND) and push-pull circuits for organic light-emitting diode switching, directly displaying the prospective of practical applications.

Reliability study of organic complementary logic inverters using constant voltage stress

We performed constant voltage stresses with different bias conditions on all-organic complementary inverters. We found a 20% maximum variation of DC inverter parameters after a 104-s stress. However, the largest stress-induced degradation was found in the delay times, which increased by a factor as high as 7. This is mainly due to the threshold voltage variation of the p-type thin-film-transistor and the mobility reduction of the n-type thin-film transistors, which both decrease the saturation drain current.

Complementary Logic Inverters: High‐Performance Hybrid Complementary Logic Inverter through Monolithic Integration of a MEMS Switch and an Oxide TFT (Small 12/2015)

Complementary Logic Inverters: High‐Performance Hybrid Complementary Logic Inverter through Monolithic Integration of a MEMS Switch and an Oxide TFT (Small 12/2015)

High‐Performance Hybrid Complementary Logic Inverter through Monolithic Integration of a MEMS Switch and an Oxide TFT

A hybrid complementary logic inverter consisting of a microelectromechanical system switch as a promising alternative for the p-type oxide thin film transistor (TFT) and an n-type oxide TFT is presented for ultralow power integrated circuits. These heterogeneous microdevices are monolithically integrated. The resulting logic device shows a distinctive voltage transfer characteristic curve, very low static leakage, zero-short circuit current, and exceedingly high voltage gain.

High-gain subnanowatt power consumption hybrid complementary logic inverter with WSe2 nanosheet and ZnO nanowire transistors on glass.

A 1D-2D hybrid complementary logic inverter comprising of ZnO nanowire and WSe2 nanosheet field-effect transistors (FETs) is fabricated on glass, which shows excellent static and dynamic electrical performances with a voltage gain of ≈60, sub-nanowatt power consumption, and at least 1 kHz inverting speed.

Ambipolar phosphorene field effect transistor.

In this article, we demonstrate enhanced electron and hole transport in few-layer phosphorene field effect transistors (FETs) using titanium as the source/drain contact electrode and 20 nm SiO2 as the back gate dielectric. The field effect mobility values were extracted to be ∼38 cm(2)/Vs for electrons and ∼172 cm(2)/Vs for the holes. On the basis of our experimental data, we also comprehensively discuss how the contact resistances arising due to the Schottky barriers at the source and the drain end effect the different regime of the device characteristics and ultimately limit the ON state performance. We also propose and implement a novel technique for extracting the transport gap as well as the Schottky barrier height at the metal-phosphorene contact interface from the ambipolar transfer characteristics of the phosphorene FETs. This robust technique is applicable to any ultrathin body semiconductor which demonstrates symmetric ambipolar conduction. Finally, we demonstrate a high gain, high noise margin, chemical doping free, and fully complementary logic inverter based on ambipolar phosphorene FETs.

High gain, low noise, fully complementary logic inverter based on bi-layer WSe2 field effect transistors

In this article, first, we show that by contact work function engineering, electrostatic doping and proper scaling of both the oxide thickness and the flake thickness, high performance p- and n-type WSe2 field effect transistors (FETs) can be realized. We report record high drive current of 98 μA/μm for the electron conduction and 110 μA/μm for the hole conduction in Schottky barrier WSe2 FETs. Then, we combine high performance WSe2 PFET with WSe2 NFET in double gated transistor geometry to demonstrate a fully complementary logic inverter. We also show that by adjusting the threshold voltages for the NFET and the PFET, the gain and the noise margin of the inverter can be significantly enhanced. The maximum gain of our chemical doping free WSe2 inverter was found to be ∼25 and the noise margin was close to its ideal value of ∼2.5 V for a supply voltage of VDD = 5.0 V.

CMOS Inverters and P-N Junction Diodes Based on Transition Metal Dichalcogenide Monolayers

The atomically thickness and emerging large bandgap of two dimensional transition metal dichalcogenides (TMDCs) offer a high degree of electrostatic control than those of bulk forms, which provide potential applications to electronics and optoelectronics. Recent progresses of exfoliated-TMDC-based n-type or p-type transistors allow widespread device applications such as circuits, diodes and sensors [1]. However, limited sample size and efficient carrier doping system are still remained, which consequently hamper the practical utility of TMDCs for complementary devices. Towards further advances, establishing scalable preparation techniques of various TMDCs and controlling their electronic properties are highly required. One of the most powerful methods to modulate the carrier density of semiconductors is electrostatic doping by using electrolyte to form electric double layer [2]. The huge specific capacitance of electric double layer transistors (EDLTs) enables the strong depletion of donor carriers and the continuous band filling, resulting in tuning material polarities.In this study, we fabricated ion-gel-gated EDLTs using large-area TMDC monolayers, MoS2, MoSe2 and WSe2, grown by chemical vapor deposition [3-6]. The Fermi level of TMDCs can be continuously shifted by applying gate voltage, and we can induce both hole and electron transport in these devices. The hole mobility of WSe2 can be enhanced up to 90 cm2/Vs at high carrier density of 1014 cm-2, whereas the MoS2 showed electron mobility of 60 cm2/Vs. By combining MoS2 and WSe2, we demonstrated complementary logic inverters, which yielded extremely high voltage gain of 110 that is the highest value in atomically thin 2D materials. We also introduce unique techniques to form stable pn junctions in ambipolar TMDC EDLTs and investigate its optoelectronic properties.[1] Q. H. Wang, et al., Nat. Nanotechnol. 7, 699 (2012). [2] J. T. Ye, et al., Science. 338, 1193 (2012).[3] J. Pu, L.-J. Li, T. Takenobu, et al., Nano Lett. 12, 4013 (2012).[4] J.-K. Huang, T. Takenobu, L.-J. Li, et al., ACS Nano. 8, 923 (2014).[5] J. Pu, L.-J. Li, T. Takenobu, et al., Appl. Phys. Lett., 103, 23505 (2013).[6] J. Pu, L.-J. Li and T. Takenobu, Phys. Chem. Chem. Phys., 10.1039/C3CP55270E (2014).

High-Gain Inverters Based on WSe2 Complementary Field-Effect Transistors

In this work, the operation of n- and p-type field-effect transistors (FETs) on the same WSe2 flake is realized,and a complementary logic inverter is demonstrated. The p-FET is fabricated by contacting WSe2 with a high work function metal, Pt, which facilities hole injection at the source contact. The n-FET is realized by utilizing selective surface charge transfer doping with potassium to form degenerately doped n+ contacts for electron injection. An ON/OFF current ratio of >10(4) is achieved for both n- and p-FETs with similar ON current densities. A dc voltage gain of >12 is measured for the complementary WSe2 inverter. This work presents an important advance toward realization of complementary logic devices based on layered chalcogenide semiconductors for electronic applications.

Investigation of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors for logic application

DC performance of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors (DCFETs) grown on a low-cost GaAs substrate is first demonstrated. In the complementary DCFETs, the n-channel device was fabricated on the InxGa1-xP metamorphic linearly graded buffer layer and the p-channel field-effect transistor was stacked on the top of the n-channel device. Particularly, the saturation voltage of the n-channel device is substantially reduced to decrease the VOL and VIH values attributed that two-dimensional electron gas is formed and could be modulated in the n-InGaAs channel. Experimentally, a maximum extrinsic transconductance of 215 (17)mS/mm and a maximum saturation current density of 43 (−27)mA/mm are obtained in the n-channel (p-channel) device. Furthermore, the noise margins NMH and NML are up to 0.842 and 0.330V at a supply voltage of 1.5V in the complementary logic inverter application.

Ambipolar charge carrier transport in organic semiconductor blends of phthalocyanine and fullerene

AbstractAmbipolar charge carrier transport is realised in organic field‐effect transistors using mixtures of p‐conductive copper‐phthalocyanine and n‐conductive buckminster fullerene as active layer. These blends are model systems for ambipolar transport with adjustable field‐effect mobilities for electrons and holes by variation of the mixing ratio. Thereby balanced mobilities for both charge‐carrier types are possible.In this paper we discuss the variation of mobility, threshold voltage and electronic energy levels with the mixing ratio. The charge carrier mobilities are strongly reduced upon dilution of the respective conducting phase by the other species. This shows that transport of each carrier species occurs by percolation through the respective phase in the blend. A strong correlation between contact resistance and mobility indicates that carrier injection is diffusion limited. A charge redistribution in the copper‐phthalocyanine causes a hole accumulation at the organic/organic interface and affects thereby the threshold voltage for holes. By analysing the electronic structure using photoelectron spectroscopy no charge transfer was found in the ground state. The common work function of these blends changes linearly between the work functions of the neat materials. Thus a constant ionisation potential for the highest occupied molecular orbitals of the two materials is obtained.Furthermore we have fabricated ambipolar inverters using mixed organic semiconductor layers and compare their behaviour to complementary inverters consisting of discrete p‐ and n‐channel transistors. The experimental findings and concomitant simulations demonstrate the need for balanced elec‐ tron and hole mobilities in order to achieve symmetric inverter characteristics. However, they also reveal the superior performance of true complementary logic inverters towards their ambipolar pendants. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Characteristics of InGaP/InGaAs complementary pseudomorphic doped-channel HFETs

The device and inverter characteristics based on InGaP/InGaAs n- and p-channel complementary pseudomorphic doped-channel HFETs are demonstrated. Particularly, the saturation voltage of the n-channel device is substantially reduced because the two-dimensional electron gas (2DEG) is formed and modulated in the InGaAs strain channel. Experimentally, an extrinsic transconductance of 109 (11.5) mS/mm and a saturation current density of 32.5 (−27) mA/mm are obtained for the n-channel (p-channel) device. Furthermore, the noise margins NM H and NM L values are up to 1.317 and 0.28 V, respectively, at a supply voltage of 2.0 V for complementary logic inverter application.