Complementary FET Research Articles

Investigation of Novel Hybrid Channel Complementary FET Scaling Beyond 3-nm Node From Device to Circuit

Complementary FET (CFET) is a promising candidate for CMOS scaling beyond 3-nm technology node. In this article, a novel hybrid channel CFET (HC-CFET) is proposed, which takes advantage of the vertical structure and simultaneously co-optimizes the preferred high-electron/hole-mobility surface of NMOS/PMOS on one substrate. The flexible combination of nanowires (NWs) and nanosheets (NSs) in the HC-CFET allows NMOS to have (100) channel surface orientation, while PMOS has (110) channel surface orientation without increasing the footprint of CFET pillars. Parasitic-aware device to circuit design-technology co-optimization (DTCO) analysis of the HC-CFET is performed based on advanced TCAD simulation of the device and comprehensive HSPICE simulation with TCAD-calibrated compact model. At the device level, the optimization of the channel surface orientation in the HC-CFET enables both NMOS and PMOS to obtain a current gain of more than 20%. By adjusting the wafer orientation and stacking type, HC-CFET exhibits higher frequency gain and comparable energy consumption in ring oscillator (RO) than multiscreen CFET (MS-CFET) and multibridge CFET (MB-CFET). After fully considering the impact of the stacking type on the static random access memory (SRAM) cell structure, (110) wafer together with n-NW on top of p-NS stack is the preferable approach to manufacture HC-CFET, which helps balance the speed, stability, and area of the SRAM cell.

Contact Analysis of Elemental Transition Metal Electrodes for Complementary 2D-FET Applications Using MoS2 and WSe2

First principle calculations for efficient transition metal contacts with monolayer MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> are carried out for complementary device application. The four parameters analysed are exchange energy, density of states, entropy measurements, and effective potential periodicity at interface. Each characterises the electrical contact, as exchange energy establishes stable interface with minimum energy (contacts with strong bonding); density of states determines the charge polarity selection (electron or hole transport) and carrier flow rate through interfaces; entropy measurement reveal contacts with minimum phonon scattering rate (enhanced mobility); and effective potential continuity provides an alternative view of contact resistance from quantum mechanical perspective. Combining these results reveal that in specific crystallographic orientation among the 3d group: V, Cr, Co, and Ni; from 4d group: Tc, Ru, Pd, Ag and from 5d group: Ir, Pt, Au form suitable elemental electrodes for MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> complementary FET applications.

A Complementary FET (CFET)-Based NAND Design to Reduce RC Delay

Complementary FET (CFET), a transistor architecture to stack pFET-on-nFET or vice versa, is a promising option to reduce the footprint of the logic gates further. The footprint shrinkage over planar logic design inevitably aggregates routing congestion and parasitic RC in the front-end design stages. In this work, we propose the adaptation of double-cell-height design, expanding the transistors of logic gates in two rows instead of only single row connected through top metal layers. Our design effectively reduces the routing congestion and minimizes the increased routing complexity of CFET. Shorter interconnect length and lowered RC delay of NAND cells family are validated through TCAD simulation. Output capacitance is reduced significantly, and the unloaded delay time of the proposed double-cell-height NAND cell can be reduced compared to the traditional single-cell-height design.

Thermal-Aware EM Reliability for Advanced Metal Interconnects of Complementary FET

Electromigration (EM) of metal interconnects is the continuous reliability concern for high-density integration beyond 5-nm technology, especially for the buried power rails in vertically stacked device structure. In this work, EM reliability of alternative metal interconnects based on complementary FET (CFET) is investigated by kinetic Monte Carlo (KMC) method. The microscopic evolutions of void formation in power rails can be well reproduced by considering the coupled effects of thermal and stress distribution during the EM simulation. The influences of grain boundary in different metal materials on EM lifetime are analyzed to provide the optimal strategy of process integration. Thermal-aware EM reliability is further predicted, indicating the importance of self-heating on EM evaluation of power rails in CFET.

Self-heating effect on logic performance of 6T-SRAM based on CFET device

Complementary FET (CFET) devices have become emerging and promising candidates for continuing Moore’s law at sub-3 nm nodes owing to the area advantage of the N-P stacked structure, which markedly improves the integration of circuits. However, the introduction of vertical structure leads to severe thermal issues due to the self-heating effect, resulting in the degradation of the device and circuit performance. This paper mainly evaluates and analyzes the performance of the static random-access memory (SRAM) unit built using the CFET structure. The CFET-SRAM exhibits better performance than the conventional CMOS-SRAM in terms of access delay, even with the impact of self-heating. For the multi-fin-based CFET, although the total gate capacitance increases, the enhanced current improves the static noise margin significantly. However, as the number of channels expands, sheet-based CFET devices show more comprehensive superiority of area and performance.

Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS With Nanosheet FET

For the first time, by using 3-D TCAD, the advantage of using complementary FET (CFET), which has vertically stacked nanosheet nFET and pFET with shared gate, is compared to standard CMOS with nanosheet FETs in perspective of CMOS inverter performance. The comparative study on CMOS operation was performed between CFET and standard CMOS in 3-nm technology node. The results indicate that, when both devices have identical DC electrical characteristics, using CFET can increase the frequency by ~2.3% in iso-power and decrease power by ~7.3% in iso-frequency compared to the standard CMOS with separate n/pFETs while effectively reducing the area by ~55%. It is also investigated that such results are due to the approximately 4.5% low effective capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) of the CFET compared to the standard CMOS. This low C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> of CFET arises from the stacked structure, which causes the gate-fringe electric field overlap and short via pitch between nFET and pFET. Furthermore, the performance of CFET by different n/pFET separation distances, channel lengths, and widths are analyzed. This study can provide critical insight into the performance improvement by using CFET for sub 3-nm technology.

Self-Heating and Thermal Network Model for Complementary FET

In this article, we investigate the self-heating effect (SHE) of the Complementary FET (CFET) device and propose a cross-coupled thermal network model. For the investigation of thermal behavior, the intra- and inter-device crosstalk of CFET is evaluated qualitatively through the defined crosstalk coefficient. The results indicate that CFETs have more severe intra-device thermal crosstalk, almost twice that of CMOS. Moreover, the vertical structure makes the heat dissipation path of CFET devices significantly different in the two transition states (inputs “1” and “0”). Based on the thermal behavior characteristics of CFET and the necessity of high-precision and rapid prediction of thermal characteristics of the devices, a thermal network model is proposed, which can quickly respond to the heat source and be extended at the array level. In the last part, we analyze the influence of load capacitance and operating frequency on the self-heating of CFET, and SHE-related reliability lifetime is predicted based on the lattice temperature obtained from the thermal network. The prediction results show that the bias temperature instability (BTI) lifetime of CFET degrades by 84% compared with standard CMOS.

A GaN Complementary FET Inverter With Excellent Noise Margins Monolithically Integrated With Power Gate-Injection HEMTs

A GaN complementary field-effect transistor (FET) inverter monolithically integrated with power gate-injection high-electron-mobility transistors (HEMTs) was realized on a Si substrate. The GaN p-channel and n-channel logic devices and power devices were fabricated based on a p-GaN/AlGaN/GaN epi-structure. Through optimization of epi-layer thickness and doping, excellent low-level noise margin (NM_L) of 1.47 V and high-level noise margin (NM_H) of 0.98 V were achieved at a supply voltage <inline-formula> <tex-math notation="LaTeX">${V}_{\text {DD}}$ </tex-math></inline-formula> of 3 V at room temperature. A maximum current density (<inline-formula> <tex-math notation="LaTeX">${I}_{\text {D,max}}$ </tex-math></inline-formula>) of 0.36 mA/mm/220 mA/mm at <inline-formula> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> of &#x2212;3 V/3 V and a threshold voltage <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> of &#x2212;2.0 V/&#x002B;2.3 V were achieved in the p-channel and n-channel FETs, respectively. A propagation delay of an inverter stage <inline-formula> <tex-math notation="LaTeX">$\tau _{\text {pd}}$ </tex-math></inline-formula> in a ring oscillator was measured to be <inline-formula> <tex-math notation="LaTeX">$1.67~\mu \text{s}$ </tex-math></inline-formula>. The power gate-injection HEMT has an ON-resistance <inline-formula> <tex-math notation="LaTeX">${R}_{ \mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> of <inline-formula> <tex-math notation="LaTeX">$18.7~\Omega \cdot $ </tex-math></inline-formula>mm and a breakdown voltage (BV) of 900 V. These results show the great potential of the developed GaN complementary FET technology in the applications of GaN power modules.

(Invited) Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts

The epitaxial growth of group IV semiconductor materials is one of the backbones of modern IC production flows. At present nodes it is used for the Source/Drain (S/D) engineering of both p- and n-MOS high performance transistors, allowing the deposition of SiGe:B and Si:P layers with active carrier concentrations ~ 1x1021 cm-3, ensuring low contact resistivities [1]. However, with reducing device dimensions, the growing importance of contact resistance in devices remains a major concern. A significantly lower parasitic S/D resistance could also be obtained thanks to the use of epitaxial and metal wrapped-around contacts (WAC) [2]. In addition, alternatives to Si channel materials (SiGe or Ge) and new device concepts such as 3D transistor stacking, complementary FET (CFET) and gate-all-around (GAA) nanosheet devices, all considered for the upcoming technological nodes of 3 nm and below [3], require process temperatures < 500ºC.To meet these temperature requirements, epitaxial processes based on the combination of high order Si and Ge precursors are explored together with low temperature Cl2 etching. The strength of this approach has already been demonstrated by the successful implementation of Ge/SiGe stacks and Ge S/D deposited at low temperature for the production of pMOS Ge GAA devices exhibiting excellent electrostatic control at sub-30 nm gate lengths [3].In this contribution, we use advanced low temperature epitaxial processes to enable cutting-edge applications. Complex and highly strained multi stacks are pseudomorphically grown with a limited thermal budget. The compositional contrast between the different parts of the stack, combined with very sharp interfaces, allows for the selective removal of sacrificial layers and the formation of active channels being totally isolated from parasitic channels in the substrate (Fig. 1(a)). In addition, highly B (Fig. 1 (b)) or B+Ga co-doped SiGe layers are grown at temperatures down to 400ºC with an active doping concentration exceeding 1x1021 cm-3. Epitaxial WAC structures are finally demonstrated Fig. 1 (c).[1] H. Wu et al., IEDM, 819 (2018)[2] S. Chew et al., 2017 IEEE Int. Interconnect Techn. Conf. (IITC), 1 (2017)[3] E. Capogreco, et al., Symposium on VLSI Technology , T94 (2019) Fig. 1. Example applications for advanced low temperature epitaxial growth processes. (a) HAADF-STEM cross-section image of a SiGe/Si multi stack used for the fabrication of nanosheet device with integrated bottom SiN/SiCO isolation; (b) B concentration profile measured by SIMS on a SiGe:B layer grown at low temperature, resulting in a carrier concentration above ~1x1021 cm-3. (c) Low temperature SiGe:B grown on Si fins demonstrating epitaxial WAC. Figure 1

Demonstration of Monolithic Polycrystalline Diamond-GaN Complementary FET Technology for High-Temperature Applications

Demonstration of Monolithic Polycrystalline Diamond-GaN Complementary FET Technology for High-Temperature Applications

Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)

With the relentless scaling of technology nodes, the track number reduction of conventional (Conv.) cell is starting to reach its limitations due to limited routing resources, lateral p-n separations, and performance requirements. As a result, to exploit the benefits of 3-D architectures, complementary-FET (CFET) technology, which stacks P-FET on N-FET or vice versa, is proposed to release the restriction of p-n separation and reduce in-cell routing congestion by enabling p-n direct connections. However, CFET standard cell (SDC) synthesis demands a holistic reconsideration of multirow (MR) structure to maximize the cell and block-level area benefits due to limited in-cell routing tracks and routability that comes from the stacked structure and reduced cell height. In this article, we propose a satisfiability modulo theory (SMT)-based MR CFET SDC synthesis framework that simultaneously solves place-and-route to minimize the cell area by considering single-row and MR placement together. We enable explorations on upper/lower M0A/PC routing to leverage the shared-and-split structure across cell rows with the proposed MR dynamic complementary pin allocation scheme. We demonstrate that MR 2.5T CFET without and with upper/lower M0A/PC routing achieves 16.44% and 20.61% on the average reduced cell areas, respectively, compared to 3.5T CFET. Moreover, MR 2.5T CFET SDCs achieve 13.43% and 14.40% less block-level area and total wirelength on average compared to 3.5T CFET SDCs.

(Invited) Layer Transfer Technology for Stacked Multi-Channel Semiconductor-on-Insulator Platform

Continuous scaling of device dimension pushed Si channel to its physical limit, alternative high mobility channels such as (Si)Ge and (In)GaAs have been considered to replace Si to further enhance CMOS performance. In the meantime, ultrathin body (UTB) semiconductor-on-insulator is compulsory structure for improved gate control and immunity against short channel effects in the ultimately scaled high performance and low power dissipation CMOS. To realize stacked multi- channel semiconductor-on-insulator platform on current mainstream Si wafers, layer transfer technology [1-3] utilizing direct bonding and selective etching was developed to integrate (Si)Ge or (In)GaAs channels on Si, showing great potential for ultimate device structures with heterogeneous integration.Figure 1(a) is the process flow for integrating InGaAs channel onto SiGe-on-insulator (SGOI) structure utilizing layer transfer technology [4]. It started with bottom SGOI pMOSFET fabrication. The SGOI structure was realized by 2-step Ge condensation technique, resulting in Ge content of 70%. After high k metal gate process, self-aligned Ni-SiGe alloy was formed as S/D metal. Subsequently, SiO2 interlayer was deposited by CVD, followed by CMP planarization. Then, InGaAs grown on InP was directly bonded onto SiO2 and InP substrates were selectively etched away. Finally, the top InGaAsOI nMOSFET fabrication and metal interconnection completed the CMOS fabrication. Fig. 1(b) shows the cross-sectional TEM images of fabricated InGaAs/SiGe channel stacked CMOS. Well aligned top and bottom devices are seen without any distinct defects.Figures 2 is a schematic flow for fabricating Ge/Si double channel-on-insulator structure by low temperature hetero-layer bonding technology (LT-HBT). The technology starts with the preparation of donor wafers (Fig. 2(a)) for the top Ge channel layer and host wafers (Fig. 2(b)) for the bottom Si channel layer. For donor wafers, a 200-nm-thick Ge was epitaxially grown on SOI wafer by reduced pressure CVD. After CMP planarization, ALD SiO2 is deposited onto Ge. For host wafers, implantation and dopant activation were carried out, followed by chemical treatment for Si oxidation. After surface activation by room temperature chemical treatment (Fig. 2(c)), the direct wafer bonding of both SiO2 surface was performed at 200 °C in a press machine (Fig. 2(d)). Then, the Si substrate of the donor wafer was removed with deep RIE. At this time, the BOX layer of the donor wafer serves as an etch-stop layer. Subsequently, the BOX layer and thin Si layer of the donor wafer were removed selectively in HF and TMAH solution, respectively (Fig. 2(f)). To precise control the top Ge channel thickness, a series of low damage etching process was adapted to thin down Ge (Fig. 2(g)). The realized double channel structure is fully isolated with an insulating insertion layer,[5] which is very promising for realizing novel complementary FET (CFET) with minimum process steps. The cross-sectional TEM image of Ge/Si stacked channel of CFET after high k metal gate process is demonstrated in Fig. 2(h). Even more multiple stacks can be realized by using LT-HBT. A vertically stacked three-layer structure with 2 bottom Si layers and 1 top Ge layers is also demonstrated using SOI-based donor wafers in Fig. 3, indicating the highly integrated density channel structure is possible. The feasibility of layer transfer technology has been proved for multi-channel structure with high mobility channels for N2 node and beyond. Acknowledgement This work was supported by JST Japan-Taiwan Collaborative Research Program, Grant Number JPMJKB1902, Japan and the Ministry of Science and Technology under Grant Number MOST-109-2628-E-492-001-MY3, 109-2923-E-492-001-MY3, 107-2221-E-492-016-MY3.

Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT

With the relentless scaling of technology nodes, design technology co-optimization (DTCO) for the conventional (Conv.) cell structure is starting to reach its limitations due to limited routing resources, lateral p-n separations, and performance requirements. As a result, system technology co-optimization (STCO) has been proposed to exploit the benefits of 3-D architectures. Complementary-FET (CFET) technology, which stacks p-FET on n-FET or vice versa, can release the restriction of p-n separation and reduce in-cell routing congestion by enabling p-n direct connections. However, CFET standard cell (SDC) synthesis demands holistic considerations to maximize the area benefit of scaling at the block level due to the extremely limited routability that comes from the stacked structure and reduced cell height. In this article, we propose a satisfiability modulo theory (SMT)-based CFET SDC synthesis framework that simultaneously solves place-and-route to generate optimized layouts. We first demonstrate that the CFET structure achieves 10.94% and 21.27% reduction on average cell area and metal length, respectively, and 15.10% smaller block-level area compared to Conv. structure as scaling down to 3.5T architecture. For routability, the proposed constraint-based minimum pin length/minimum pin opening and objective-based edge-based pin-separation/M2 track use reduce up to 48% #DRVs at the block level compared to the previous work. Then, through extensive DTCO explorations on ground design rules and #BEOLs, 3.5T CFET SDCs achieve up to 6.50% smaller block-level areas than 4.5T CFET SDCs. Finally, with the assistance of STCO and DTCO, 3.5T CFET SDCs achieve 21.0% on average reduced block-level areas compared to 4.5T Conv. SDCs.

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

New two-terminal C-MNOS memory cells

New two-terminal nonvolatile memory cells are proposed, in which an n-channel MNOS transistor is functionally integrated with a p-channel MNOS or MOS transistor. The operational principle of both types of the cells is substantially based on the Λ (lambda)-shaped I-V Characteristic of complementary FET's. The most valuable feature of the new cells is the unipolar pulse operation of the simple diode-matrix array which can be used in a RAM mode by the use of selective writing and erasing as well as in an electrically alterable PROM mode.

A new Λ-type negative resistance device of integrated complementary FET structure

A new type of negative resistance diode having a Λ-type I-V characteristic is presented. The device is constructed by a functional integration of two complementary FET's of an n- and p-channel depletion mode. The operational principle together with some experimental results are described.

Grounded load complementary FET circuits: Sceptre analysis

The performance of grounded load complementary MOS circuits has been evaluated. It has been found that a very significant improvement in performance and reduction in circuit-area might be achieved by employing grounded load devices in portions of a system employing large-scale integrated CMOS circuits.