Compilation Phase Research Articles

A study on critical reviews on a compilation phase written by literary scholars of Chinese Qing dynasty during 19th century, focused on Chosun's Chinese poetry

A study on critical reviews on a compilation phase written by literary scholars of Chinese Qing dynasty during 19th century, focused on Chosun's Chinese poetry

Compiler verification meets cross-language linking via data abstraction

Many real programs are written in multiple different programming languages, and supporting this pattern creates challenges for formal compiler verification. We describe our Coq verification of a compiler for a high-level language, such that the compiler correctness theorem allows us to derive partial-correctness Hoare-logic theorems for programs built by linking the assembly code output by our compiler and assembly code produced by other means. Our compiler supports such tricky features as storable cross-language function pointers, without giving up the usual benefits of being able to verify different compiler phases (including, in our case, two classic optimizations) independently. The key technical innovation is a mixed operational and axiomatic semantics for the source language, with a built-in notion of abstract data types , such that compiled code interfaces with other languages only through axiomatically specified methods that mutate encapsulated private data, represented in whatever formats are most natural for those languages.

Designing and Implementing Control Flow Graph for Magic 4th Generation Language

A good compiler which implements many optimizations during its compilation phases must be able to perform several static analysis techniques such as control flow or data flow analysis. Besides compilers, these techniques are common for static analyzers as well to retrieve information from source code, for example for code auditing, quality assurance or testing purposes. Implementing control flow analysis requires handling many special structures of the target language. In our paper we present our experiences in implementing control flow graph (CFG) construction for a special 4th generation language called Magic. While we were designing and implementing the CFG for this language, we identified dierences compared to 3rd generation languages mostly because of the unique programming technique of Magic (e.g. data access, parallel task execution, events). Our work was motivated by our industrial partner who needed precise static analysis tools (e.g. for quality assurance or testing purposes) for this language. We believe that our experiences for Magic, as a representative of 4GLs, might be generalized for other languages too.

Formal verification of synchronous data-flow program transformations toward certified compilers

Translation validation was invented in the 90's by Pnueli et al. as a technique to formally verify the correctness of code generators. Rather than certifying the code generator or exhaustively qualifying it, translation validators attempt to verify that program transformations preserve semantics. In this work, we adopt this approach to formally verify that the clock semantics and data dependence are preserved during the compilation of the Signal compiler. Translation validation is implemented for every compilation phase from the initial phase until the latest phase where the executable code is generated, by proving the transformation in each phase of the compiler preserves the semantics. We represent the clock semantics, the data dependence of a program and its transformed counterpart as first-order formulas which are called clock models and synchronous dependence graphs (SDGs), respectively. We then introduce clock refinement and dependence refinement relations which express the preservations of clock semantics and dependence, as a relation on clock models and SDGs, respectively. Our validator does not require any instrumentation or modification of the compiler, nor any rewriting of the source program.

A Generic Tool for Teaching Compilers

In this paper, we propose a two-fold generic tool for compiler construction. First, it facilitates teaching compilers. Second, it constitutes a new approach for compiler construction. In addition, it enables a smooth transition from theory to practice and introduces a unified approach for the implementation of the different compiler phases. Such unification is achieved based on the representation of the compiler phases as a generic domain that is then mapped into a generic automaton. The generic automaton simulates the behavior of finite and shift-reduce automata, annotated by respective translation schemes. Thus, the tool acts as a scanner, a parser or as syntax directed translator. Without loss of generality, the proposed tool is used within a compiler-teaching framework. Comparisons with similar and well-known approaches have shown that our approach is pedagogical, conceptually simpler, requires less student efforts and more relevant to core curriculum.

Relaxed-memory concurrency and verified compilation

In this paper, we consider the semantic design and verified compilation of a C-like programming language for concurrent shared-memory computation above x86 multiprocessors. The design of such a language is made surprisingly subtle by several factors: the relaxed-memory behaviour of the hardware, the effects of compiler optimisation on concurrent code, the need to support high-performance concurrent algorithms, and the desire for a reasonably simple programming model. In turn, this complexity makes verified (or verifying) compilation both essential and challenging. We define a concurrent relaxed-memory semantics for ClightTSO , an extension of CompCert's Clight in which the processor's memory model is exposed for high-performance code. We discuss a strategy for verifying compilation from ClightTSO to x86, which we validate with correctness proofs (building on CompCert) for the most interesting compiler phases.

Safe, multiphase bounds check elimination in Java

AbstractAs part of its type‐safety regime, Java's semantics require precise exceptions at runtime when programs attempt out‐of‐bound array accesses. This paper describes a Java implementation that utilizes a multiphase approach to identifying safe array accesses. This approach reduces runtime overhead by spreading the out‐of‐bounds checking effort across multiple phases of compilation and execution: production of mobile code from source code, just‐in‐time (JIT) compilation in the virtual machine, application method invocations, and the execution of individual array accesses. The code producer uses multiple passes (including common subexpression elimination, load elimination, induction variable substitution, speculation of dynamically verified invariants, and inequality constraint analysis) to identify unnecessary bounds checks and prove their redundancy. During class‐loading and JIT compilation, the virtual machine verifies the proofs, inserts code to dynamically validate speculated invariants, and generates code specialized under the assumption that the speculated invariants hold. During each runtime method invocation, the method parameters and other inputs are checked against the speculated invariants, and execution reverts to unoptimized code if the speculated invariants do not hold. The combined effect of the multiple phases is to shift the effort associated with bounds‐checking array access to phases that are executed earlier and less frequently, thus, reducing runtime overhead. Experimental results show that this approach is able to eliminate more bounds checks than prior approaches with minimal overhead during JIT compilation. These results also show the contribution of each of the passes to the overall elimination. Furthermore, this approach increased the speed at which the benchmarks executed by up to 16%. Copyright © 2010 John Wiley & Sons, Ltd.

Intermediate Predicate Format for Design Automation Tools

This paper describes the Intermediate Predicate Format (IPF) which is used in Design Automation for complex digital hardware. Programs written in standard high-level programming languages are translated into the IPF file, using an optimizing front-end compiler phase. The IPF file is a tabular structure containing lists of Prolog language predicate facts, in the same manner as in Artificial Intelligence applications. IPF files are suitable to hold the algorithmic information, the hierarchy, the granularity, the control & data flow, the object typing and operator attributes of the original source code programs which specify the functionality of the intended designs. The syntax and semantics of the IPF predicate facts are formally defined here. The generated IPF facts are then loaded into the knowledge-base of the back-end compiler. This back-end phase is built with Prolog predicates which process the IPF facts in order to transform them into optimized state schedules. A standalone Finite State Machine, is generated from each subprogram in the designer’s original source code. In this way, high-level program code is automatically and formally transformed into custom hardware. The generated custom hardware is then implemented in VLSI technology (e.g. FPGAs or ASICs) using standard industrial ECAD tools. It is shown in the present work that compact IPF files “guide” the knowledge-base back-end compiler into quickly taking optimum decisions during mapping of the abstract source program operations into functionally equivalent digital hardware states.

A verified compiler for an impure functional language

We present a verified compiler to an idealized assembly language from a small, untyped functional language with mutable references and exceptions. The compiler is programmed in the Coq proof assistant and has a proof of total correctness with respect to big-step operational semantics for the source and target languages. Compilation is staged and includes standard phases like translation to continuation-passing style and closure conversion, as well as a common subexpression elimination optimization. In this work, our focus has been on discovering and using techniques that make our proofs easy to engineer and maintain. While most programming language work with proof assistants uses very manual proof styles, all of our proofs are implemented as adaptive programs in Coq's tactic language, making it possible to reuse proofs unchanged as new language features are added. In this paper, we focus especially on phases of compilation that rearrange the structure of syntax with nested variable binders. That aspect has been a key challenge area in past compiler verification projects, with much more effort expended in the statement and proof of binder-related lemmas than is found in standard pencil-and-paper proofs. We show how to exploit the representation technique of parametric higher-order abstract syntax to avoid the need to prove any of the usual lemmas about binder manipulation, often leading to proofs that are actually shorter than their pencil-and-paper analogues. Our strategy is based on a new approach to encoding operational semantics which delegates all concerns about substitution to the meta language, without using features incompatible with general-purpose type theories like Coq's logic.

Building the infrastructure: The effects of role identification behaviors on team cognition development and performance.

The primary purpose of this study was to extend theory and research regarding the emergence of mental models and transactive memory in teams. Utilizing Kozlowski, Gully, Nason, and Smith's (1999) model of team compilation, we examined the effect of role identification behaviors and posited that such behaviors represent the initial building blocks of team cognition during the role compilation phase of team development. We then hypothesized that team mental models and transactive memory would convey the effects of these behaviors onto team performance in the team compilation phase of development. Results from 60 teams working on a command-and-control simulation supported our hypotheses.

Language embedding and optimization in mython

Mython is an extensible variant of the Python programming language. Mython achieves extensibility by adding a quotation mechanism that accepts an additional parameter as well as the code being quoted. The additional quotation parameter takes the form of a Mython expression. Unlike other user code, Mython evaluates the quotation parameter at compile-time. The result of the compile-time expression is a function that is used to both parse the quoted code, and extend the compile-time environment. By explicitly passing the compilation environment to compile-time quotation functions, Mython's parameterized quotation allows users to inject code into the language compiler. Injected code can extend the language by modifying the compilation phases, which are visible to the compilation environment. The Mython language is realized by the MyFront compiler, a tool for translating Mython into Python byte-code modules. This paper introduces the Mython language, describes the implementation and usage of the MyFront tool, and shows how MyFront can be used to implement domain-specific optimizations using a little rewrite language.

Generalized instruction selection using SSA -graphs

Instruction selection is a well-studied compiler phase that translates the compiler's intermediate representation of programs to a sequence of target-dependent machine instructions optimizing for various compiler objectives ( e.g. speed and space). Most existing instruction selection techniques are limited to the scope of a single statement or a basic block and cannot cope with irregular instruction sets that are frequently found in embedded systems. We consider an optimal technique for instruction selection that uses Static Single Assignment ( SSA ) graphs as an intermediate representation of programs and employs the Partitioned Boolean Quadratic Problem ( PBQP ) for finding an optimal instruction selection. While existing approaches are limited to instruction patterns that can be expressed in a simple tree structure, we consider complex patterns producing multiple results at the same time including pre/post increment addressing modes, div-mod instructions, and SIMD extensions frequently found in embedded systems. Although both instruction selection on SSA-graphs and PBQP are known to be NP-complete, the problem can be solved efficiently - even for very large instances. Our approach has been implemented in LLVM for an embedded ARMv5 architecture. Extensive experiments show speedups of up to 57% on typical DSP kernels and up to 10% on SPECINT 2000 and MiBench benchmarks. All of the test programs could be compiled within less than half a minute using a heuristic PBQP solver that solves 99.83% of all instances optimally.

Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration

Multimedia and DSP applications have several computationally intensive kernels which are often off loaded and accelerated by application-specific hardware. This paper presents a speculative loop pipelining technique to overcome limitations of binary translation for hardware acceleration. Although many compilers have been developed at source level, it is desirable to translate the binary targeted to popular processors onto hardware for several practical benefits. However, the translated code can be less optimized. In particular, it is difficult to optimize memory accesses on binary to exploit pipeline parallelism since memory optimization techniques require perfect dependence information for correctness and efficiency. This information is not often available at binary level or even at the source level. Our technique synthesizes the pipeline with memory dependence speculation and postpones some phases of compilation by generating a small dependence analysis code or logic which makes use of runtime values. Such speculative optimization achieves the large amount of parallelism and does not depend on any user annotation. The experimental results show a promising speedup of up to 2.53 compared with the code in which memory accesses are not optimized in the pipeline fashion due to conservative memory analysis. In addition, we have evaluated our technique at hardware level implementation on FPGA devices and achieved comparable clock frequency and power consumption compared to a conservative method while achieving significant improvement in throughput.

Learning compiler construction by examples

In traditional compiler construction courses, each compiler phase is studied in detail before moving on to the next one. This not only places a great distance between theory and practice but also makes the students lose the big picture of the subject. We have been employing a different course format in which the subject is incrementally introduced through ten compilers of increasingly complexity. The first compiler is in fact just a syntax analyzer of a very simple language. The last one is a complete compiler of a Pascal-like language. Students of this course learn how to build compilers faster than the usual.

The embedded machine

The Embedded Machine is a virtual machine that mediates in real time the interaction between software processes and physical processes. It separates the compilation of embedded programs into two phases. The first phase, the platform-independent compiler phase, generates E code (code executed by the Embedded Machine), which supervises the timing, not the scheduling of, application tasks relative to external events such as clock ticks and sensor interrupts. E code is portable and, given an input behavior, exhibits predictable (i.e., deterministic) timing and output behavior. The second phase, the platform-dependent compiler phase, checks the time safety of the E code, that is, whether platform performance (determined by the hardware) and platform utilization (determined by the scheduler of the operating system) enable its timely execution. We have used the Embedded Machine to compile and execute high-performance control applications written in Giotto, such as the flight control system of an autonomous model helicopter.

Solving the Register Allocation Problem for Embedded Systems Using a Hybrid Evolutionary Algorithm

Embedded systems are unique in the challenges they present to application programmers, such as power and memory space constraints. These characteristics make it imperative to design customized compiler passes. One of the important factors that shape runtime performance of a given embedded code is the register allocation phase of compilation. It is crucial to provide aggressive and sophisticated register allocators for embedded devices, where the excessive compilation time can be tolerated due to high demand on code quality. Failing to do a good job on allocating variables to registers (i.e., determining the set of variables to be stored in the limited number of registers) can have serious power, performance, and code size consequences. This paper explores the possibility of employing a hybrid evolutionary algorithm for register allocation problem in embedded systems. The proposed solution combines genetic algorithms with a local search technique. The algorithm exploits a novel, highly specialized crossover operator that takes into account domain-specific information. The results from our implementation based on synthetic benchmarks and routines that are extracted from well-known benchmark suites clearly show that the proposed approach is very successful in allocating registers to variables. In addition, our experimental evaluation also indicates that it outperforms a state-of-the-art register allocation heuristic based on graph coloring for most of the cases experimented.

Methodology of hydrogeological characterization of deep carbonate aquifers as potential reservoirs of groundwater. Case of study: the Jurassic aquifer of El Maestrazgo (Castellón, Spain)

A methodology for the characterization of deep carbonate aquifers has been developed and applied to El Maestrazgo Jurassic aquifer in Castellon, Spain. Characterization of these aquifer formations, located at more than 300 m deep, consisted of a previous phase of compilation, analysis and synthesis of the existing information about the area, followed by a coordinated combination of different speciality studies: geology, stratigraphy, structural analysis, hydrogeology, hydrochemistry, geophysics and remote sensing. Geological studies included geological mapping, definition of stratigraphical units and facies and structural analysis. The aim of the hydrogeology study was to define aquifer formations, recharge area, aquifer points inventory and groundwater flow directions for the establishment of piezometric and water quality observation nets. Special techniques were applied, like thermal infrared aerial images and the evaluation of submarine groundwater discharge by means of natural radium isotopes. Hydrochemical techniques, including majority elements characterization and stable isotopes (18O, 2H and 3H) determination, allowed classifying hydrochemical facies and establishing a renewal pattern for water within the system. Geophysics was useful in determining the aquifer geometry, the features of the basement and the petrophysical characteristics of the geological formations. Preliminary results show an important tectonic complexity and the possibilities for groundwater uses in the area of study.

Tetris

The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler phases include instruction scheduling, which maximizes instruction level parallelism (ILP), and register allocation, which minimizes data spills to external memory. If ILP is maximized without considering register constraints, high register pressure may result, leading to increased spill code and reduced run-time performance. In this paper, a new register pressure reduction technique for embedded VLIW processors is presented to control register pressure prior to instruction scheduling and register allocation. By modifying the relative ordering of operations, this technique restructures code to better reduce spills. Our technique has been implemented in Trimaran, an academic VLIW compiler, and evaluated using a series of VLIW benchmarks. Experimental results show that, on average, our algorithm reduces dynamic spills and improves overall cycle counts by 6% for a VLIW architecture with 8 functional units and 32 registers versus previous spill code reduction techniques.

NATIONAL EDUCATIONAL STRATIFICATION OF DENTAL SCHOOLS IN IRAN

Background and Pupose:After two decades of expansion of universities of medical sciences and increasing the number of medical sciences students as one of the most attainable solutions for the problem of substandard status of Iranian community health, recently, quality-based policies in medical education have taken priority over most of the national health plans. We conducted this study to determine differences in the field of education between Iranian dental schools by stratifying their educational services. Method: To measure the educational performance that could be utilized to rate the schools nationwide, a benchmarking tool, consisting of about 60 indicators, was devised. Each school was asked to introduce a representative who would complete a questionnaire, which was designed to collect schools’ information. In the next step, all the divisions were visited by one of the project’s members and the school’s representative to revise and approve the data. Then, data retrieval was performed and verified at the project’s office. Finally, a special computer software was exploited to perform the final analysis. Results: There were 18 public and private dental schools nationwide, which were stratified based on their individual scores. Furthermore, all schools were also ranked in each indicator. Conclusion: This study as one of the phases of Strategy Compilation for Educational Missions of the National System of Medical Education, defines the educational strengths and weaknesses of Iranian dental schools that could be used as a measure for authorities to determine the developmental limits and current stance of these schools; and optimize their budget and facilities. Keywords:EDUCATION, DENTAL, MEDICAL, IRAN, RANKINGS, EDUCATIONAL PERFORMANCE, STRATIFICATION, SCHOOL, BENCHMARKING, RANKING.

A research C# compiler

AbstractC# is the new flagship language in the Microsoft .NET platform. C# is an attractive vehicle for language design research not only because it shares many characteristics with Java, the current language of choice for such research, but also because it is likely to see wide use. Language research needs a large investment in infrastructure, even for relatively small studies. This paper describes a new C# compiler designed specifically to provide that infrastructure. The overall design is deceptively simple. The parser is generated automatically from a possibly ambiguous grammar, accepts C# source, perhaps with new features, and produces an abstract syntax tree, or AST. Subsequent phases—dubbed visitors—traverse the AST, perhaps modifying it, annotating it or emitting output, and pass it along to the next visitor. Visitors are specified entirely at compilation time and are loaded dynamically as needed. There is no fixed set of visitors, and visitors are completely unconstrained. Some visitors perform traditional compilation phases, but the more interesting ones do code analysis, emit non‐traditional data such as XML, and display data structures for debugging. Indeed, most usage to date has been for tools, not for language design experiments. Such experiments use source‐to‐source transformations or extend existing visitors to handle new language features. These approaches are illustrated by adding a statement that switches on a type instead of a value, which can be implemented in a few hundred lines. The compiler also exemplifies the value of dynamic loading and of type reflection. Copyright © 2004 John Wiley & Sons, Ltd.