Intermediate Predicate Format for Design Automation Tools

Abstract

This paper describes the Intermediate Predicate Format (IPF) which is used in Design Automation for complex digital hardware. Programs written in standard high-level programming languages are translated into the IPF file, using an optimizing front-end compiler phase. The IPF file is a tabular structure containing lists of Prolog language predicate facts, in the same manner as in Artificial Intelligence applications. IPF files are suitable to hold the algorithmic information, the hierarchy, the granularity, the control & data flow, the object typing and operator attributes of the original source code programs which specify the functionality of the intended designs. The syntax and semantics of the IPF predicate facts are formally defined here. The generated IPF facts are then loaded into the knowledge-base of the back-end compiler. This back-end phase is built with Prolog predicates which process the IPF facts in order to transform them into optimized state schedules. A standalone Finite State Machine, is generated from each subprogram in the designer’s original source code. In this way, high-level program code is automatically and formally transformed into custom hardware. The generated custom hardware is then implemented in VLSI technology (e.g. FPGAs or ASICs) using standard industrial ECAD tools. It is shown in the present work that compact IPF files “guide” the knowledge-base back-end compiler into quickly taking optimum decisions during mapping of the abstract source program operations into functionally equivalent digital hardware states.