Compact Model Extraction Research Articles

Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach

Parameter extraction of compact transistor models is an expensive process, heavily relying on engineering knowledge and experience. To automate such a process, we propose a novel approach, Graph-based Compact Model (GCM), that integrates physical modeling and data-driven learning. GCM utilizes Graph Neural Networks (GNNs) to establish the model structure, while retaining the physicality in compact models. We implement our GCM in Verilog-A to support circuit simulations. As demonstrated with an academic 7nm FinFET PDK, the new approach automatically generates a GCM model within a minute, and achieves excellent accuracy and efficiency in SPICE.

Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors

In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN-based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.

Improved compact model extraction of statistical variability in 5 nm nanosheet transistors and applied to SRAM simulations

In this paper, we look at how artificial neural networks (ANNs) may be used to improve compact model extraction of statistical variability in 5 nm nanosheet transistors (NSTs) and how it can be applied to 6NST-static random access memory (SRAM) simulations. To begin, both the TCAD simulation platform and compact model of 3D n-type and p-type NST have been rigorously validated against the experimental data. The transfer characteristics curves of 1104 NST samples generated by metal gate granularity, random discrete dopants and line edge roughness are used to extract the important figures of merit (FoM) including ON-current (I ON), OFF-current (I OFF), threshold voltage (V TH) and subthreshold slope. Meanwhile, we can collect the main compact model parameters of these NST samples using our automatic extraction technique. Furthermore, a multi-layer ANN engine is trained to anticipate the important compact model parameters by entering FoMs, which significantly speeds up the automatic extraction. When we compare the prediction results to the genuine values, we discover that their correlation coefficients are all larger than 0.99. Finally, we simulated the 6NST-SRAM circuit and obtained its stability variation, with the help of extracted NST variability by the aforementioned speedup techniques.

High-fidelity circuit simulation of AQFP circuits through compact models extracted from layout

Adiabatic Quantum Flux Parametron (AQFP) superconductor logic circuits rely on magnetic coupling between the gate and clock and control lines to function. Circuit designers start by designing a circuit netlist, selecting parameters to fit design objectives, optimizing the netlist in simulation and then progressing to integrated circuit layout. Hand-designed netlists mostly do not contain all the mutual inductances between inductors. The lack of a complete set of mutual inductances can limit the accuracy of the designed netlist. For a circuit netlist to be an exact representation of the layout, the number of inductors should be equal to the number of fundamental cycles in the netlist graph and all inductors should be coupled. In this paper, we show that full-circuit inductance extraction of AQFP layout where self and mutual inductances are specified by the designer produces small but possibly significant errors due to mismatch between the design schematic and the layout. With compact simulation model extraction, which we added to the InductEx tool chain, a much more accurate simulation model that includes all mutual inductances can be obtained to verify circuit performance after layout. We propose compact model extraction as the final step in cell library characterisation.

The Extraction of Polyoxometalate Flash Compact Model and Corresponding Circuit Simulation

The main component of the POM flash memories is a polyoxometalates (POMs) layer which is used as the floating gate. As a competitive candidate of NAND Flash, POM flash memories attract significant interest and intensive investigations which have been conducted on modelling its physical characteristics and electrical properties. In this paper, we report the development of a specific compact model extraction strategy for POM flash memory based on BSIM4 compact model, allowing the corresponding circuit performance investigation. POM flash compact models are extracted and optimized using genetic algorithm (GA) at the three POM flash redox states. The extracted models are in good agreement with both high drain and low drain bias TCAD simulations. For the first time, the extracted compact models are applied in the circuit simulation to investigate the circuit behaviour of POM flash cells. This will provide valuable guidance for the practical design using POM flash cells.

(Invited) Versatile Compact Model and Evolutionary Parameter Extraction Method for Organic Thin-Film Transistors

Contact effects in thin-film transistors (TFTs), such as organic (OTFTs) and 2D field-effect transistors (2D-FETs), remain an important problem to be solved. The correct physio-chemical modeling of the contact regions in TFTs is necessary in order to incorporate these effects into transistor compact models [1,2]. Regarding OTFTs, much effort has been made to include contact effects into compact models, since the existence of a standard compact model, which effectively brings together the device- and system-level development, would place the OFET technology at a higher technological level [3].In this work, we present a versatile contact model, which is incorporated into a well-known generic analytical model for the current-voltage (I-V) characteristics of OTFTs, valid for all the operation regions of the transistor, including the subthreshold region [4,5]. The resulting model is complemented with an evolutionary procedure to extract the parameters that best fit experimental current-voltage characteristics [6]. Our motivation is that the combined compact model and parameter extraction method fulfils the conditions for this long expected standard compact model.The versatility of our proposal is based on the following pillars: (i) the contact model must reproduce linear, space-charge-limited and Schottky-barrier contacts [7]; and (ii) the contact model must be applied both, in transistors in which the source contact region is dominant (observed in many OTFTs), and in transistors in which drain and source contacts contribute in a similar way (mainly observed in some staggered OTFTs and 2D-FETs).In this work, we give details of how the compact model, including the contact effects, has been built from its origins [8] up to now. We also describe how the evolutionary procedure is adapted to extract the model parameters of different OTFTs, in which only the source contact, or both source and drain contact effects, limit the device performance [6, 7, 9].Finally, the compact model including contact effects and the extraction procedure mentioned above are tested successfully with coplanar and staggered OTFTs (with and without negligible drain contact effects). Our numerical calculations reproduce quite well the experimental electrical characteristics and the model parameters are extracted. The comparison of our results with other methods designed for specific TFTs confirms the validity of our standard compact model for TFTs with contact effects. Acknowledgments This work was partially financed by the Consejería de Economía y Conocimiento de la Junta de Andalucía, the Spanish “Ministerio de Ciencia, Innovación y Universidades”, and the European Regional Development Funds (ERDF), under projects A-TIC-117-UGR18 and PGC2018-098813-B-C31.

Statistical compact model extraction for skew‐normal distributions

A technique to extract statistical model parameters for skewed Gaussian process variations is proposed. Statistical compact model extraction traditionally assumes that underlying process variations are Gaussian in nature. ON currents in certain high voltage technologies, which are linear in process deviations, show skew in their distribution and hence is indicative of skew in the underlying process variations. The use of skew-normal random variables is proposed to model such variations. Artificial neural networks (ANNs) are used to empirically model the functional relation of performance on process deviations and a framework to propagate skew-normal random variables through ANNs is proposed. A non-linear optimisation problem is formulated to extract the parameters that characterise the skew-normal process variations, with constraints imposed on the objective function to penalise any deviation from Gaussian variations. Results show that the extracted parameters, when simulated, match the performance parameter targets to within 3% for both Gaussian and skewed process variations.

Automatic Extraction of Measurement-Based Large-Signal FET Models by Nonlinear Function Sampling

A new method is proposed for the accurate experimental characterization and fully automated extraction of compact nonlinear models for field-effect transistors (FETs). The approach, which leads to a charge-conservative description, is based on a single large-signal measurement under a two-tone sinusoidal wave excitation. A suitable choice of tone frequencies, amplitudes, and bias allows to adequately characterize the transistor over the whole safe operating region. The voltage-controlled nonlinear functions describing the two-port FET model can be computed over an arbitrarily dense voltage domain by solving an overdetermined system of linear equations. These equations are expressed in terms of a new nonlinear function sampling operator based on a biperiodic Fourier series description of the acquired frequency spectra. The experimental validation is carried out on a 0.25- $\mu \text{m}$ gallium nitride (GaN) on silicon carbide (SiC) high-electron-mobility transistor (HEMT) under continuous-wave (CW) and two-tone excitation (intermodulation distortion test).

Substrate Engineering of Inductors on SOI for Improvement of Q-Factor and Application in LNA

High Q-factor inductors are critical in designing high performance RF/microwave circuits on SOI technology. Substrate losses is a key limiting factor when designing inductors with high Q-factors. In this context, we report a substrate engineering method that enables improvement of quality factors of already fabricated inductors on SOI. A novel femtosecond laser milling process is utilized for the fabrication of locally suspended membranes of inductors with handler silicon completely etched. Such flexible membranes suspended freely on the BOX show up to 92 % improvement in Q-factor for single turn inductor. The improvement in Q-factor is reported on large sized inductors due to reduced parallel capacitance which allows enhanced operation of inductors at high frequencies. A compact model extraction methodology has been developed to model inductor membranes. These membranes have been utilized for the improvement of noise performance of LNA working in the 4.9 - 5.9 GHz range. A 0.1 dB improvement in noise figure has been reported by taking an existing design and suspending the input side inductors of the LNA circuit. The substrate engineering method reported in this work is not only applicable to inductors but also to active circuits, making it a powerful tool for enhancement of RF devices.

TCAD simulations and accurate extraction of reliability-aware statistical compact models

In this paper, we focus on the TCAD simulation and accurate compact model extraction of the time evolution of statistical variability in conventional (bulk) CMOS transistors, due to bias temperature instability (BTI). The 25-nm physical gate length MOSFETs, typical for 20 nm bulk CMOS technology, are used as test-bed transistors to illustrate our approach. Statistical physical simulations of fresh devices and devices at initial, middle and final stages of BTI degradation are performed and the corresponding nominal and statistical compact models are extracted using a two-stage extraction strategy. The extracted compact models not only accurately capture time evolution of the statistical distribution of the key MOSFET figures of merit, but also the complex correlations between them. An excellent agreement with the original physical TCAD simulation results provides a high degree of confidence that the extracted compact models deliver accurate representation of the operation of each device for the purposes of reliable circuit simulation and verification.

A Compact Model and Parameter Extraction Method for a Staggered OFET With Power-Law Contact Resistance and Mobility

We present a drain current model and a consistent parameter extraction method for organic field-effect transistors (OFETs) considering the gate voltage-dependent contact resistance and mobility by power-law. The physical origin of the asymptotic power-law dependence of contact resistance is elaborated based on the current crowding model. The parameters of a new model can be completely extracted without ambiguity by the proposed extraction method based on the linear fitting. Pentacene-based OFETs with the Au source/drain contact in a staggered configuration experimentally validate the proposed model and the extraction method, which further reveal the bulk resistivity as the major contribution to contact resistance.

ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress

The IARPA SuperTools program requires the development of superconducting electronic design automation (S-EDA) and superconducting technology computer-aided design (S-TCAD) tools aimed at enabling the reliable design of complex superconducting digital circuits with millions of Josephson junctions. Within the SuperTools program, the ColdFlux project addresses S-EDA and S-TCAD tool research and development in four areas: 1) RTL synthesis, architectures and verification; 2) analog design and layout synthesis; 3) physical design and test; and 4) device and process modeling/simulation and cell library design. Capabilities include, but are not limited to, the following: device level modeling and simulation of Josephson junctions, modeling and simulation of the superconducting process manufacturing processes, powerful new electrical circuit simulation, parameterized schematic and layout libraries, optimization, compact SPICE-like model extraction, timing analysis, behavioral, register-transfer-level and logic syntheses, clock tree synthesis, placement and routing, layout-versus-schematic extraction, functional verification, and the evaluation of designs in the presence of magnetic fields and trapped flux. ColdFlux consists of six research groups from four continents. Here, we present an overview of the current and planned activities related to the project and justify the design assumptions and decisions that were made to allow the development of design tools for million-gate circuits.

Modeling and Parameter Extraction of OFET Compact Models Using Metaheuristics-Based Approach

Research on the fabrication of organic field effect transistors (OFETs) has been dramatically increased in the last decade, considering their lightweight and flexible structure as well as their practical and low-cost production. In the next step of fabrication, building compact models and developing parameter extraction methods have critical importance in designing electronic circuits using fabricated OFETs. In this paper, we propose a parameter extraction approach which benefits from the power of metaheuristics. Although direct extraction tools offer analytical solutions in successive steps to extract model parameters, metaheuristics-based global optimization methods can find all parameters at once by exploring a wide range of parameters. Direct extraction tools are cumbersome and need human expertise. On the other hand, global optimization methods are very flexible, adaptive and can be automated as parameter extraction tools of any compact model. In this study, we introduce three different global optimization algorithms, namely, a genetic algorithm (GA), a hybrid artificial bee colony (h-ABC) algorithm, and bacterial foraging optimization (BFO) algorithm, for the parameter extraction. To the best of our knowledge, h-ABC and BFO algorithms have been used for the first time in extracting parameters of OFET compact models. We use two OFET compact models developed by Estrada et al. and Marinov et al. for two different datasets of OFET transistors, both having pentacene as organic semiconductor. While one of the dataset of transistor (T1) is available in literature, the dataset of the other transistor fabricated in our laboratory (T2) is generated as a new dataset. In order to tune control parameters of the developed algorithms, Taguchi's orthogonal experimental design (OED) method is used. Experimental results show that the proposed metaheuristics-based approach can extract model parameters successfully and can perform better than direct extraction methods. The studied OFET compact models fit to the experimental data with these parameters and predict similar output characteristic curves. The algorithms show a good agreement with the experimental data of T1 and T2, having normalized root-mean-square error values under 3.70%, and 8.74% for the models of Estrada et al. and Marinov et al., respectively. It is shown that h-ABC and BFO algorithms perform better than GA on average. It is also observed that the compact model by Estrada et al. performs better for both T1 and T2 compared to the model of Marinov et al.

Multiple heat path dynamic thermal compact modeling for silicone encapsulated LEDs

A new multiple heat path dynamic compact model extraction method for LED packages with silicone domes is proposed. The method enables separate characterization of the LEDs dome and the main heat path. It is based on thermal transient analysis of LED configurations with and without the dome. The heat paths de-embedding procedure proposed significantly increases accuracy of the LED thermal characterization compared to a typical singular heat path approach.The method is demonstrated with a representative mid-power LED. The results are validated with steady-state FEA. Suppressed estimation errors of the heat path evaluation are indicated.

(Invited) Process Variability for Devices at and Beyond the 7 Nm Node

Introduction Advanced CMOS devices are increasingly affected by various kinds of process variations. Whereas the impact of statistical process variations such as Random Dopant Fluctuations (RDF), see Fig. 1 (right), has for several years been discussed in numerous publications, the effect of systematic process variations which result from non-idealities of the equipment used has got much less attention, although the diversity of processes and equipment leads to many different sources of variations. Fig. 1 (left) shows an example for the effect of defocus and dose in optical lithography on the pattern size generated in the photoresist. In order to assess and minimize the impact of variations on device and chip performance, relevant systematic and statistical variations must be simulated in parallel, from equipment through process to device and circuit level. Correlations must be traced from their source to the final result. This enables variation-aware Design Technology Co-Optimization (DTCO). This topic is being addressed by the cooperative European project SUPERAID7 [1]. Approach and examples of results The SUPERAID7 project especially addresses highly three-dimensional devices as shown in Fig. 2, which are mandatory for advanced CMOS below 10nm. In turn, the development of an integrated topography simulator is one of the core activities of the project. Background tools from IISB and TU Wien for the simulation of lithography (Dr.LiTHO [2]), etching and deposition have been closely integrated, and new models for specific etching and deposition steps have been implemented. Fig. 3 gives an example for the influence of the photoresist shape, which resulted from lithography, on the structure etched into the underlying layer. Simply starting from the resist footprint would lead to erroneous results. Current multipatterning steps are considerably affected by variations in the lithography, etching and deposition steps used, with their propagation strongly depending on details of processing, device and circuit architecture, and circuit layout. For the simulation of subsequent doping steps, Sentaurus Process [3] is employed. The device structures fabricated are subsequently simulated with the variability-aware device simulator GARAND [4]. In order to meet the requirements of very small device cross sections and variations such as surface roughness, several improved physical models for confined carrier transport in nanowires are being developed. Fig. 4 shows the results of quantum mechanical calculations of the electron dynamics in presence of surface potential variations caused by surface roughness, using the so-called Wigner approach. After 400 fs evolution, the systems reach stationary states. High productivity drift-diffusion simulations employing GARAND are required to enable the large number of device simulation runs needed to investigate the impact of statistical variability, such as RDF and surface roughness. Corrections to the drift diffusion approach used are extracted from more sophisticated device modeling work, and implemented as enhancements of GARAND. Furthermore, GARAND has been extended to include the extraction of interconnect resistance and capacitance including effects of metal granularity and wire scaling, and providing SPICE-like netlists for enabling circuit simulations. Fig. 5 shows as an example of an interconnect structure for a 14 nm FinFET based double inverter used as a testbed, namely a sample metal grain granularity (left) and the electric field streamlines calculated with GARAND (right). Finally, using the novel compact model for nanowires LETI-NSP [5] and a hierarchical compact model extraction approach presented earlier [6], both the device without variations (“uniform device”) and the impact of several kinds of variations can be described. Fig. 6 shows the IDVG characteristics of a statistical ensemble of 100 nMOS devices. The overall software system is being bechmarked against experimental data of the project partner CEA/Leti. Conclusions Hierarchical variability-aware simulation spanning from equipment through process and device to circuit level is needed to assess and minimize the impact of systematical and statistical process variations on circuits and devices. Especially for highly three-dimensional devices the impact of equipment-induced variations on device topography and performance must be included. In the full presentation several examples will illustrate these effects and solutions provided by the SUPERAID7 project. Acknowledgement The research leading to these results has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 688101 SUPERAID7. The author wants to thank the contributors from CEA/Leti, Fraunhofer IISB, Glasgow University, GSS/ Synopsys, and TU Wien.

Hot electron generation under large-signal radio frequency operation of GaN high-electron-mobility transistors

In order to assess the underlying physical mechanisms of hot carrier-related degradation such as defect generation in millimeter-wave GaN power amplifiers, we have simulated the electron energy distribution function under large-signal radio frequency conditions in AlGaN/GaN high-electron-mobility transistors. Our results are obtained through a full band Monte Carlo particle-based simulator self-consistently coupled to a harmonic balance circuit solver. At lower frequency, simulations of a Class AB power amplifier at 10 GHz show that the peak hot electron generation is up to 43% lower under RF drive than it is under DC conditions, regardless of the input power or temperature of operation. However, at millimeter-wave operation up to 40 GHz, RF hot carrier generation reaches that from DC biasing and even exceeds it up to 75% as the amplifier is driven into compression. Increasing the temperature of operation also shows that degradation of DC and RF characteristics are tightly correlated and mainly caused by increased phonon scattering. The accurate determination of the electron energy mapping is demonstrated to be a powerful tool for the extraction of compact models used in lifetime and reliability analysis.

FinFET Centric Variability-Aware Compact Model Extraction and Generation Technology Supporting DTCO

In this paper, we present a FinFET-focused variability-aware compact model (CM) extraction and generation technology supporting design-technology co-optimization. The 14-nm CMOS technology generation silicon on insulator FinFETs are used as testbed transistors to illustrate our approach. The TCAD simulations include a long-range process-induced variability using a design of experiment approach and short-range purely statistical variability (mismatch). The CM extraction supports a hierarchical CM approach, including nominal CM extraction, response surface CM extraction, and statistical CM extraction. The accurate CM generation technology captures the often non-Gaussian distributions of the key transistor figures of merit and their correlations preserving also the correlations between process and statistical variability. The use of the hierarchical CM is illustrated in the simulation of FinFET-based SRAM cells and ring oscillators.

Influence of Transistors With BTI-Induced Aging on SRAM Write Performance

Write time is a critical component of memory performance, which often defines cycle time. In order to accurately predict static random access memory (SRAM) performance, it is also important to take temporal degradation effects into account. This paper investigates the influence of bias temperature instability induced transistor degradation on a dynamic write performance of 20 nm bulk CMOS SRAM. The circuit simulations are based on the comprehensive physical simulation of the aging process and on a very accurate statistical compact model extraction and generation technology. Several scenarios, which differ based on aging pattern of the cell, are investigated to identify the most important transistors and the corresponding critical aging conditions. Mismatch between the two inverters results in an imbalance of the cell, which enlarges the difference in write time between 0 and 1. Finally, we show a response surface of changes in write margin in response to different degradation levels in the ON and OFF transistors.

On the Performance of Multiobjective Evolutionary Algorithms in Automatic Parameter Extraction of Power Diodes

In this paper, a general, robust, and automatic parameter extraction of nonlinear compact models is presented. The parameter extraction is based on multiobjective optimization using evolutionary algorithms, which allow fitting of several highly nonlinear and highly conflicting characteristics simultaneously. Two multiobjective evolutionary algorithms which have been proved to be robust for a wide range of multiobjective problems <xref ref-type="bibr" rid="ref1 ref2" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> – <xref ref-type="bibr" rid="ref3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[3]</xref> , the nondominated sorting genetic algorithm II and the multiobjective covariance matrix adaptation evolution strategy, are used in the parameter extraction of a novel power diode compact model based on the lumped charge technique. The performance of the algorithms is assessed using a systematic statistical approach. Good agreement between the simulated and measured characteristics of the power diode shows the accuracy of the used compact model and the efficiency and effectiveness of the proposed multiobjective optimization scheme.

Accurate Simulation of Transistor-Level Variability for the Purposes of TCAD-Based Device-Technology Cooptimization

In this paper we illustrate how the predictive Technology Computer Aided Design (TCAD) process device simulation can be used to evaluate process, statistical, and time-dependent variability at the early stage of the development of new technology. This is critically important for the delivery of accurate early Process Design Kits, including process variability, statistical variability, time-dependent variability (degradation) and their interactions and correlations. This is also critical to the TCAD-based Design-Technology Co-Optimisation (DTCO). To accomplish this task, the fast, large area Coventor virtual fabrication platform SEMulator3D was integrated in the GoldStandradSimulations TCAD-based DTCO tool chain. Published data for Intel 22-nm FinFET technology are used to illustrate and validate the results of the TCAD process and device simulation, the compact model extraction, and the statistical circuit simulation.