Compact Circuit Model Research Articles

SolarDesign: An online photovoltaic device simulation and design platform

Abstract SolarDesign (https://solardesign.cn/) is an online photovoltaic device simulation and design platform that provides engineering modeling analysis for crystalline silicon solar cells, as well as emerging high-efficiency solar cells such as organic, perovskite, and tandem cells. The platform offers user-updatable libraries of basic photovoltaic materials and devices, device-level multi-physics simulations involving optical-electrical-thermal interactions, and circuit-level compact model simulations based on detailed balance theory. Employing internationally advanced numerical methods, the platform accurately, rapidly, and efficiently solves optical absorption, electrical transport, and compact circuit models. It achieves multi-level photovoltaic simulation technology from “materials to devices to circuits” with fully independent intellectual property rights. Compared to commercial software, the platform achieves high accuracy and improves speed by more than an order of magnitude. Additionally, it can simulate unique electrical transport processes in emerging solar cells, such as quantum tunneling, exciton dissociation, and ion migration.

Influence of Substrate on Sb2Se3/CdS Heterojunction Thin Film Solar Cells and Evaluation of Their Performance by Dark J‐V Analysis

ABSTRACTA simple binary antimony selenide (Sb2Se3) absorber is evolving as an alternative photovoltaic material in thin film solar cells because of its unique properties and easy processing. Sb2Se3 thin films having good crystalline quality are grown via versatile thermal evaporation from pre‐synthesized near stoichiometric compound material on molybdenum‐coated soda lime glass (SLG) and borosilicate glass (BG) substrates. Following the systematic characterizations on the absorber films, substrate configured Sb2Se3/CdS heterojunction devices were fabricated and their photovoltaic characteristics have been studied using current density vs. voltage (J‐V), dark J‐V modeling, external quantum efficiency and capacitance vs. voltage measurements. The power conservation efficiency values of 4.88% and 5.04% were achieved for the devices fabricated on SLG and BG substrates, respectively with deficit in open circuit voltage. The obtained values are higher in comparison to the reported device efficiencies in substrate configured Sb2Se3 solar cells, in which the absorber is prepared through thermal evaporation. To understand the loss in open circuit voltage, a compact equivalent circuit model was considered and identified the contribution of different shunt leakage paths in the devices. In addition to that, the device fabricated on the SLG was stable with minimal changes in its photovoltaic performance for a period spanning over 200 days. The results obtained are encouraging with scope for improving the device performance through interface engineering and back surface passivation strategies.

Nonvolatile logic gate and full adder based on tri-terminal oxide resistive switching devices

Today's on-chip computing power is constrained by the “memory wall” and “power wall” caused by the Von Neumann bottleneck. As a potential solution, this work has developed nonvolatile logic gates based on field-effect tri-terminal oxide resistive switching memory devices (3T-RRAM). A compact circuit model using a polynomial control source (PCS) is proposed to describe the behavior of the fabricated 3T-RRAM. The 3T-RRAM can be regarded as a nonvolatile transmission gate for constructing nonvolatile logic gates. Additionally, a full adder with input storage functionality has been designed using only eight 3T-RRAMs (four nonvolatile logic gates), and a binarized neural network (BNN) based on 3T-RRAM logic gate arrays has been proposed. This demonstrates the great potential of nonvolatile logic gates in computing-in-memory applications.

Dynamic Characterization of SynRM With Dual-Axis Hybrid Excitation Self-Commissioning

The synchronous reluctance machine (SynRM) has gained increasing attraction for future electric drive systems. The characterization of its magnetic and current dynamics is essential for high-performance model-driven control, which still remains a promising problem. In this paper, a dynamic characterization scheme for SynRM with dual axis hybrid excitation self-comissioning is proposed to characterize the magnetic and current dynamics. Inspired by separating dual-axis current variables, a compact magnetic circuit model is investigated with reciprocity analytics. Furthermore, an improved current dynamic model is derived with resulting analytical apparent and incremental inductances. On this basis, the characterized parameters involved in the magnetic circuit and current dynamic models can be accurately identified by combining the designed dual axis hybrid excitation method with effective parameter identification algorithm. The effectiveness and practicability of the proposed scheme are verified based on the development platform for commercial SynRM drive. This simple dynamic characterization scheme fits for online implementation on standard drives. Compared with the existed work, 38.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> improvement of normalized modeling accuracy for magnetic circuit can be achieved. In the meanwhile, the normalized modeling errors of apparent inductances for current dynamics are strictly less than 6.91 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> .

A Compact Circuit Model for Frequency-Selective Limiters With Strong Field Nonuniformity

A Compact Circuit Model for Frequency-Selective Limiters With Strong Field Nonuniformity

Flexible circuit mechanisms for context-dependent song sequencing.

Sequenced behaviours, including locomotion, reaching and vocalization, are patterned differently in different contexts, enabling animals to adjust to their environments. How contextual information shapes neural activity to flexibly alter the patterning of actions is not fully understood. Previous work has indicated that this could be achieved via parallel motor circuits, with differing sensitivities to context1,2. Here we demonstrate that a single pathway operates in two regimes dependent on recent sensory history. We leverage the Drosophila song production system3 to investigate the role of several neuron types4-7 in song patterning near versus far from the female fly. Male flies sing 'simple' trains of only one mode far from the female fly but complex song sequences comprising alternations between modes when near her. We find that ventral nerve cord (VNC) circuits are shaped by mutual inhibition and rebound excitability8 between nodes driving the two song modes. Brief sensory input to a direct brain-to-VNC excitatory pathway drives simple song far from the female, whereas prolonged input enables complex song production via simultaneous recruitment of functional disinhibition of VNC circuitry. Thus, female proximity unlocks motor circuit dynamics in the correct context. We construct a compact circuit model to demonstrate that the identified mechanisms suffice to replicate natural song dynamics. These results highlight how canonical circuit motifs8,9 can be combined to enable circuit flexibility required for dynamic communication.

Identification of Compact Equivalent Circuit Model for Metamaterial Structures

Identification of Compact Equivalent Circuit Model for Metamaterial Structures

A Physics-Based Analytical Formulation for the Tunneling Current Through the Base of Bipolar Transistors Operating at Cryogenic Temperatures

A physics-based analytical solution for the direct tunneling current through the base region of bipolar transistors operating at cryogenic temperatures (CTs) is derived. The obtained formulation is continuously differentiable over the entire bias region and contains only few experimentally determinable model parameters, which makes it well-suited for compact circuit modeling. Very good agreement of the new formulation with both a numerical evaluation of the tunneling current integral and experimental data of two silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) process generations is demonstrated.

Analytical subthreshold current model of the dual-material tri-gate (DMTG) MOSFET and its application for subthreshold logic gate

Multi-gate MOSFETs are considered for realizing ultra-low-power circuits due to their superior channel control capability and short channel effect (SCE) resistance. To achieve this goal, it is necessary to establish a suitable compact device circuit model for them. However, current research focuses more on single-material multi-gate MOSFET, and there is no research report on dual-material logic gates. In this work, we develop a subthreshold current model for dual-material tri-gate (DMTG) MOSFET. It is found that the gate metal close to the source can affect the subthreshold characteristics of the transistor to a greater extent. Moreover, combined with the equivalent transistor model, the noise margin (NM) model of the subthreshold inverter composed of DMTG MOSFETs is developed. The nearly equal NM can be obtained by equal NM design (END). An appropriate work function can be selected through END to obtain the optimal NM when designing the inverter. The NM under different device geometric parameters is given, and the simulation result shows that the model accuracy reaches 98%. Finally, the effect of DMTG structure on the device drain induced barrier lowering (DIBL) is given, which effectively reduces DIBL by 42%. These models still remain high accuracy when the device channel length shrink down to 20 nm, which provide the possibility for DMTG MOSFET to be effectively applied to ultra-low-power circuits.

Comprehensive Analysis of Linear and Nonlinear Equivalent Circuit Model for GaAs-PIN Diode

Comprehensive analysis of small-signal equivalent circuit models for GaAs-based PIN diodes is performed in this article. The analysis provides the equivalent circuit models for PIN diode operation in four different operation modes. A compact nonlinear equivalent circuit model has been developed which takes into account the dc/ac frequency dispersion of the diode dynamic resistance. In order to verify the validity of the proposed circuit model, the comparison between the modeled and measurement data is given, good fitting is obtained for GaAs-based PIN diode.

Comparison of Different Optimization Methods for the Microstructure of Proton Exchange Membrane Fuel Cells

Proton exchange membrane fuel cells (PEMFCs) have attracted much attention in the research and commercial sectors because they are environmental friendly and have relatively high power density compared to most other energy storage devices based on electrochemical processes. A significant part of the research on PEMFCs is related to decreasing the cost and improving the structure of PEMFCs by optimizing numerically the microstructure of these devices including the non-uniform porosity, carbon, nafion, and catalyst (i.e. platinum) distributions and the geometrical characteristics. The existing optimization techniques can generally be divided into heuristic and non-heuristic techniques. Heuristic techniques usually use stochastic approaches that search the optimization space using trial-and-error methods. Examples of such techniques include the genetic algorithm, particle swarm optimization, differential evolution, simulating annealing, harmony search, memetic algorithms, etc. These techniques can be applied to optimize a small number of design variables and often need to be used with simplified (often purely mathematic and not based on fundamental physics) models, such as compact, reduced-order models, or equivalent circuit models. On the other hand, non-heuristic techniques are deterministic and often require evaluating the gradient of the objective function. In general, these techniques have local convergence and their rate of convergence can be increased, using second-order derivatives such as the Hessian matrix, or taking advantage of the particular functional form of the objective function. Non-heuristic techniques usually require between a few tens of iterations to optimize the objective function compared to heuristic techniques which require at least tens of thousands of iterations.In this presentation we will make a thorough critical review of the different optimization methods used in the literature for PEMFCs. In additional, we will present the results of our efforts to develop a full-cell optimization algorithm for PEMFCs using the adjoint method [1-3]. The advantages and disadvantages of different methods, including the adjoint method, will be discussed in detail and examples of sample simulations results will be presented.

Bonding wire interconnection de-embedding for GaN high electron mobility transistor loadpull measurement with fixture.

Test fixtures with high power capacity and an impedance matching network are generally chosen for measurements of high-power gallium nitride high electron mobility transistors. To make interconnection of the test fixtures and devices under test, wire bonding is an effective assembly method. Bonding wires become dominant parasitic elements, especially in the S parameter measurement and loadpull measurement, which should be taken into account and accurately de-embedded for device measurements and modeling. In this paper, test fixtures and through-reflect-line calibration kits are designed to achieve the S parameter measurements of the bonding wire with a vector network analyzer. Equivalent inductances of the bonding wire can be obtained with the electromagnetic simulation model and compact circuit model proposed based on the test fixture. The good agreement of the equivalent inductances extracted with the test fixture and models verified that the way to characterize bonding wire interconnection is effective and accurate. Cree's CGHV1J006D is chosen to take the S parameter measurement for proving the accurate model of the bonding wire. Finally, the equivalent inductance of the 2mm gate-width transistor is obtained with the electromagnetic model. The drain impedance is accurately calculated after the loadpull measurement with bonding wire effects de-embedded, which matches the loadline theory.

Optimal Design and Noise Analysis of High-Performance DBR-Integrated Lateral Germanium (Ge) Photodetectors for SWIR Applications

This work presents the high-performance Si/SiO2 distributed Bragg reflector (DBR)-integrated lateral germanium (Ge) p-i-n photodetectors (PDs) for atmospheric gas sensing and fiber-optic telecommunication networks in the short-wave infrared (SWIR) regime. In addition, this study also proposes an optoelectronic compact small-signal noise equivalent circuit model (SSNECM) of the designed device to compute the noise performance at the detectors&#x2019; output. Various figure-of merits including current under dark and illumination, responsivity, detectivity, bandwidth, and the noise of the proposed device are estimated at the room temperature (RT) for an incident optical power of 0.5 &#x03BC;W. Furthermore, the impact of width and height scaling on dark current, responsivity, and bandwidth are investigated to optimize the proposed device. The validation of the proposed model is done by comparing various parameters including dark current, responsivity, and detectivity of the designed device with other Ge PDs. The estimated results show the reduced trade-off between responsivity and bandwidth of the designed device. At &#x03BB;=1550 nm, the proposed device achieves a high detectivity and SNR of &#x003E;2&#x00D7;1011Jones and 120 dB (at 3 THz), respectively, with the bias voltage of -2V. These encouraging results pave the path for the future development of low-noise and high-speed detectors.

Memoryless linearity in undoped and B-doped graphene FETs: A relative investigation to report improved reliability

In this work, reliability of boron-doped graphene field effect transistor (GFET) is examined by modeling the effect of doping in terms of linearity performance metrics. The key potential (VN) induced in B doped GFET is analytically modeled for various B doping concentrations. An accurate compact equivalent circuit model integrated with VN for B doped GFET is proposed to investigate the effects of memoryless nonlinearity on transconductance. The proposed equivalent circuit model is verified with the simulated results of an industry standard circuit simulation tool. The fundamental figures of merit (FOMs) such as second and third order harmonic distortion terms (HD2 and HD3), gain compression point (Ain, 1dB), second and third order intermodulation distortion terms (IM2 and IM3), second and third order input intercept points (AIIP2 and AIIP3) are mathematically modeled for doped GFET to examine the linear behaviour of the device. In addition to that, these FOMs are investigated with respect to various B doping concentrations, applied small signal amplitude, and gate-oxide capacitance. The proposed model is compatible and predicting accurate results for both B doped and undoped GFET. The simulation results are having excellent agreement with the mathematical model, which are also compared with undoped GFET and conventional MOSFET. It is also noticed that by doping the graphene sheet with boron significantly induces bandgap in it and hence enhances the linear behaviour of the B doped GFET. Hence, reliability of doped GFET is improved while comparing with undoped GFET and promises highly desirable linearity requirement in analog/RF applications.

Characterization of Tiled Architecture for C-Band 1-Bit Beam-Steering Transmitarray.

A new implementation of a beam-steering transmitarray is proposed based on the tiled array architecture. Each pixel of the transmitarray is manufactured as a standalone unit which can be hard-wired for specific transmission characteristics. A set of complementary units, providing reciprocal phase-shifts, can be assembled in a prescribed spatial phase-modulation pattern to perform beam steering and beam forming in a broad spatial range. A compact circuit model of the tiled unit cell is proposed and characterized with full-wave electromagnetic simulations. Waveguide measurements of a prototype unit cell have been carried out. A design example of a tiled 10 × 10-element 1-bit beam-steering transmitarray is presented and its performance benchmarked against the conventional single-panel, i.e., unibody, counterpart. Prototypes of the tiled and single-panel C-band transmitarrays have been fabricated and tested, demonstrating their close performance, good agreement with simulations and a weak effect of fabrication tolerances. The proposed transmitarray antenna configuration has great potential for fifth-generation (5G) communication systems.

A Compact and Robust Technique for the Modeling and Parameter Extraction of Carbon Nanotube Field Effect Transistors

Carbon nanotubes field-effect transistors (CNTFETs) have been recently studied with great interest due to the intriguing properties of the material that, in turn, lead to remarkable properties of the charge transport of the device channel. Downstream of the full-wave simulations, the construction of equivalent device models becomes the basic step for the advanced design of high-performance CNTFET-based nanoelectronics circuits and systems. In this contribution, we introduce a strategy for deriving a compact model for a CNTFET that is based on the full-wave simulation of the 3D geometry by using the finite element method, followed by the derivation of a compact circuit model and extraction of equivalent parameters. We show examples of CNTFET simulations and extract from them the fitting parameters of the model. The aim is to achieve a fully functional description in Verilog-A language and create a model library for the SPICE-like simulator environment, in order to be used by IC designers.

An improved 220‐GHz RF CMOS compact equivalent circuit model considering magnetic coupling effect

AbstractIn this study, an improved RF CMOS transistor compact equivalent circuit model is presented. Due to the finite resistivity of the substrate, the magnetic coupling effect between the interconnection line and the substrate affects the signal propagation at mm‐wave frequency range. To characterize transistors in the terahertz band, a sophisticated network is introduced to represent the magnetic field of interconnection lines and substrate image current. In addition, the parameters of the proposed model are extracted by an analytical method. By comparison with the reported model, the proposed model can significantly improve the phase accuracy. The comparison of calculation results and experimental data shows that the proposed model can well characterize the transistor up to 220 GHz.

A Compact High-Efficient Equivalent Circuit Model of Multi-Quantum-Well Vertical-Cavity Surface-Emitting Lasers for High-Speed Interconnects

Due to their low power consumption, high modulation speed, and low cost, vertical-cavity surface-emitting lasers (VCSEL) dominate short-reach data communications as the light source. In this paper, we propose a compact equivalent circuit model with noise effects for high-speed multi-quantum-well (MQW) VCSELs. The model comprehensively accounts for the carrier and photons dynamisms of a MQW structure, which includes separate confinement heterostructure (SCH) layers, barrier (B) layers, and quantum well (QW) layers. The proposed model is generalized to various VCSEL designs and accommodates a flexible number of quantum wells. Experimental validation of the model is performed at 25 Gb/s with a self-wire-bonded 850 nm VCSEL.

A Low-Voltage Si-Ge Avalanche Photodiode for High-Speed and Energy Efficient Silicon Photonic Links

Silicon-germanium (Si-Ge) avalanche photodiodes (APDs) have large gain bandwidth product (GBP) and low excess noise due to the low impact ionization coefficient ratio of silicon. Optical receivers using APDs are able to achieve high-speed and energy efficient optical transceiver systems. We demonstrate a waveguide Si-Ge APD with low breakdown voltage of −10 V, achieving 60 Gb/s PAM4 successfully. A compact APD circuit model was constructed to allow photonic devices and transceiver circuitry co-design. The APD receiver has achieved −16 dBm sensitivity at 50 Gb/s PAM4 with a bit error rate (BER) of 2.4 $\times \,10^{-4}$ . The sensitivity of APD receivers changes with the multiplication gain. In our analysis, compared to a PIN PD receiver the APD receiver operating at optimum gain can obtain $\sim$ 8 dB more sensitivity for NRZ signaling at $ 50 Gb/s and 3–4 dB more sensitivity for PAM4 signaling at 50–100 Gb/s. Also, the APD receiver operating at optimum gain can reduce power consumption by $\sim\!\text{10}\%$ at PAM4 data rates of 50 Gb/s and $\sim\!\text{15}\%$ at 100 Gb/s in a silicon carrier-depletion microring modulator based WDM photonic link.

A Compact Model for Si-Ge Avalanche Photodiodes Over a Wide Range of Multiplication Gain

Silicon-germanium (Si-Ge) avalanche photodiodes (APDs) have superior gain bandwidth product due to the low impact ionization ratio of silicon. To enable efficient optical transceiver systems, cosimulation environments are essential for optimization of optical devices and transceiver circuitry. A compact Si-Ge APD circuit model, which captures both electrical and optical dynamics over a wide range of multiplication gain, is presented. This model includes effects of carrier transit time, avalanche buildup time and electrical parasitics. Model parameters are extracted by small-signal measurement and impulse response measurement where three gain regimes are discussed corresponding to the different mechanisms of carrier transit time and electrical parasitics. Simulated and measured bandwidth versus gain have a good agreement for APD multiplication gains from M = 1 to M = 17. Excellent matching between simulated and measured 25 Gb/s eye diagrams at M = 2 and M = 5.9 is achieved.