Commutation Loop Research Articles

Advanced gate driving concepts and switching optimization for SiC semiconductors

Silicon carbide (SiC) MOSFETS are increasingly favoured in power electronics for their improved properties compared to silicon-based counterparts, such as IGBTs. Their ability to operate at higher switching frequencies and execute faster switching transients is notable. However, these features also raise significant concerns with electromagnetic interference (EMI). To exploit the full capabilities of SiC-based technology, meticulous design strategies encompassing the power stage, commutation loop, and gate drive are essential. This paper conducts a comprehensive review of existing gate drive techniques aimed at enhancing the performance of SiC devices. Moreover, this study introduces an innovative approach for optimizing switching processes through the use of active gate drivers (AGD). By pre-mapping the gate-source voltage profiles for different conditions (such as load current, temperature, and DC-link voltage), it is possible to achieve a significantly improved switching trajectory. This optimization process can be applied on a cycle-by-cycle basis in practical scenarios. Herein, pre-mapping and optimization have been experimentally confirmed in a half-bridge configuration. Through simulation, it is demonstrated that optimizing the switching trajectory can lead to a balanced compromise between EMI and switching losses, showcasing the potential for significant performance enhancements in SiC device operation.

A Family of Si and SiC Devices-Based Short Commutation Loop Hybrid-NPC Rectifiers

A Family of Si and SiC Devices-Based Short Commutation Loop Hybrid-NPC Rectifiers

On performance evaluation of high‐power, high‐bandwidth current measurement technologies for SiC switching devices

AbstractSilicon carbide (SiC) power metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) switch at an unprecedented speed, even at high currents. For accurate dynamic characterization, current sensors must measure high currents at a high bandwidth. Moreover, at high switching speeds, parasitic impedances in the commutation loop become critical. To ensure high‐accuracy measurements, the current sensor insertion impedance must be minimal. Here, a two‐step current sensor evaluation method is proposed. This method serves the characterization and suitability assessment of high‐power, high‐bandwidth current sensors for fast‐switching applications using SiC power MOSFETs. Conducting a small‐ and a large‐signal transmission behaviour analysis separately results in holistic information about the current sensor behaviour in both time and frequency domain. The proposed method is validated using four commercially available current sensors that are widely used for SiC power MOSFET characterization. The work concludes transferring the knowledge derived in the conducted experiments to a practical, application‐oriented sensor selection guide.

Investigation of a Low-Speed Commutation Voltage Shock Problem in Three-Level ANPC Inverter with Hybrid Modulation Mode

With the development of the photovoltaic industry; there will be an increasing demand for efficient, high-power density, and low-cost grid interface converters. Compared with two-level inverters, multilevel inverters have the following advantages: (1) lower device voltage ratings; (2) better output filtering spectrum; (3) lower electromagnetic interference (EMI) noise; and (4) higher switching speed capability. However, the complex switching circuit of the multilevel inverter will bring more parasitic inductance, resulting in severe switching overvoltage (ringing). Especially in order to reduce the cost of the inverter, using the long-loop modulation mode, the commutation loop will introduce more parasitic inductance, which will make the overvoltage more serious. Consider that commonly used overvoltage absorption schemes are effective only for overvoltage or suppression of oscillations. Therefore, a new overvoltage absorption circuit is proposed in this paper, which can not only alleviate the overvoltage and ringing phenomena but also suppress the effect of voltage jumps during low-frequency switching on high-frequency input voltage. This overvoltage absorption circuit is characterized by low overvoltage, fast ringing damping, and minimum capacitance. Experiments and simulations are conducted to verify the effectiveness of this overvoltage absorption circuit using a three-level ANPC inverter as a prototype. The results show that the proposed overvoltage absorption circuit can significantly reduce the overvoltage level, shorten the oscillation time, and reduce the voltage difference between the upper and lower DC bus capacitors.

Online Junction Temperature Estimation Method for SiC MOSFETs Based on the DC Bus Voltage Undershoot

Silicon carbide (SiC) power devices are promising in industrial applications. Junction temperature monitoring is greatly significant for improving the reliability of devices and systems. However, state-of-the-art SiC MOSFET junction temperature estimation methods generally have drawbacks of low resolution, difficult measurement, and complicated installation. In this article, a novel junction temperature estimation for SiC MOSFETs based on the dc bus voltage undershoot is proposed. The correlation between junction temperature and current change rate is analyzed and verified by experiments. The current change rate of each SiC MOSFET can be measured via the dc bus voltage undershoot because of the stray inductance of the bus commutation loop. The undershoot of the dc bus voltage during the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> transient displays a linear dependence on the junction temperatures of the corresponding SiC MOSFET. Hence, the dc bus voltage undershoot can be utilized for monitoring the junction temperatures of two SiC MOSFETs in the half-bridge. Besides, practical implementation and estimation errors are presented. The method proposed has high accuracy and resolution for junction temperature monitoring. Besides, the method proposed can reduce the complexity, size, and cost of the monitoring circuit. Moreover, the method proposed is noninvasive and easy to install. It is promising for SiC MOSFET junction temperature monitoring in practical applications.

Modulation Strategy for Suppressing Peak Voltage Spikes of SiC-MOSFETs During ANPC Commutation

After active neutral point clamped(ANPC) adopts SiC-MOSFETs, SiC-MOSFETs are easily damaged due to the excessive peak voltage. This paper establishes a single-phase parasitic inductance model of ANPC based on the SiC-MOSFET half-bridge modules. Then, based on this model, the cause of peak voltage on SiC-MOSFETs during ANPC commutation is analyzed. Finally, a short-loop commutation modulation strategy is proposed under the full working conditions of ANPC. The modulation strategy considers the influence of modulation carriers selection and dead time on ANPC commutation and optimizes the ANPC commutation loop to suppress the overvoltage on SiC-MOSFETs during ANPC commutation.

Commutation Behavior and Stray Inductance Analysis of a FC-3L-BDC Phase-Leg PEBB

The bidirectional dc-dc converter is a critical component for extending the use of renewable energy and improving the efficiency of high-power electronic systems. This paper presents the analysis of the stray inductance of a commutation loop and the commutation behavior of IGBT devices in a flying capacitor three-level bidirectional DC-DC converter (FC-3L-BDC) phase-leg power electronic building block (PEBB). An FC-3L-BDC phase-leg PEBB was designed as an example, which can be used to build 400 kW to MW-grade light rail train chargers, battery energy storage interface converters, or metro regenerative braking energy recovery converters with a single PEBB or several PEBBs interleaved parallel. In order to optimize the stray inductance of commutation paths and realize snubberless operation, a five-layer laminated bus bar was carefully designed, and the stray inductance of the bus bar was extracted by three-dimensional finite element analysis simulation. To obtain higher accuracy, the stray inductances of IGBT devices and capacitors were extracted from the test instead of their datasheets. Then, the accuracy of the commutation loop stray inductance analysis method was verified by practical experiments. The impact of the stray inductance of the commutation loop on the commutation behavior of IGBT devices was analyzed, and the switching characteristics of IGBT devices were measured under maximum DC-link voltage and entire current rating range at the temperatures of −40 °C, 25 °C, and 150 °C, respectively, finding that neither the excessive turn-off overvoltage of IGBTs nor the snappy reverse recovery of FWDs was observed.

GaN-Based Multichip Half-Bridge Power Module Integrated on High-Voltage AlN Ceramic Substrate

Power electronic systems employing wide-bandgap GaN transistors promise high efficiency operation and power density but require minimized parasitic circuit elements and an effective cooling concept. This article presents a half-bridge module integrating two 600 V/170 mΩ gallium nitride (GaN) high-electron mobility transistors with their gate drive stages and a fraction of the dc-link capacitance on a patterned multilayer polycrystalline AlN-substrate. The high-voltage isolation at a layer distance of 10 μm and a dense chip-by-chip integration on the GaN half-bridge module enable a compact lateral commutation loop design combined with improved cooling capability of the power transistors. Consequently, the GaN half-bridge module allows for higher load currents at lower device temperature while most parasitic circuit elements are reduced compared to a conventional printed circuit board (PCB) design. The parasitic circuit elements of the GaN half-bridge module and a reference four-layer PCB half-bridge are evaluated using 3D-FEM field simulation and in-circuit measurements. Selected finite element method (FEM) simulation results are validated by <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameter measurements and further used to parametrize a lumped commutation loop model. The thermal characterization of the GaN half-bridge module validates the improved cooling capability of the GaN half-bridge power module. Transient switching characteristics are studied in hard-switching mode. The device temperature and converter efficiency are evaluated in dc/dc buck-converter operation.

Printed circuit board embedded power semiconductors: A technology review

Embedding power semiconductor devices into printed circuit boards (PCB) provides several benefits compared to conventional packaging technologies. Integrating the semiconductor dies into the circuit board reduces the converter size. This results in short current loops, enabling low interconnection resistances and parasitic inductances. Both contribute to a higher system-level efficiency, as conduction and switching losses are reduced. Moreover, the use of thick Cu substrates allows efficient heat removal, due to a low thermal resistance. Therefore, PCB embedding has received a lot of attention in the power electronics community for more than a decade. This article aims to provide a comprehensive review of the scientific literature on the topic ranging from basic fabrication technology over module or system-level demonstrators for electrical and thermal testing to reliability studies. Performance indicators, such as the commutation loop inductance Lσ, the chip area independent thermal resistance Rth × Achip, allow a comparison of different approaches and benchmarking with conventional power modules. Several publications report stray inductances below 1 nH and chip area independent thermal resistances in the range of 20…30 mm²K/W.

Passive Capacitor Voltage Balancing of SiC-Based Three-Level Dual-Active-Bridge Converter Using Hybrid NPC-Flying Capacitor Structure

Three-level (TL) dual-active-bridge (DAB) converter serves a critical role in the medium-voltage (MV) solid-state-transformers in which high voltage rating and bidirectional power flow are required. The regular neutral-point-clamping (NPC) topology is easily subjected to capacitor voltage unbalance due to nonideal operating conditions. In this article, a hybrid structure incorporating NPC and flying capacitor (FC) is presented to resolve the voltage unbalance issue. The key advantages include minimal additional hardware efforts and no need to resort to active control. The FC behaves as a buffer to leverage the upper and lower capacitor so that passive voltage balance between the two dc-link capacitors can be achieved on a switching cycle basis. Closed-form analysis further reveals the impact of FC value on voltage unbalance. Moreover, the appropriate modulation scheme, switching condition, and commutation loop are evaluated to provide detailed rule of thumb to the implementation of FC circuit. Analysis shows the FC also brings favorable switching loss performance and is friendly to employ upon fast switching of wide bandgap devices such as SiC. Finally, a 1.6 kV input, 400 V output, 8 kW scaled-down hybrid NPC-FC-based DAB converter is built to validate the above analysis.

Enhanced Level-Shifted Modulation for a Three-Phase Five-Level Modified Modular Multilevel Converter (MMC)

The rapid growth of the penetration level of renewable energy sources (RESs) in low-voltage (LV) networks increases the research interest in more efficient, compact, reliable, and easily expandable energy conversion systems. The long commutation loops of the existing LV multilevel converters (MLCs), such as active neutral point clamped (ANPC) converters, lead to high-voltage overshoots induced during switching due to the significant parasitic inductance. Modular multilevel converters (MMCs) are gaining an increased interest due to their modularity, flexibility, and short commutation loops also for some LV applications. However, several issues related to the number of components, dc capacitor requirements, and the added complexity need to be considered. This article aims to reduce the five-level modified MMC capacitance requirements where the upper and lower submodules (SMs) are connected in parallel. This reduction has been achieved using an improved modulation technique by minimizing the insertion time of the SMs that require higher capacitance. The proposed modulation is effective in reducing the inner SMs’ capacitor voltage ripple at lower modulation indices. Instead, the circulating current injection of the second harmonics effectively reduces the voltage ripple at higher modulation indices. Thus, maximum reduction in the total capacitance requirement for the entire operating range of modulation index can be achieved by a proper combination of the two solutions. Simulation and experimental results on a laboratory-scaled prototype verify the validity of the proposed solution.

Design of Low Inductance SiC-MOS/Si-IGBT Hybrid Module for PV Inverters

In this paper, design of a low parasitic inductance T-type SiC-MOS/Si-IGBT hybrid module for PV inverters is studied. Current commutation loops and self- and mutual inductances model of the hybrid module are analyzed. Then stacked substrates structures with vertical power commutation loop to reduce parasitic inductance are identified and compared. Finally, a hybrid module with stacked bond wire substrates structure is built and test results are provided to verify the design.

1200 V/650 V/160 A SiC+Si IGBT 3L Hybrid T-Type NPC Power Module With Enhanced EMI Shielding

Three-level (3L) inverters suffer from higher parasitic inductance due to the increased number of series-connected switches in a single current commutation loop (CCL) results in a larger size of CCL compared to their two-level (2L) counterparts. As such, semiconductors are subjected to higher voltage stress and severe ringing at the switching transient. While silicon carbide's (SiC) faster switching speed improves overall efficiency by reducing switching loss, the faster voltage, and current gradient (dv/dt and di/dt) generate electromagnetic interference (EMI) noise, requiring a larger and complicated filter stage design. To solve this problem, an optimized 3L T-type neutral point clamped power module has been proposed with a hybrid combination of the switch (SiC mosfet + Si IGBT) rated for 1200 V/160 A. Two direct bonded copper (DBC) substrates have been stacked to have a vertical power loop using laser-drilled vias, which provides low commutation loop inductance as low as 4.6 nH for the major CCLs including the wire bond. Other associated CCLs have also been identified and optimized. Additional DBC in the package will be acting as an EMI shield. The EMI noise has been compared to a traditional power module and a 21 dB reduction of common-mode noise has been observed.

EMI Performance of Active Neutral Point Clamped Phase Leg for Dual Active Bridge DC–DC Converter

This article evaluates the electromagnetic interference (EMI) caused by active neutral point clamped (ANPC) phase leg undergoing zero voltage switching (ZVS). ZVS, together with a high fundamental frequency operation is encountered in dual active bridge (DAB) converters. This allows ANPC phase leg to be operated in a different manner than its inverter counterpart. A comprehensive evaluation of four switching schemes for NPC/ANPC-DAB with regard to their EMI performance, voltage overshoot, and losses have been done. Switching state redundancies have been used to reduce the EMI of the ANPC phase leg. To further help in reduction of high frequency EMI and voltage overshoot, a low inductance busbar design has been presented for through-hole discrete devices. Finite element simulation and measurement results show a busbar inductance of 7.7 nH for long commutation loops. Finally, EMI performance (conducted and radiated) together with the busbar design has been experimentally validated for two of the most useful switching schemes. The switching schemes and the busbar design can boost adoption of NPC/ANPC-DAB by ensuring EMI compliance and improved efficiency without affecting the normal DAB operation or using additional hardware.

A novel double-sided cooling packaging structure of SiC-based half bridge module integrating the laminated busbar

This paper presents a novel double-sided cooling SiC-based half-bridge (HB) module with laminated busbar. The novelty of this module lies in the integration of a laminated busbar which can result in a significant reduction of the module parasitic inductance. Moreover, a 3D vertical structure design can reduce the commutation loop area inside the module, thereby further achieving a lower commutation loop inductance. Meanwhile, this module achieves wire-free bonding that can improve the reliability of the power module to a certain extent. A fan-shaped DBC layout is designed to ensure the symmetrical layout of the paralleled chips, which can realize a better current sharing performance. In fact, an unbalanced junction temperature can also affect the current balance of each parallel device, resulting in unequal turn-on and turn-off losses. Therefore, a three-outlet circular water-cooled heat sink is proposed to ensure the junction temperature balance of the parallel chips, which is demonstrated by thermal simulation. Then, by the Ansys Q3D, the extracted parasitic inductance of the module is about 5.63 nH, and the imbalance degree between each parallel branch is about 5.8%. Finally, the low parasitic inductance and highly symmetry of the module are verified by the experimental tests.

A New Press Pack IGBT for High Reliable Applications With Short Circuit Failure Mode

The modular multilevel converter (MMC or M2C) technology becomes the mainstream solution in today's voltage source converter-high voltage direct current (VSC-HVDC) transmission lines because of its unique performance. Recently press pack IGBT (PPI) has come into focus as a preferred realization for high power rating VSC-HVDC stations, it could offer the highest current rating IGBTs and advanced features in reliability. A new PPI is introduced in this paper, which is designed for several innovative improvements based on the application demands from VSC-HVDC systems. The chip is optimized for low on-state voltage with advanced trench technology, and well protected in a chip-stack by double side sinter process. The disc package is designed with hermetic sealed ceramic housing to avoid environmental erosion and could provide a robust feature of short circuit failure mode (SCFM), which is fully qualified under the worst-case scenario. In addition to the PPI device, system solutions had also been developed and investigated to support field developments, including electrical and mechanical design. An example of a power stack is analyzed in commutation loop, pressure distribution, and power losses.

A New Current Source Converter Using AC-Type Flying-Capacitor Technique

Entering the new millennium, current source converters (CSCs) have drawn increasing attention not only for high-power but also some emerging low-power applications which prefer the inherent voltage boosting nature and low dv/dt on ac-side. However, the dc-link quality of CSC has not been well improved and is rarely discussed in literature. To fill this gap, a new type of CSC topology is proposed in this article through the isomorphic theory. It utilizes the ac-type flying capacitors in each phase leg and provides alternative commutation loops, which can reduce the dc-side dv/dt and improve the common-mode voltage simultaneously. Besides, this technique can increase the withstand voltage of the converter without series connections of switching devices. Different from the voltage-source converter type, the flying capacitor voltage in CSC should be maintained as ac voltage, thus, active voltage regulation is necessary. To deal with such a challenge, carrier-based pulsewidth modulation with flying capacitor voltage regulation is also developed in this work. Compared with the traditional device-series-connected CSC topologies, the numbers of active switches and the device blocking voltage can remain the same, while the ac-type flying capacitors are added in the proposed topology to gain all the above merits. Simulation and experiment results are obtained to verify the advantages of this new type of CSC topology.

Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

Due to the high switching speed of Gallium Nitride (GaN) transistors, parasitic inductances have significant impacts on power losses and electromagnetic interferences (EMI) in GaN-based power converters. Thus, the proper design of high-frequency converters in a simulation tool requires accurate electromagnetic (EM) modeling of the commutation loops. This work proposes an EM modeling of the parasitic inductance of a GaN-based commutation cell on a printed circuit board (PCB) using Advanced Design System (ADS®) software. Two different PCB designs of the commutation loop, lateral (single-sided) and vertical (double-sided) are characterized in terms of parasitic inductance contribution. An experimental approach based on S-parameters, the Cold FET technique and a specific calibration procedure is developed to obtain reference values for comparison with the proposed models. First, lateral and vertical PCB loop inductances are extracted. Then, the whole commutation loop inductances including the packaging of the GaN transistors are determined by developing an EM model of the device’s internal parasitic. The switching waveforms of the GaN transistors in a 1 MHz DC/DC converter are given for the different commutation loop designs. Finally, a discussion is proposed on the presented results and the development of advanced tools for high-frequency GaN-based power electronics design.

Characterization of Parasitic Impedance in PCB Using a Flexible Test Probe Based on a Curve-Fitting Method

Switching in power semiconductors with emerging materials such as silicon carbide (SiC) leads to undesired overvoltages and oscillations that limit switching frequency, largely due to impedance in the current commutation loop. Minimizing this parasitic impedance in printed circuit boards (PCB) requires precise characterization. To this end, this work presents a new measurement method based on obtaining S-parameters with a vector network analyzer (VNA) and on using a shielded flexible probe with mobile test terminals. The flexible probe uses a metal shielding plane perpendicular to the PCB to prevent the main measurement errors resulting from the variation in the magnetic flux responsible for loop inductance during the VNA frequency sweep. The proposed curve-fitting procedure consists of measuring the characteristic impedance and propagation time of the traces, considering they form ideal transmission lines. These values are used for a nonlinear least squares adjustment for the actual line (with losses). Finally, an experimental assembly with microstrip transmission lines was developed to validate the proposed method experimentally. The experimental results were compared with those obtained by using a rigid test fixture as a reference, those calculated analytically and those obtained from partial element equivalent circuit (PEEC) simulation. The curve-fitting method yields better results than the analytical and the simulation methods and they exhibit (up to 350 MHz) precisions of 1.37% in the characteristic impedance measurement and of 0.81% in the propagation time.

Si/SiC hybrid 5-level active NPC inverter for electric aircraft propulsion drive applications

Medium voltage DC(MVDC) system is considered as a promising technology to improve the efficiency and power density of electric aircraft propulsion(EAP) drives. To adapt to the MVDC voltage level and achieve high drive performance, a five-level active neutral point clamped(5L-ANPC) inverter consisting of three-level ANPC and flying capacitor circuits is investigated, which possesses higher voltage capability, lower output harmonics, as well as mitigated dv/dt and common-mode voltage. To fulfill the requirements of high-speed operation and pursue further enhanced efficiency and power density of the inverter for the next-generation EAP drives, Silicon Carbide(SiC) semiconductor devices are considered for implementing the 5L-ANPC inverter. However, the large commutation loops associated with certain switching states of the inverter lessen the benefits of configuring all the switches as SiC devices. As a result, a hybrid Si/SiC 5L-ANPC inverter is developed with a synchronous optimal pulse(SOP) width modulation strategy for controlling the switches in cell 2 and finite-control-set model predictive controller(FCS-MPC) for those in cell 3 of the inverter. Consequently, in the proposed topology, the SiC devices are merely used for the high-frequency switches in cell 3 and the rest of the low-frequency switches are configured with Si IGBTs. This Si/SiC hybrid ANPC inverter concurrently provides high efficiency and low implementation cost at high-speed operation mode. Simulation and experimental results are provided to verify the effectiveness of the proposed hybrid inverter.