Common-source Structure Research Articles

An analytical approach to designing millimeter‐wave LNAs with transformer‐based matching networks

AbstractIn this article, an analytical method for designing transformer matching network of millimeter‐wave (mm‐wave) low noise amplifier (LNA) is presented. In the circuit design, neutralizing capacitors (NCs) structure is used to mitigate the intrinsic gate‐drain feedback capacitance in the transistor for increasing the reverse isolation and available gain, thus allowing the common source (CS) structure can be regarded as an unilateralized active amplification part. The equivalent circuit of the active amplification part and the matching transformer network is modeled, then the analytical matching equations can be established, and the required matching transformer parameter can be determined quickly. As a proof of concept, a Ka‐band LNA operating at 37–43 GHz is designed and implemented in 65 nm complementary metal oxide semiconductor. The measured results show that the small signal gain of the circuit is 19.2–20.5 dB at 37–43 GHz. The noise figure (NF) in the operating band is 3.2–4.2 dB, and the minimum NF is 3.2 dB at 40.2 GHz. The chip area is only 0.08 mm2 excluding pads.

Design of a Ka-band power amplifier

This paper introduces the design of a type of power amplifier working in the Ka-band, which has three stages based on 45nm CMOS technology. The operating frequency is 25-27GHz, and it has good efficiency and linearity. Among them, the driving stage adopts a cascode structure, the power stage adopts common source structure, and the matching network adopts a transformer structure. Using Cadence Virtuoso for simulation at the operating voltage of 1.8V, power gain of the single-ended power amplifier is 44.76 dB, saturation output power is 14.66 dBm, the output power at the 1dB compression point is 12.9dBm, and corresponding power-added efficiency is 22.19%.

High Linear and Temperature Insensitive GaAs Power Amplifier Operating at 3.3–3.6 GHz Using a Multi-Feedback Branch Bias Circuit

This letter describes a design of a 3.3–3.6-GHz GaAs heterojunction bipolar transistor (HBT) power amplifier (PA) with high linearity and temperature insensitivity for the fifth-generation (5G) of new radios (NRs). By involving a multi-feedback branches bias circuit, the voltage at the feedback node of the bias circuit can achieve dynamic self-tuning to stabilize the base voltage as the amplifier’s input power grows and stabilize the bias current as the temperature increases as well. A three-stage common source structure PA in the form of a monolithic microwave integrated circuit (MMIC) is designed using a multi-feedback branch bias circuit with a size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times1.2$ </tex-math></inline-formula> mm. Measured with continuous wave (CW) signals, the output 1-dB compression point at 3.3–3.6 GHz is 34 dBm. The linearity of the PA is also evaluated using a 5G-NR 100-MHz 64-quadratic-amplitude modulated (QAM)-orthogonal frequency division multiplexing (OFDM) signal with a 7-dB peak-to-average-power ratio (PAPR). The proposed PA achieves an adjacent channel power ratio (ACPR) less than −49.5 dBc at an average power of 28 dBm with a power-added efficiency (PAE) of 20% without the use of digital pre-distortion (DPD). In the temperature range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 40\,\,^{\circ }\text{C}$ </tex-math></inline-formula> to 120 °C, the variance of bias current, small signal gain, PAE, output power at 1-dB compression point (OP1dB), and ACPR is relatively minor. This design is ideally suited for 5G communication systems due to its high linearity and temperature insensitivity.

Ka-Band Three-Stack CMOS Power Amplifier with Split Layout of External Gate Capacitor for 5G Applications

In this study, we designed a Ka-band two-stage differential power amplifier (PA) using a 65 nm RFCMOS process. To enhance the output power of the PA, a three-stack structure was utilized in the power stage, while the driver stage of the PA was designed with a common-source structure to minimize power consumption in the driver stage. The layout of an external gate capacitor for the stacked power stage was split to maximize the performance of the power transistor. With the proposed split layout of the external capacitor, gain, output power, and power-added efficiency (PAE) were improved. Additionally, a capacitive neutralization technique was applied to the power and driver stages to ensure the stability and enhance the gain of the PA. The measured P1dB and the saturation power were 22.0 dBm and 23.3 dBm, respectively, while the peak PAE was 27.8% at 28.5 GHz.

Small-Signal Processing Low-Overhead Operational Amplifier for delta-Sigma ADC

Aiming at the fully differential (FD) sensing and high-precision small-signal output characteristics of micro-electromechanical systems (MEMS) gyroscopes, a low area overhead, high-gain, medium-speed, FD operation amplifier (Op-Amp) is designed for building a small-signal processing delta-Sigma analog-to-digital converter (ADC). The Op-Amp is a two-stage cascade structure, which combines folded cascade (FC) and gain-boosted technology to make the low frequency gain up to 129 dB, to meet the high-precision requirements of 18-bit delta-Sigma ADC. The first stage is FC gain-boosted structure, which uses a small bias current to achieve high-gain and low area overhead. In order to reduce the input noise, process smaller signals, the input pair adopts positive channel Metal–Oxide–Semiconductor (PMOS). The second-stage uses a large bias current to achieve a high unity gain bandwidth (UGB). Under the premise that the tail current source of the first stage is PMOS, in order to reduce the area overhead, abandoning the traditional common source (CS) structure of negative channel Metal–Oxide–Semiconductor (NMOS) input and PMOS as the current mirror load, adopting a new CS structure that PMOS input and NMOS used as independent bias current source. In this structure, the large overdrive voltage significantly reduces the size of transistors and greatly reduces the area overhead. The Op-Amp was implemented in SMIC 0.18 μm BCD process, 5 V supply voltage. Its post-layout simulation achieved a low-frequency gain of 129 dB, a UGB of 35 MHz and a phase margin (PM) of 62° for a load capacitance of 2 pF. Output voltage swings are ±3.71 V and including common mode feedback (CMFB), bias voltage generating circuit and filter capacitor, the area of Op-Amp is 167.162 μm × 200.82 μm. Behavioral-level verification shows that the designed Op-Amp meets the requirements of high-precision delta-Sigma ADCs.

A Compact 60GHz Power Amplifier in 65nm CMOS Technology

A compact 60GHz power amplifier chip in 65nm CMOS technology of three-stage common source structure is presented. The first two amplifiers offer sufficient gain to pre-amplify the small input power. The third stage amplifier uses two sets of differential pairs to achieve power synthesis. On-chip transformer coupling is adopted to realize inter-stage impedance matching as well as input and output matching. The compact structure of on-chip transformer can reduce the chip size and improve the integration degree. The measured small signal gain at 60GHz of 22.3dB, the saturation power of 20.2dBm, the output P-1dB of 17.3dBm, the PAE of 14%, and the core area is 0.19mm2. The power amplifier can be used in high-speed short-range wireless communication system to enhance communication data transmission capacity.

Ku-Band CMOS Power Amplifier with Three-Stack Power Stage to Enhance Output Power and Efficiency

In this study, we proposed a power amplifier structure with improved efficiency while securing high output power. First, the characteristics of the common-source and stack structures were investigated. In particular, the output power and output impedance characteristics of the stack structure were analyzed compared with the common-source structure. A common-source structure was applied to the driver stage to minimize dc power consumption, and a stack structure was applied to the power stage to ensure high output power. In order to verify the proposed structure, a Ku-band power amplifier was designed using the 65-nm RF CMOS process that provides nine metal layers. At the operating frequency of 15 GHz, saturation output power and maximum power-added efficiency were confirmed to be 22.1 dBm and 17.2%, respectively.

A 54–68 GHz Power Amplifier With Improved Linearity and Efficiency in 40 nm CMOS

This brief presents a 54–68 GHz two-stage power amplifier (PA) with linearity and efficiency enhancement in a 40 nm CMOS process. The first stage adopts a current reuse cascaded common-source (CS) structure with a shunt RC feedback to maximize the gain and minimize the DC power consumption to boost the linearity and efficiency, while the second stage is a cascode structure with two built-in linearizers to enhance the linearity much further. Based on the proposed structure, the fabricated PA exhibits measured output of 1-dB compression point, saturated output power, power added efficiency (PAE) and AM-PM distortion of +14 dBm, +15 dBm, 20% and 8 degrees, respectively. In addition, the proposed CMOS PA achieves high and flat power gain of 14 dB with ripple less than 1.5 dB through the operating 54—68 GHz frequency band while consuming only 110 mW.

A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS

In this paper, a wideband low-noise amplifier (LNA) with a two-fold noise cancellation scheme is proposed. Finetuned for advanced CMOS, the proposed LNA architecture uses a common-gate input branch to provide wideband input matching. It is followed by two stages of the common-source structure which cancels the noise and distortion of the first and second stages and relaxes the design restriction on the first noise-cancellation stage. The provided circuit-level analysis is verified by simulations. The proposed LNA is fabricated in 28-nm CMOS. It achieves a minimum noise figure (NF) of 2.5dB and input return loss (S₁₁) &#x003C; &#x2212;15dB over 0.02&#x2013;2GHz bandwidth while consuming only 4.1mW from a 1V supply and driving an external 50-<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load. The &#x2212;3dB power gain (S₂₁) is 18.5dB and IIP3 is &#x002B;4.25dBm.

An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers

This article presents a low-voltage high-transconductance input differential pair for bulk-driven amplifiers. The proposed structure employs two bulk-driven flipped voltage follower (FVF) cells as nonlinear tail current sources to enhance the slewing behavior. This method also increases the transconductance of the proposed amplifier two times against the conventional one. The enhanced topology is merged with a conventional bulk-driven input differential pair using cross-coupled connections to significantly increase the transconductance. These circuitry ideas lead to an improvement in the amplifier's specifications, such as dc gain, slew rate (SR), and input noise without any degeneration in other parameters. Moreover, thanks to the use of the bulk terminals as the input nodes and also a simple common-source structure as the second stage, rail-to-rail input, and output swings are achieved, respectively. The proposed amplifier was fabricated in TSMC 0.18- μm CMOS technology. Under a supply voltage of 0.5 V, the measurement results show that the proposed amplifier achieves a dc gain of 78 dB, a gain bandwidth of 7.5 kHz, and an SR of 8.6 V/ms with just 91-nA current dissipation.

Analysis and design of ultra‐wideband low noise amplifier using complementary structure with series inductive peaking technique and shunt feedback

SummaryIn this paper, an ultra‐wideband low noise amplifier (LNA) is presented using 0.18‐μm RF CMOS technology. A complementary structure with series inductive peaking technique is introduced by using two inductor‐loops to achieve flat gain. In the first and third stages, two complementary structures are utilized to achieve a high and flat gain, a wideband input impedance matching and a low noise figure. In addition, a shunt feedback is utilized to increase input impedance matching and stability. In the second stage, a common source structure is used as interstage, which increases the −3 dB bandwidth. The designed LNA presents a high and flat gain of 15.6–16.5 dB, an excellent input return loss better than −11 dB and a good NF of 2.2–3 dB in the frequency range of 3.1–10.6 GHz. Also, the proposed structure consumes 6.8 mW from a 0.8‐V supply voltage and has an IIP3 of −4 dBm at 6.5 GHz. The proposed structure only occupies 0.59 mm2.

An 18–56-GHz Wideband GaN Low-Noise Amplifier With 2.2–4.4-dB Noise Figure

An 18-56-GHz gallium nitride (GaN) low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) is presented in this letter. This LNA is fabricated with commercial 0.1-μm gate-length GaN-on-silicon (GaN/Si) process. The gain is 16-21.5 dB and the |S11| and |S22| are below -5 dB across the band. The noise figure (NF) is 2.2-4.4 dB and the output power at 1-dB compression point (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> ) is 10-20 dBm. This LNA has four-stage-cascade and common-source structure with 4.8 × 1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area. The dc power dissipation is 1.4 W. To the best of the author's knowledge, there has been no GaN LNA covering such a wide bandwidth at this frequency range. This LNA shows ultrawide bandwidth, low NF, high linearity, and high robustness. Moreover, it can be directly integrated with GaN power amplifiers (PAs) and switches to realize the monolithic RF front-ends, which can largely reduce the packaging loss and the module volume. This LNA has a great potential in wideband, high-speed, high-reliability, and high-integration applications.

An Ultra-Wideband 0.1–6.1 GHz Low Noise Amplifier in 180 nm CMOS Technology

In this paper, an Ultra-Wideband (UWB) low noise amplifier (LNA) with low power consumption and high-power gain in 180[Formula: see text]nm CMOS technology is presented. An innovative combination of conventional methods to design UWB-LNA, i.e., resistive-feedback, inductive-series peaking, noise cancelling and inductive degeneration techniques is described here. The proposed LNA consists of two common source amplifiers with resistive feedback in which the noise and power consumption have been reduced by using the noise cancelling and current reuse techniques, respectively. Also, resistive feedback in the first stage reduces input resistance, hereby improving input impedance matching. In the second stage, which is used to increase the power gain, a common source structure with inductive-series peaking and noise cancellation techniques is used. The analytical results agree well with the post layout simulation results. The post-layout simulation shows a gain of [Formula: see text][Formula: see text]dB and noise figure (NF) of 2.3[Formula: see text]dB in the whole [Formula: see text][Formula: see text]dB bandwidth of 0.1[Formula: see text]GHz to 6.1[Formula: see text]GHz, while the S11 and S22 are less than [Formula: see text][Formula: see text]dB. The proposed circuit has a figure of merit of 9.9 which is significantly improved compared to the previous works. The total power dissipation is only 7.3[Formula: see text]mW, and the active area is less than 0.7[Formula: see text]mm2.

Design of Ultra-low Power Consumption Low-dropout Regulator

This paper designs a type of ultra-low power consumption LDO with the CSMC 0.5μm technology, which can output the 1.5V voltage. In this LDO, the error amplifier is structed with two-stage operational amplifiers. The input of first stage uses PMOS differential pairs that can decrease the noises and the second stage uses the common-source structure in order to increase the open-loop gain. In addition, the MOS amounts we use are as less as possible over the whole circuit, which decrease the die size to satisfy the trend of product miniaturization. The result of simulator Spectre shows that the LDO proposed can output the 1.5V voltage stably, the PSR is -66dB at 1kHz, and the loop gain is 72.5dB, the lowest dropout voltage is 93mV, the power consumption is only 1mW.

A Novel 5-5.7GHz Low-Power LNA Using Low-Power Techniques

In this paper, a novel 5-5.7GHz low power low noise amplifier (LNA) is designed. It utilizes two stage structures, including common-source structure adopting self-forward-body-bias (SFBB) technique, improved input matching and output matching methods. In 5-5.7GHz band, simulation results shows the design has gain greater than 16.5dB, operating voltage lower than 1V and low noise figure.

Design and Implementation of Low Noise Amplifier At 60ghz using Current Mirror Feedback

This discourse used 45nm CMOS technology to design a Low noise amplifier for a Noise figure &lt; 2dB and gain greater than 13dB at the 60GHz unlicensed band of frequency. A single stage, primary cascode LNA is modeled and its small signal model is analyzed. Common source structure is hired in the driver stage to escalate the output power with single stage contours. To enhance small signal gain, simple active transistor feedback and cascode feedback configurations are designed and appended to the basic LNA. In addition to this, current re-use inductor is designed and added to the cascode amplifier which is deliberated to give low power and low noise figure. Small signal analysis of simple active transistor feedback and current re-use inductor has been presented. The measurement results indicated that the input match and the output gain at 60GHz achieves -8dB and 13dB respectively with the supply voltage of 900mV. The frequency response obtained is a narrow band response with 6GHz of bandwidth. The circuit is simulated by Cadence Virtuoso tool. The layout of the related circuit is drawn by means of the Virtuoso Layout editor with total size of 0.1699μm2.

Gain-controlled noise-reduction LNA design using source-bulk resistors and double common-source topology

This paper presents the design of a Low Noise Amplifier (LNA) using double common-source technique results in wideband input matching. Moreover, to reduce the noise figure, a resistor series to source-bulk substrate resistance is applied. One of the main problems of the common-source structure in LNA design is the narrow-band property. Using the proposed double common-source scheme, the narrow-band problem is solved and the desired wideband attributes can be achieved. In addition, using a resistor series to the source-bulk substrate resistance results in significant noise figure reduction. In the proposed scheme, the gain of LNA in frequency band of 3–12 GHz would be between 14.2 dB and 15.1 dB. Furthermore, the variation of gain in this band is 0.45 dB which is significant. The 3-dB bandwidth of the designed LNA is 10.2 GHz (from 2.4 to 12.6 GHz). The worst case of return loss of input port is −10 dB. The above mentioned series resistor causes the noise figure to decrease and set between 3.47 and 4.12 dB. Using 180-nm TSMC technology, the DC power is 11 mW from 1-V supporting voltage.

60 GHz low‐power LNA with high g m × R out transconductor stages in 65 nm CMOS

This Letter presents a 60 GHz low power low noise amplifier (LNA) with high g m × R out transconductor stages in a 65-nm complementary metal oxide semiconductor (CMOS) technology. Different from the cascode and current-reused common source-common source (CS-CS) structure, the new transconductor proposed in this Letter comprises a CS transistor whose DC current is shared by other two transistors. With this configuration, the equivalent transconductance, g m and output resistance, R out of the transconductor are both high while its noise figure is deteriorated slightly comparing with CS structure, making it suitable for low-power LNA circuits. From the measurement results, the LNA gets a gain of 13.4 ± 1.5 dB and 3-dB bandwidth of 16.7 GHz (48-64.7 GHz). The average noise figure of the LNA is 6.1 dB with a power dissipation of 9.6 mW under 1 V power supply.

65 nm CMOS 공정을 이용한 W-대역 전력증폭기 설계

본 논문에서는 차량 충돌 방지 장거리 레이더(Long Range Radar: LRR)을 위한 77 GHz 전력증폭기를 65 nm CMOS 공정을 이용하여 설계하였다. 제안한 회로는 3단 차동 전력증폭기로 공통 소스 구조와 트랜스포머를 사용했다. 측정결과로 77 GHz에서 18.7 dB의 전압 이득과 13 GHz의 3 dB 대역폭을 얻었다. 측정된 최대 출력 전력은 10.2 dBm, 입력 <TEX>$P_{1dB}$</TEX>는 -12 dBm, 출력 <TEX>$P_{1dB}$</TEX>는 5.7 dBm이며, 측정된 최대 전력 효율은 7.2 %이다. 본 전력증폭기는 1.2 V의 공급전원으로부터 140.4 mW의 DC 전력을 소모한다. In this paper, we propose 77 GHz power amplifier for long range automotive collision avoidance radar using 65 nm CMOS process. The proposed circuit has a 3-stage single power amplifier which includes common source structure and transformer. The measurement results show 18.7 dB maximum voltage gain at 13 GHz 3 dB bandwidth. The measured maximum output power is 10.2 dBm, input <TEX>$P_{1dB}$</TEX> is -12 dBm, output <TEX>$P_{1dB}$</TEX> is 5.7 dBm, and maximum power add efficiency is 7.2 %. The power amplifier consumes 140.4 mW DC power from 1.2 V supply voltage.

A broadband 47–67 GHz LNA with 17.3 dB gain in 65-nm CMOS**Project supported by the National High Technology Research and Development Program of China (No. 2011AA010202).

A broadband 47–67 GHz low noise amplifier (LNA) with 17.3 dB gain in 65-nm CMOS technology is proposed. The features of millimeter wave circuits are illustrated first and design methodologies are discussed. The wideband input matching of the LNA was achieved by source inductive degeneration, which is narrowband in the low-GHz range but wideband at millimeter-wave frequencies due to the existence of gate–drain capacitance, Cgd. In order to minimize the noise figure (NF), the LNA used a common-source (CS) structure rather than cascode in the first stage, and the noise matching principle is explored. The last two stages of the LNA used a cascode structure to increase the power gain. Analysis of the gain boost effect of the gate inductor at the common-gate (CG) transistor is also performed. T-shape matching networks between stages are intended to enlarge the bandwidth. All on-chip inductors and transmission lines are modeled and simulated with a 3-dimensional electromagnetic (EM) simulation tool to guarantee the success of the design. Measurement results show that the LNA achieves a maximum gain of 17.3 dB at 60 GHz, while the 3-dB bandwidth is 20 GHz (47–67 GHz), including the interested band of 59–64 GHz, and the minimum noise figure is 4.9 dB at 62 GHz. The LNA absorbs a current of 19 mA from a 1.2 V supply and the chip occupies an area of 900 × 550 μm2 including pads.