Design of Ultra-low Power Consumption Low-dropout Regulator

Abstract

This paper designs a type of ultra-low power consumption LDO with the CSMC 0.5μm technology, which can output the 1.5V voltage. In this LDO, the error amplifier is structed with two-stage operational amplifiers. The input of first stage uses PMOS differential pairs that can decrease the noises and the second stage uses the common-source structure in order to increase the open-loop gain. In addition, the MOS amounts we use are as less as possible over the whole circuit, which decrease the die size to satisfy the trend of product miniaturization. The result of simulator Spectre shows that the LDO proposed can output the 1.5V voltage stably, the PSR is -66dB at 1kHz, and the loop gain is 72.5dB, the lowest dropout voltage is 93mV, the power consumption is only 1mW.