Common Source Low Noise Amplifier Research Articles

Low Noise Amplifier at 60 GHz Using Low Loss On-Chip Inductors

This paper proposes the technique of using low loss on-chip inductors in the design of low noise amplifier (LNA) that offers high gain and lower noise figure. Upon the substrate of octagonal spiral inductors, a surface of patterned ground shield is inserted that significantly reduces the substrate loss. This effect limits the penetration of electric filed into the substrate, thereby improving the inductor’s Quality (Q) factor and decouples the substrate parasitic that results with smaller series resistance. These effects result with improved gain and noise figure of LNA at 60 GHz when the designed inductors are included in it to serve as gate, source, and load inductances. The proposed work uses an inductively degenerated 3-stage common-source LNA in a 65-nm CMOS process. Simulation results show that the LNA using custom designed inductors achieves the peak gain of 17.02 dB at 56 GHz with a noise figure of 5 dB at 60 GHz for the power consumption of 10 mW. The figure-of-merit (FOM) is 14.56 which is 0.8 times more than the LNA design using off-chip inductors. A complete LNA layout using custom designed inductor footprints has been presented and analyzed.

Mutually coupled CG-CS current reuse low noise amplifier architecture for 4 – 14 GHz frequency

Abstract The current research paper presents a design of a mutually coupled cascode Common Gate Common Source (CG-CS) Low Noise Amplifier (LNA) using current reuse technique. The proposed design provides a significant improvement in the gain and noise performance of the LNA, while also reducing power consumption. Mutually coupled inductors help in reducing the size of the circuit while transformer connected at the output provide output impedance matching. Proposed LNA simulated for the 4–14 GHz RF frequency. Mathematical analysis of proposed LNA has been analyzed using the small signal model henceforth input impedance; gain and Noise Figure (NF) have been derived from it. The design and simulation results show that the proposed LNA design with current reuse technique achieved a maximum gain of 17.87 dB, minimum NF of 5.45 dB, and input reflection coefficient less than –10 dB for the 10 GHz bandwidth. These results indicate a significant improvement in the overall performance of the LNA compared to conventional designs as Figure of Merit (FoM) is 17.34.

Bulk CMOS Low Noise Amplifier With Two Stage HPF Noise Matching Structure

In this study, a two-stage low-noise amplifier (LNA) was developed in which the noise-matching network of a high-pass filter (HPF) structure is applied to both stages. As the HPF noise matching network is used in both stages, the noise figure of the proposed LNA can be reduced compared to that of the conventional LNA. In particular, the noise figure is improved in the high-frequency region. To verify this development, a two-stage common-source LNA was implemented using 0.18-lm bulk complementary metal oxide semiconductor technology. The fabricated LNA achieved an average noise figure of 2.6 dB (minimum noise figure of 2.23 dB at 3.95 GHz) and a peak gain of 14.19 dB. In addition, the LNA has an input 1-dB compression point (IP1dB) of.12 dBm and a third-order input intercept point (IIP3) of +2.0 dBm at 3.5 GHz, consumes 16 mA with a 0.9 V supply, and has an area of 0.7 mm2.

A 9-to-42-GHz High-Gain Low-Noise Amplifier Using Coupled Interstage Feedback in 0.15-μm GaAs pHEMT Technology

This article presents a 3-stage millimeter-wave low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) design for broadband applications. The proposed structure consists of cascading common-source (CS) LNA with coupled interstage feedback (CIF) paths at the second and third stages. By tuning the coupling factor and the inductance of the CIF, enhanced overall gain and extended working bandwidth can be achieved simultaneously. The proposed CIF formed by a simple on-chip edge-coupled parallel metal-lines features small size and high flexibility. To facilitate circuit design and optimization, an equivalent circuit for the proposed CIF structure is developed. Besides, to address the trade-off between impedance matching and noise performance, a noise matching strategy focusing more on higher frequencies is presented to achieve good noise performance. With the proposed techniques, an LNA prototype is demonstrated in a commercial 0.15- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs E-mode pHEMT process. The fabricated LNA has a die size of 1.15 mm2 and DC power consumption of 109 mW. The measurement results show a peak gain of 25.6 dB with a 3-dB bandwidth of 9~42 GHz, the minimal noise figure (NF) of 1.91 dB, a group delay of 68.7± 20.5 ps, and 20.8 dBm best OIP3 under 2.0-V VDD.

A highly-linear, sub-mW LNA at 2.4 GHz in 40 nm CMOS process

This paper focuses on designing low-power, low-noise amplifiers (LNA) performances. Different LNA topologies operating with sub-mW power consumption at 2.4 GHz have been implemented in a commercial 40 nm CMOS process. The LNA1 (cascode common source LNA) has a voltage gain of 12.22 dB, a noise figure (NF) of 4.35 dB, and a third-order input intercept point (IIP3) of −12.68 dBm at 995.6 μW while the proposed LNA2 with improved linearity has a 5.68 dB gain, 5.13 dB NF, and a −0.12 dBm IIP3. The difference between both final designs, which consist of improved linearity and gain, stems from the location of the gate inductance (Lg) in the chip. The proposed LNA3 with an on-chip Lg has a voltage gain of 11.1 dB, an NF of 4.27 dB, and an IIP3 of -0.82 dBm. Moreover, the proposed LNA4 with an off-chip Lg has 10.31 dB voltage gain, 3.68 dB NF, and 0.89 dBm IIP3 at 989.6 μW in post-layout simulations. Comparing the LNAs, the proposed LNA4 with an off-chip Lg has the best figure-of-merit (FOM). This work aims to achieve improved linearity figures at sub-mW power.

A 0.092-mm2 2–12-GHz Noise-Cancelling Low-Noise Amplifier With Gain Improvement and Noise Reduction

This brief proposes a broadband noise-cancelling (NC) common-gate (CG)-common-source (CS) low-noise amplifier (LNA) with a passive network to improve the gain and noise performance simultaneously. In the CG-CS LNA with active feedforward, a current-bleeding (CBLD) circuit is required to provide the required DC current of the auxiliary amplifier, which introduces additional noise. In the proposed work, by adding a passive network at the output, the noise of the CBLD circuit can be made negligible. Moreover, the passive network also provides the shunt peaking to facilitate the gain and noise performance over the desired band. Fabricated in TSMC 40 nm CMOS technology, the measured results show the proposed LNA exhibits a gain of 16.5 – 19.5 dB, a noise figure (NF) of 3.2 – 5.2 dB from 2 to 12 GHz and an IIP3 of −3.5 dBm at 6 GHz. It consumes 9 mW from a 1.2 V supply and occupies a very compact die area of 0.092 mm2.

An improved cascode common-source LNA with inductive source degeneration for RF applications

This paper presents a novel structure to enhance the power gain (S21) of the conventional cascode common-source (CS) low-noise amplifier (LNA) with inductive source degeneration. The proposed LNA has an extra transistor and a capacitor in comparison with the conventional structure. The additive transistor significantly increases the S21 of the conventional cascode CS LNA with inductive source degeneration with the same DC power consumption (PDC), third-order input intercept point (IIP3), area, and slightly lower noise figure (NF). The utilized capacitor is used to improve the IIP3 of the proposed LNA. The power gain improvement of the proposed LNA has been validated by both theoretical analysis and extensive post-layout simulation results. The proposed and conventional LNAs have been designed in TSMC 180 nm CMOS technology. The post-layout simulation results of the proposed LNA are 2.42 dB NF, S21 of 15.55 dB, and 0.84 dBm IIP3 while consuming 3.2 mW from 1.2 V power supply. The simulated S21 of the proposed LNA is about 2.55 dB (34.2 %) larger than the conventional cascode LNA with the same other performance parameters. Also, the achieved figure-of-merit (FoM) of the proposed LNA is substantially larger than the conventional cascode CS LNA with inductive source degeneration.

A Wideband E/W-Band Low-Noise Amplifier MMIC in a 70-nm Gate-Length GaN HEMT Technology

This article reports on a gallium-nitride (GaN) low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) with a 3-dB gain bandwidth (BW) from 63 to 101 GHz. The MMIC is fabricated in the Fraunhofer IAF 70-nm GaN-on-silicon-carbide (SiC) high-electron-mobility transistor (HEMT) technology. The four-stage common-source LNA exhibits an average noise figure (NF) of 3 dB for a measured frequency range from 75 to 101 GHz. The MMIC reaches a minimum NF of 2.8 dB at an operating frequency of 83 GHz. A mapping of two 100-mm wafers shows an excellent homogeneity with an 86% yield and an average NF of 3–3.3 dB. At 100 GHz, the LNA obtains output-referred 1-dB compression and third-order intercept points of 12.1 and 14.4 dBm, respectively. Furthermore, comprehensive investigations of the bias dependence of all measured performance parameters provide an insight into the presented device and LNA. To the best of the authors’ knowledge, this MMIC demonstrates the lowest NF among GaN LNAs at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}/{W}$ </tex-math></inline-formula> -band frequencies.

6.7–15.3 GHz, High-Performance Broadband Low-Noise Amplifier With Large Transistor and Two-Stage Broadband Noise Matching

This letter presents a fully integrated wideband, ultralow average noise figure (NF), low power consumption, compact, and electrostatic discharge protected 6.7-15.3-GHz low-noise amplifier (LNA). A peak-gain distribution technique with a large transistor and two-stage broadband noise matching technique are proposed. For verification, a two-stage common source LNA is implemented in a 65-nm bulk complementary metal-oxide-semiconductor technology. The fabricated LNA achieved an average NF of 2.08 dB and an average gain of 19.1 dB with in-band gain ripple of ±0.75 dB in the frequency range of 7.6-14.7 GHz. It has a 3-dB fractional bandwidth of 78% and the third-order input intercept point is -9.0 dBm at 10 GHz. It consumes a 16 mA at a 0.8-V supply and has an area of 0.144 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 0.061-mm² 1–11-GHz Noise-Canceling Low-Noise Amplifier Employing Active Feedforward With Simultaneous Current and Noise Reduction

This article proposes a novel wideband common-gate (CG) common-source (CS) low-noise amplifier (LNA) with active feedforward for simultaneous current and noise reduction. By employing an active feedforward stage in the main path, the current dissipation and the thermal noise are effectively suppressed, while the noise and distortion cancelation properties of CG-CS topology are preserved. Moreover, no extra noise is introduced since the additional g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boost amplifier follows the same noise-canceling (NC) principle as the CG amplifier, and its noise can be fully canceled at the output theoretically. Thus, the proposed LNA benefits from the g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosting and NC technique simultaneously to obtain a good tradeoff between gain, noise figure (NF), and power consumption. Fabricated in standard 40-nm CMOS technology, the measured results show the proposed LNA exhibits a peak gain of 17 dB, NF of 3.5-5.5 dB from 1 to 11 GHz and an IIP3 of -2.8 dBm at 6 GHz. It consumes 9 mW from a 1.2-V supply and occupies a very compact die area of 0.061 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Multi-Feed Antenna and Electronics Co-Design: An E-Band Antenna-LNA Front End With On-Antenna Noise-Canceling and Gₘ-Boosting

This article presents an E-band low-noise amplifier (LNA) co-designed and co-integrated with an on-chip multifeed antenna for antenna-level LNA noise-canceling and gm -boosting. Different from conventional approaches that view antennas as a simple 50-Ω radiation load, we exploit antennas as multi-feed passive radiating networks with direct onantenna signal conditioning and processing capabilities. Such an antenna-electronics co-design concept can potentially advance wireless front-end performance beyond electronics-only designs and opens the door to a plethora of front-end innovations. We also propose equivalent circuits to model multi-feed antenna systems and elucidate on-antenna signal processing operations. As a proof of concept, we propose an antenna-LNA co-designed architecture and explore the interactions among a common-gate (CG) LNA path, a common-source (CS) LNA path, and a pair of near-field coupled folded slot antennas for on-antenna noise-cancellation and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosting. In the measurements, a true V-factor radiation method is introduced as a new approach to measure the noise figure (NF) of the on-chip multi-feed antenna and LNA/RX integration. Then, we perform the conventional sensitivity-based NF measurement. Both measurements show accurate and consistent NF characterization at high millimeter-wave (mm-Wave). The E-band antenna-LNA front end is implemented in the Globalfoundries 45-nm CMOS SOI process and demonstrates 4.8-dB NF with 2.2-dBm IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , achieving the best reported FoM at similar frequencies. Furthermore, over-the-air modulation tests are demonstrated, supporting >10-Gb/s high-fidelity high-order QAM signals over an E-band wireless link.

A 0.096-mm$^{2}~1$ –20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration

This article proposes a novel wideband common-gate (CG) common-source (CS) low-noise amplifier (LNA) with a dual complementary pMOS–nMOS configuration to provide a current-reuse output. Triple-path noise-cancellation is effectively revealed to eliminate the thermal noise of the two CG transistors. Simultaneously, partial cancellation of intrinsic third-order distortion of output-stage transistors improves the input third-order intercept point (IIP3). In addition, we embed a resistive feedback in one of the auxiliary CS amplifiers to balance the multiple tradeoffs between noise figure (NF), input matching (S11), and forward gain (S21). Fabricated in 65-nm CMOS, the proposed wideband LNA exhibits an IIP3 of 2.2–6.8 dBm and an NF of 3.3–5.3 dB across a 19-GHz BW while consuming 20.3 mW at 1.6 V. S11 is $\pi $ -type input-matching network. The LNA exhibits a peak $\text{S}_{\vphantom {D_{j}}21}$ of 12.8 dB and occupies a very compact die area of 0.096 mm2.

Performance Analysis of Inductive Source Degeneration Low Noise Amplifier using Multi-finger Technique

In the current paper, common source Low Noise Amplifier using inductively degenerated technique is designed to meet Radio Frequency (RF) range 2.45 GHz-2.85 GHz. The designed LNA is implemented using single and multi-finger transistor logic. The transistor geometry greater than 300 μm has been split into multiple fingers using multi-finger technology. The schematic is captured using ADS. The performance of LNA for various technologies has been analyzed using PTM 180 nm, PTM 130 nm and PTM 90 nm models. The amplifier with single transistor achieves minimum noise figure of 0.178 dB noise figure and maximum gain of 20.045 dB using 130 nm model technology for Bluetooth applications. Similarly 0.288 dB of minimum noise figure and peak gain of 17.971 dB are obtained using multi-finger MOSFET of PTM 90 nm technologyrespectively.The reverse isolation (S12) below -50 dB is achieved.

Low-power fully monolithic MICS band receiver for 402-405 MHz implantable devices

ABSTRACTA 402–405MHz fully monolithic Radio Frequency (RF) low-Intermediate Frequency (IF) receiver is presented. The proposed low-power RF receiver consists of a differential Common gate-Common Source Low-Noise Amplifier (CG-CS LNA) with a positive–negative feedback technique, passive mixer, fully integrated Voltage Controlled Oscillator (VCO), and an IF Variable Gain Amplifier (VGA). To achieve a wide tuning range while keeping a low gain (Kvco), the VCO has 16 bands selectable by a 4-bit digital control. The complete receiver prototype is implemented in a 0.13μm CMOS process and occupies 0.625 mm2 active chip area. The receiver consumes only 3.76 mW of power from a 1.2 V power supply and has a gain of 45 dB and a noise figure of 13.6 dB (integrated from 20 Hz to 0.5 GHz). The design achieves an in-band IIP3 of 2 dBm, IIP2 better than 44 dBm. It presents a 3-dB IF bandwidth of 3 MHz with −80 dBm sensitivity.

An Ultra-Low-Power 5 GHz LNA Design with Precise Calculation

In this paper, an ultra-low-power low-noise amplifier (LNA) at 5GHz is proposed. The main focus is on precise computation of output impedance, input impedance, and gain of the LNA. The LNA is composed of a common-source LNA and a cascode LNA. In fact, the casode LNA can assist to have more stability by declining S12 considerably. Plus, it can be beneficial via increasing the gain of the second stage of the final LNA. In addition, in order to emphasize the significance of the meticulous calculations, the formulas calculated in this paper are compared with their counterparts in other papers. The combination of two different supply voltage is mentioned as an approach to bring down the power dissipation of the circuit. Simulation is performed by MATLAB, HSPICE, and Advanced Design System (ADS). TSMC 0.18 um CMOS process is used to evaluate the circuit. The LNA is analyzed with two different voltage supply 0.7 V and 0.9 V. The input matching (S11) is -14 dB and -16 dB for voltage supply 0.7 V and 0.9 V respectively. Plus, power dissipation, noise figure (NF), and gain (S21) are 532 μW, 944 μW, 1.25 dB, 1.05dB, 15dB, and 17dB for voltage supply 0.7 V and 0.9 V respectively.

Design of inductively degenerated common source RF CMOS Low Noise Amplifier

The Low Noise Amplifier (LNA) is the first stage in RF CMOS receivers. The Common Gate (CG) LNA and Inductively Degenerated Common Source (CS) LNA are one of the widely used topologies for realizing RF CMOS receivers. The present work emphasizes a simple and exhaustive search procedure for the synthesis and analysis of CMOS CG and Inductively Degenerated CS LNA circuits. The width (W), gate source voltage ( $$ V_{gs} $$ ) and drain source voltage ( $$ V_{ds} $$ ) of the transistors constitute the design space in the circuit design. The design first involves the use of a circuit simulator (HSPICE) to obtain the small signal parameters of the circuit for various W, $$ V_{gs}$$ , and $$ V_{ds} $$ of the transistors and then to generate a Look-Up Table (LUT) for all design points using the obtained values. This LUT is used to meet the target performance specifications along with appropriate analytical expressions derived from the circuit in a numerical simulator (MATLAB). This will enable one to explore the whole design space quickly and fastly for arriving at the optimal values for the device dimensions, bias voltages and bias currents of the two LNA circuits. The design methodology is demonstrated by designing CG and Inductively Degenerated CS LNA circuits using 90 nm CMOS technology library in which Inductively Degenerated CS LNA gets high gain and low noise figure than CG LNA.

A Coupled-RTWO-Based Subharmonic Receiver Front End for 5G &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$E$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Band Backhaul Links in 28-nm Bulk CMOS

An $E$ -band direct-conversion subharmonic receiver (SHRX) is designed exploring a coupled-rotary-traveling-wave-oscillator-based (coupled-RTWO-based) architecture. Distributed oscillators are leveraged to generate $N=8$ differential phases at $f_{\mathrm{ LO}}=f_{\mathrm{ RF}}/4$ . Current-mode passive mixers (MXs) are adopted to enable <1-V supply operation and greatly simplify the layout. An inductively degenerated neutralized common source (DCS) low-noise amplifier (LNA) is embedded in a fourth-order transformer-based matching network to allow broadband impedance scaling and high reverse isolation. Implemented in a 28-nm bulk CMOS technology without ultra-thick top metal option, the realized prototype outperforms prior reported CMOS designs in terms of phase noise, figure of merit (FOM), and tuning range. The SHRX front end achieves 8.3-dB noise figure (NF), 12.5 GHz −3-dB RF bandwidth (BW), and −25-dBm ICP1 dB, while consuming <100 mW.

A novel high dynamic range differential LNA using quartet topology

In some applications such as short-range radars, a large target can desensitize the receiver. A high dynamic range low-noise amplifier (LNA), as a key component of a transmitter/receiver module, can improve the entire system performance. This study presents a high dynamic range differential LNA that uses a differential quartet topology for the first time. The LNA shows more linearity than the conventional differential common source LNAs. For a typical 0.18 µm CMOS technology, it achieves a power gain of about 5.5 dB at 24 GHz, a low noise figure (NF) of 3.5 dB, very good linearity performance, an input-referred third-order intercept point (IIP3) of + 6.3 dBm, and an input-referred 1 dB compression point (P1dB) of − 4.5 dBm.

Gm-boosted current-reuse inductive-peaking common source LNA for 3.1–10.6 GHz UWB wireless applications in 32 nm CMOS

A low power, low noise amplifier (LNA) for 3.1–10.6 GHz ultra-wideband (UWB) wireless applications is reported in this paper. The proposed LNA is designed using common source (CS) current-reused architecture. Flat and high power gain (S21) with constant noise figure (NF) is achieved using series inductive peaking between CS primary stage and the current reused second stage. Input–output matching networks have been used to achieve acceptable values of input reflection coefficient (S11) and output reflection coefficient (S22) for the complete UWB frequency range. The use of inductive peaking with current reused architecture enhances the overall performance of proposed ultra-wideband LNA. The LNA is analyzed and designed using 32 nm CMOS process. It has a constant NF of 2.7 dB, a high and flat S21 of 23.8 ± 0.7 dB with high reverse isolation (S12) of < − 37.3 dB. The proposed LNA provides acceptable results for S11 and S22 parameters with values less than − 7.5 and − 11.0 dB respectively, for the UWB frequency range of 3.1–10.6 GHz. The proposed LNA provides 1-dB compression point (P1dB) of − 20 dBm and third order intercept point (IIP3) of − 10 dBm. The power consumed by the reported LNA is only 8.05 mW for a 0.7 V power supply.

A common‐gate common‐source low noise amplifier based RF front end with selective input impedance matching for blocker‐resilient receivers

SummaryThis paper presents an integrated wideband radio frequency front end with improved blocker resilience achieved through selective voltage attenuation at both input and output nodes of the low noise amplifier (LNA). The architecture differs from traditional LNA architectures where blockers are only attenuated at LNA output node. The proposed dual attenuation is attained by designing a low intrinsic input impedance common‐gate common‐source LNA with capacitive feedback, together with an N‐path filtering load. The capacitive feedback across the LNA ensures that the selective N‐path filtering profile at the LNA output is transferred to the LNA input nodes creating a selective input impedance. Consequently, the achieved front‐end input impedance is low at blocker frequencies and matched to the source impedance at the desired frequencies, creating the desired voltage attenuation for blockers. Further, a detailed theoretical analysis of proposed architecture is presented, which leads to clear design guidelines. Evaluated in a 28‐nm fully depleted silicon‐on‐insulator complementary metal oxide semiconductor (CMOS) process, front end is designed for wideband operation from 0.7 to 2.7 GHz. It consumes 11‐mA current from a 1‐V supply (excluding local oscillator (LO) buffering) and possesses a maximum noise figure of 5.1 dB. The front end demonstrates an out‐of‐band blocker compression point of −1.5 dBm and out‐of‐band IIP3 of +14 dBm at a 100‐MHz offset from LO frequency. In comparison with a traditional common‐gate common‐source LNA‐based front end with wideband input impedance matching, the proposed front end achieves 3.5‐dB improvement in the blocker compression point at a 100‐MHz offset from LO.