Common-mode Voltage Research Articles

Development of Improved Low-leakage Current H6 Single-Phase Full-Bridge Inverter Topology

Objective: To minimize leakage current in non-isolated photovoltaic grid connected inverters. Methods: The circuit design integrates extra switches and modifies the switch drive signals at the midpoint of the DC bus voltage, altering the common-mode current path. Findings: The proposed topology exhibits significant potential for widespread adoption, finding practical applications in diverse industrial settings as well as in residential use. Novelty: The suggested method implies that the topology presents distinctive or beneficial characteristics in contrast to current solutions, rendering it especially promising for a range of industrial and residential applications. This novelty may arise from enhancements in efficiency, cost-effectiveness, scalability, versatility, or other favorable attributes that distinguish it from traditional approaches. Moreover, Simulation outcomes distinctly demonstrate a noteworthy decrease in leakage current within the refined topology when contrasted with both the H5 topology and the High Efficient and Reliable Inverter Concept (HERIC) topology. This compelling evidence affirms the effectiveness of the proposed configuration in proficiently mitigating leakage current. Keywords: Photovoltaic, Common Mode Voltage, Leakage Current, Grid Connected Inverter

A virtual space vector modulation strategy for suppressing common-mode voltage in dual-output T-type three-level converters

A virtual space vector modulation strategy for suppressing common-mode voltage in dual-output T-type three-level converters

A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse

A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 μm CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply.

Non-Weighted Two-Stage Model Predictive Control Strategy Based on Three-Level NPC Inverter

This paper investigates the asynchronous motors driven by a Three-Level Neutral-Point-Clamped Voltage Source Inverter (3L-NPC-VSI) and aims to achieve control without weight factors and reduce torque ripple. It puts forward a non-weighted two-stage Finite-Control-Set Model Predictive Control (FCS-MPC) strategy. First, a hierarchical optimization method is adopted to address the difficulty of setting weight factors in traditional FCS-MPC applications. The method offers stratified designs of three performance indices, voltage jump, common-mode voltage, and current tracking, obviating the need for weight factor setting and reducing the calculation load of predictions. Secondly, to further mitigate torque ripple, an optimal vector or vector combination is implemented at the current control layer by adhering to the principle of minimal current tracking error. During the selection of the optimal vector combination, the first vector of the combination is chosen to be the vector at the end of the present cycle. This ensures that there is at most one switch within each control period, reducing the switching losses of the two-stage FCS-MPC. Lastly, detailed simulation and experimental analyses are conducted to verify the feasibility and effectiveness of the proposed strategy.

A boost converter-based CSI-fed PMSM drives with common-mode voltage suppression for low-input voltage application

A boost converter-based CSI-fed PMSM drives with common-mode voltage suppression for low-input voltage application

Dual three-phase permanent magnet synchronous motors model predictive torque control based on zero common-mode voltage

This article proposes a multi-vector model predictive torque control strategy based on zero common-mode voltage to suppress common-mode voltage and harmonic currents in a dual three-phase permanent magnet synchronous motor. Firstly, 20 zero common-mode voltage vectors are selected from the traditional 64 basic voltage vectors. By synthesizing these 20 vectors into 6 virtual voltage vectors (VVV), control over the harmonic plane is achieved, reducing harmonic currents and eliminating common-mode voltage. Then, the control error of the flux is reduced by increasing the number of vectors to achieve the purpose of reducing the flux ripple. Finally, through duty cycle modulation, multi-vector model predictive torque control extends the modulation range to the entire sector plane. Simulation results confirm that this strategy can effectively suppress harmonic currents and common mode voltage.

Development of a low-power SAR ADC for analog front-end readout circuit of hydrophones

A low-power 16 bit 250KSa/s successive approximation analog-to-digital converter (SAR ADC) is designed. The capacitor array consists of a 2-segment sub-capacitor array and high sampling makes the coupling capacitance a unit capacitance, solving the problem of fractional capacitance mismatch. The power consumption is reduced by introducing a common-mode voltage during the switching process of the capacitor array. The circuit uses a 4-stage pre-amplifier and adds a dynamically latched comparator using output misalignment calibration to ensure high accuracy resolution. Simulated in DB Hitek 0.18 μm process, the Fast Fourier Transform(FFT) simulation results for 4096 points show that the signal-to-noise distortion ratio (SNDR) of the ADC can reach 90.2 dB and the effective number of bits (ENOB) can reach 14.69 bit. The average power consumption is 2.507mW at a supply voltage of 5 V, and this holds significant significance for the long-term deep-sea detection capabilities of sonar systems.

A Discrete Selective Harmonic Elimination Formulation With Common-Mode Voltage Elimination Ability

A Discrete Selective Harmonic Elimination Formulation With Common-Mode Voltage Elimination Ability

Performance Analysis of a Dual-Inverter-Fed Open-End Winding Induction Machine under Asymmetrical Control: Theoretical Approach and Experimental Validation

Currently, power trains based on an Open-End Winding Induction Machine fed by a Dual Inverter (DI-OEWIM) are attracting a great deal of interest in various modern industrial applications. However, applying symmetrical control to this system (DI-OEWIM), which is symmetrical in nature, will lead to malfunction. Therefore, the objective of this paper is to explore the influence of asymmetric control on the performance of this system. The principle of this study is to create an asymmetrical control by integrating a phase-shift angle in the Space Vector Pulse Width Modulation (SVPWM) strategy. We then evaluate the impact of these angles on various performances, such as the Total Harmonic Distortion (THD), power losses, Common Mode Voltage (CMV), Zero-Sequence Voltage (ZSV), rotation speed and torque ripple of this system. This study was carried out in the Matlab/Simulink environment and was validated experimentally using the dSPACE 1104 board. The results show that the different angles have significant effects on the overall performance of this system.

Methods to Improve Suppression of Leakage Current Generation in Single-phase Non-isolated Photovoltaic Grid-connected Inverters

Analysis of methods to suppress leakage current through the topology of a single-phase inverter is carried out, aiming to address the phenomenon that disturbs the normal operation of electrical equipment and poses risks to human life when equipment integrates the electrical system into the grid. The topology of a single-phase inverter is taken as the research object, whose issues will be researched and summarized. First of all, by analyzing the single-phase inverter circuit, a simplified equivalent circuit is obtained. Then during the simplification process, it can be concluded that the generation of leakage current is related to the rate of change of common-mode voltage. After that based on this phenomenon, the general direction for suppressing leakage current has been obtained: when the electrical equipment links to the grid: keep Vcm constant, and four clear methods to suppress leakage current. Then reanalyze the way some new non-isolated grid-tied inverter topology how to suppress leakage current. Eventually, the conclusion would be reached.

Common-Mode Voltage Reduction Method Based on Variable Sampling Frequency Finite Control Set-Model Predictive Control for PMSM Drive Systems

In this article, a finite control set-model predictive control (FCS-MPC) with variable sampling time is proposed. A zero-voltage vector appears in the dead time between specific voltage vectors, resulting in an unintentionally large common-mode voltage. Herein, a large common-mode voltage was suppressed, and the load current was controlled using a voltage vector combination that did not cause a zero-voltage vector in dead time. Additionally, to improve the total harmonic distortion (THD) of the load current, the intersection of the predicted current and the command current by all the volage vectors (VVs) in the combination is confirmed. The VV where the intersection occurs is selected as the optimal VV. This optimal VV is applied to the point where the predicted current and the reference current intersect. The applicable range of the sampling time should be selected by considering the calculation time and number of switching. Through the proposed FCS-MPC strategy, not only can the common-mode voltage be limited to within ±Vdc/6, but an improved THD can also be obtained compared to the existing method using fixed sampling. The proposed method was verified through PSIM simulation and experimental results.

An Algorithm for a Space-Vector Pulse Width Modulation with a Hybrid Switching Sequence for a Three-Level Neutral Point Clamped Voltage Source Inverter

This paper proposes a new algorithm for a space-vector pulse width modulation (SVPWM) with a hybrid switching sequence (SS) designed to control a three-level (3L) neutral point clamped (NPC) voltage source inverter (VSI). Based on the advantages of five-stage and seven-stage SS, we designed a hybrid SS to improve four key parameters in the system: inverter output current quality, neutral point (NP) and common-mode (CM) voltage levels, and switching losses of power switches. The proposed algorithm flexibly regulates meeting the four criteria depending on the system operating conditions by changing the regulation coefficient. The paper obtained an approximate dependence to determine the optimal regulation coefficient for any values of the inverter modulation coefficient when operating jointly with an active-inductive load. The effectiveness of the proposed algorithm is confirmed by computer simulation in the MatLab+Simulink environment, as well as the results of experimental studies. The paper presents the experimental dependences of static state spaces, including the distortion coefficient of higher current harmonics at the inverter output, the maximum error of the NP voltage, the number of switching pairs of power switches, and the pulse duty factor of CM voltage, depending on the inverter modulation coefficient and the regulation coefficient of the hybrid SS. The results showed that in the algorithm for a SVPWM with a hybrid SS, the number of switchings of power switches is reduced by an average of 13.5 % while maintaining the NP voltage balance and the quality of the curve at the inverter output at an acceptable level, close to a seven-stage SS (the deviations do not exceed 0.5 % and 0.2 %, respectively). The average CM voltage coefficient decreased by no more than 4.5 %. The indicators improve the energy saving, the weight-size parameters, and the operational reliability of the 3L NPC VSI. The application area of the algorithm is much wider and includes the control of power switches of active front ends, grid converters for electricity storage systems, active power filters, and power conditioners. DOI: https://doi.org/10.52783/pst.237

Common-Mode Voltage Reduction of Modular Multilevel Converter Using Adaptive High-Frequency Injection Method for Medium-Voltage Motor Drives

This study proposes an adaptive high-frequency injection method (AHFI) aimed at mitigating common-mode voltage (CMV) on the AC side and alleviating current stress on power semiconductor devices within each arm of a medium-voltage motor propulsion system designed for modular multilevel converters. By adjusting the quantity of high-frequency components injected into each arm according to the fluctuation coefficient, the amplitude of injected high-frequency CMV and circulating currents can be reduced across medium to rated motor speeds. This approach enhances the start-up performance of medium-voltage motor drives while diminishing CMV effects on the motor side, resulting in decreased total harmonic distortion (THD) in the three-phase output waveforms. Furthermore, the effectiveness of the proposed AHFI method in SM voltage regulation and circulating current control under low-frequency operation is thoroughly analyzed. The validity of this method is established through comprehensive mathematical scrutiny and time–domain simulations performed using MATLAB/SIMULINK software, along with real-time simulations conducted employing the real-time simulator OPAL/RT via hardware-in-the-loop simulation (HILS).

A 0.6V 119 dB High-CMRR Low-NEF PGA with common-mode voltage control for ECG recording

This paper proposes a programmable gain amplifier (PGA) with common-mode voltage control for ECG recording. In order to ensure that input common-mode interference (CMI) does not deteriorate amplifier performance, a novel common-mode voltage control module is proposed, which soaks up CMI and maintains the common-mode input within the expected range. Utilizing a standard 65 nm CMOS process, our PGA runs on a 0.6 V supply. This amplifier has a frequency response range of 10 Hz–57.0 kHz, a gain range of 0 dB–24 dB, and a noise efficiency factor (NEF) of 4.17. Its common-mode rejection ratio (CMRR) is over 119.2 dB, and input reference noise within the amplifier bandwidth is 6.6 μVrms.

On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity

The paper proposes an ameliorated methodology to minimize the effect of charge injection over a wide input common-mode range. Instead of a conventional single dummy switch compensation [1], the multi-dummy switches are proposed and employed to eradicate the injected charge on to the sampling capacitor. A detailed methodology is presented to compensate the charge injection in a MOS switch. The closed-form equations are derived mathematically to substantiate the proposed technique. For the proof-of-concept, a track-and-hold (T/H) stage has been simulated in 0.18μm CMOS technology with the proposed technique for a 10-bit resolution. The proposed technique based T/H stage exhibits the spurious free dynamic range (SFDR) of 62.6 dB, effective number of bits (ENOB) of 9.36, peak input-referred third-order intercept point (IIP3) of 13.02 dBm and an input-referred 1 dB compression point (P1dB) of 3.8 dBm at 1.074 MHz input frequency, sampled at 100 MSa/s. The performance of the proposed method is compared with the existing single dummy switch compensation method where our technique shows 88.8% compensation in minimizing the charge injection error and 272% improvement in dynamic linearity. Moreover, the presented technique quantifies 9× improvement in mean percentage error (MPE) when simulated across the various process corners and rail-to-rail input common-mode voltage.

Nonisolated Three-Phase Current DC-Link Buck–Boost EV Charger With Virtual Output Midpoint Grounding and Ground Current Control

Non-isolated three-phase AC/DC converter concepts facilitate more compact and more efficient realizations of future EV chargers. However, without the galvanic isolation and/or high common-mode (CM) impedance provided by an isolation transformer, non-isolated chargers must employ other means to suppress CM leakage currents to ground sufficiently and to prevent nuisance tripping of mandatory residual current devices (RCDs). Typically, the required EMI filters reduce high-frequency (HF) CM leakage currents to uncritical values. However, low-frequency CM voltages, e.g., generated by third-harmonic injection, may drive significant LF CM currents through the parasitic capacitances of the DC output (including the battery pack) to protective earth (PE). Therefore, considering a non-isolated three-phase buck-boost current DC-link PFC rectifier system that consists of a buck-type current-source rectifier (CSR) stage and a three-level boost-type DC/DC-stage, this paper first proposes a virtual grounding control (VGC) of the DC output voltage midpoint. VGC employs the DC/DC-stage to compensate the LF (third-harmonic) CM voltage inherently generated by the CSR-stage, and thus controls the LF CM voltage between the DC output midpoint and PE to zero. This enables further a direct connection of the DC output midpoint to PE, where an additionally proposed ground current control (GCC) ensures near-zero LF CM leakage current. The proposed concepts are verified with a 10kW hardware demonstrator (power density of 6.4 kW/dm3 or 107.5 W/in3, full-load peak efficiency of 98.5%) considering TT (Terra-Terra) and TN (Terra-Neutral) grounding systems. With a direct connection of the DC output midpoint to PE, GCC limits the LF CM leakage current to < 6mA RMS, i.e., significantly below typical RCD trip levels, and, using the human-body impedance model according to UL 2202, achieves a test voltage of 110mV that is clearly below the most stringent limit (250 mV) of the standard.

ПІДВИЩЕННЯ ЯКОСТІ ВІБРАЦІЙНОЇ ДІАГНОСТИКИ ВУЗЛІВ ТА АГРЕГАТІВ АГРАРНОЇ ТЕХНІКИ

It is known that friction and vibrations are the main factors affecting the condition of the equipment during its operation. Therefore, monitoring and diagnostics of vibration resistance of machines and mechanisms are of great importance for their effective operation. This article will present and describe methods of vibroacoustic diagnostics, which are simple and sensitive for detecting defects in various mechanisms and machines, in particular in the agricultural sector. One of the key elements used to diagnose and control the degree of wear of parts is a piezoelectric transducer. It is easy to use and highly accurate. Such converters are almost not affected by electric and magnetic fields, acoustic signals and other mechanical vibrations, except in certain cases. This article will consider the improvement of the piezoelectric transducer, which can be used to measure the vibration rate of oscillations of elements and assemblies of agricultural machines. The technical solution includes the use of a differential amplifier with buffer stages connected to a basic differential amplifier. This approach allows you to reduce the impact of out-of-band interference and increase measurement accuracy. The use of a common-mode perturbation voltage is also an important element in the improved piezoelectric transducer, helping to provide more accurate results. This article reveals important aspects of vibration diagnostics and offers a new technical solution to improve measurements. It will be useful for specialists in the field of mechanical engineering and agricultural industry, who are interested in effective control and support of machines and mechanisms during their work.

Low-Complexity Heun's Method-Based FCS-MPC With Reduced Common-Mode Voltage for a Five-Level Inverter

Low-Complexity Heun's Method-Based FCS-MPC With Reduced Common-Mode Voltage for a Five-Level Inverter

A Transformerless Converter with Common-Mode Decoupling in Low-Voltage Hybrid Grids

Compared with isolated converters, transformerless converters are a preferred choice in low-voltage grids due to their efficiency and lower cost. However, leakage current and common mode (CM) voltage appear through the converter and ground in hybrid grids, which consist of AC and DC subgrids. The leakage current and CM voltage seriously influence operation and power quality in low-voltage distribution systems. This paper proposes a common-ground-type (CGT) converter equipped with a CM decoupling control strategy to eliminate the leakage current and CM voltage. A CM model is derived, and the leakage current and CM voltage are analyzed in detail. A CGT four-leg converter is constructed to eliminate the high frequency CM voltage. A dual DQ current control loop is developed to suppress the DC double-frequency ripple. Additionally, an active damping method is proposed, based on the neutral current feed-forward plus inductor current feedback, to attenuate the low frequency CM voltage. The proposed converter and control strategy guarantees excellent performance in suppressing leakage current and CM voltage. The DC voltage of the converter connected to the DC grid maintains stability and symmetry. The leakage current is significantly reduced, and the leakage current suppression performance is improved by 83%. The high frequency CM voltage is attenuated from 50%udc to 2%udc, and the low frequency CM voltage is suppressed from approximately 32%udc to 3%udc, which is a significant improvement compared with the traditional method. In addition, the proposed control strategy has good transient performance when the load changes abruptly. Finally, an experimental platform is established to validate the feasibility and performance. The experiment results showed that the proposed control strategy improves the system performance and power quality.

Mitigation of common mode voltage in ultra sparse matrix converters using auxiliary shoot‐through switches for wind energy systems

SummaryThis paper targets to minimize the peak common mode voltage (CMV) in ultra sparse matrix converters (USMC) by applying new zero vectors for the space vector modulation technique (SVM). Conventional zero vectors in the SVM raise the peak CMV by 42.23%. An increased magnitude of CMV is associated with the occurrence of leakage current, hence resulting in insulation degradation. So, the reduction of peak CMV is necessary for USMC. The proposed method offers suitable switching arrangements using auxiliary shoot through (AST) switches to minimize the peak‐to‐peak CMV. This proposed method holds the advantages of the conventional method, like a wide range of modulation index and zero current switching at the rectifier side, and also reduces the CMV problem. This paper also provides a comparative analysis of the existing reported methods and the proposed method. The effectiveness of the proposed method is validated through both simulation and experimental results.