Common-mode Voltage Research Articles

A Low-Power SAR ADC with Capacitor-Splitting Energy-Efficient Switching Scheme for Wearable Biosensor Applications.

A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage Vcm, and common-mode techniques, the proposed switching scheme achieves 93.76% less switching energy compared to the conventional scheme with common-mode voltage shift in one LSB. With the switching scheme, the proposed SAR ADC can lower the dependency on the accuracy of Vcm and the complexity of digital control logic and DAC driver circuits. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low sampling error sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrate that the ADC achieves a 61.77 dB SNDR and a 78.06 dB SFDR and consumes 4.45 μW of power in a 180 nm process with a 1 V power supply, a full-swing input signal frequency of 93.33 kHz, and a sampling rate of 200 kS/s.

Modified SVPWM technique for CMV reduction in asymmetrical dual three phase induction machine drive

Due to its advantages, the asymmetrical dual three-phase induction motor drive is a strong choice in high-power applications. However, the common-mode voltage produced by the voltage source inverters affects the winding insulation and damages the bearings. Common-mode voltage is also responsible for electromagnetic interference and leakage currents. This paper, therefore, analyses the common-mode voltage produced by the inverter supplying a dual three-phase induction motor drive and proposes a novel modified space vector decomposition-based Space Vector Pulse Width Modulation (SVPWM) technique for common mode reduction. The vector space decomposition-based space vector modulation technique offers excellent flexibility as it reduces the common-mode voltage (CMV) by exploiting the additional degree of freedom in a dual three-phase system. The common-mode voltage (CMV) can be reduced to one-sixth of the DC link voltage compared to the highest CMV, i.e. half of the DC-link voltage produced in conventional space vector modulation. The proposed method is also validated experimentally to demonstrate the effectiveness of the proposed scheme in terms of the amplitude of CMV, pulsations, and total harmonic distortion(THD) in current.

Characteristics of Common-Mode Voltage Offset in Small Sectors and OC Fault Diagnosis Method for Three-Level Inverter

Characteristics of Common-Mode Voltage Offset in Small Sectors and OC Fault Diagnosis Method for Three-Level Inverter

Electrostatic discharge impacts on the main shaft bearings of wind turbines

Abstract. This paper studies the electrostatic discharge effect in wind turbines, a possible trigger source of the main bearing current. A lab setup with a charge generator and downsized wind turbine was built to verify the impact of electrostatic discharge on the main bearing current. In the test, a fatal amplitude for the bearing current was found at only −93 mV driven voltage on the shaft. Compared with the bearing current driven by the common-mode voltage, the electrostatic discharge effect triggers the bearing breakdown at a lower shaft voltage but much higher bearing current amplitude. The results demonstrate that the electrostatic discharge effect is a pattern of the bearing current in wind turbines and is much more dangerous to the bearing.

Common-Mode Voltage Reduction for Back-to-Back Two-Level Converters Based on Zero-Sequence Voltage Injection

High frequency and high amplitude common-mode voltage (CMV) can induce a number of problems on the reliable operations of back-to-back two-level converters, such as shaft voltages and bearing currents. To restrain the CMV for back-to-back two-level converters, a simple and effective CMV reduction method based on zero-sequence voltage (ZSV) injection is proposed in this article. By injecting the optimal amount of ZSV on either the rectifier-side or the inverter-side, the corresponding pulse overlapping areas that result in high CMV amplitudes can be eliminated with the proposed method, then the amplitude of CMV can be reduced by half, and the pulse edges of CMV can be reduced by one-third. Simulation and experimental results are presented to verify the effectiveness of the proposed method in CMV reduction, while some comparisons are also conducted to demonstrate the superiority of the proposed method.

Analysis and Simulation Test of Electromagnetic Disturbance Mode Conversion in Secondary Circuit of Substation

Under ideal conditions, the electromagnetic interference experienced by the secondary circuit is manifested as a common mode. However, due to circuit imbalance, common mode disturbance is converted into differential mode disturbance, thereby presenting a danger to the normal functioning of secondary equipment. The investigation measured the distribution ratio of common mode voltages and differential mode voltages at the ports of secondary equipment during switching operations. A computational circuit model of the secondary circuit was established by using multi-conductor transmission line theory. The mechanisms and influencing factors of transformation from common mode to differential mode were analyzed, and a simulation test was carried out in a substation to explore the conversion law under impedance imbalance. The results showed that the differential mode voltage of the secondary equipment port was greater than the common mode voltage when the circuit breaker was in operation. Common-differential mode conversion in the secondary loop was predominantly caused by an imbalance in circuit structure and extraneous parameters. Differential mode disturbance generated by switch field side imbalance had a greater impact than that generated by protection chamber side imbalance. As the degree of imbalance increased, the differential mode voltage also increased.

An Improved Modulation Scheme of Isolated Matrix Converter for Common-Mode Voltage Reduction and DC-Bias Current Mitigation

In this paper, an optimized space vector modulation (SVM) method is proposed for the isolated three-phase matrix-type AC/DC converter, where the four-quadrant operation ability of the bidirectional power switch can be fully used. The primary-side transformer current can be eliminated naturally during zero current vectors without extra switching actions. Therefore, the conduction loss of matrix converter (MC) is reduced and the efficiency can be increased. Moreover, the proposed method can avoid the shoot-through operation in MC, and the common-mode voltage can be mitigated effectively. As the zero current vector is kept with the proposed modulation strategy, the current harmonics will not be increased. Thirdly, both the DC-link inductor current and DC-bias current of high-frequency transformer (HFT) are measured through the secondary-side current of HFT. Therefore, the DC-bias current and the saturation of HFT are avoided by closed-loop control with the proposed modulation strategy. The experiments have been carried on a 1-kW laboratory prototype to verify the validity of the proposed modulation scheme.

Mitigation of PQ issues in EV charging station connected distribution system using novel RSMLI-based shunt APF

<span>In the present scenario, the significant use of electric vehicles (EVs) is growing rapidly in the automotive industry due to cheaper transportation, no fossil fuel required, low maintenance, no fuel cost, and low impacts on the environment over the formal internal combustion engine (ICE) vehicles. In actuality, these EVs are powered by batteries that are charged by a utility-grid-based charging facility. A power-electronic conversion-based charging device is used in this charging station to charge the battery packs in the EV system. The problem statement of this work is identified, these conversion devices in charging units proliferate the power quality of the utility grid. To overcome these problems, a classical square-wave inverter-based active power filter (APF) is employed. The major problems in classical inverters are high common-mode voltage, more harmonic profile, high dV/dt stress, high switching stress, and low efficiency. The contribution of this work is proposing the multilevel inverter (MLI) based APF for better compensation over classical inverters. In this approach, a novel reduced-switch MLI-based APF has been proposed for the mitigation of harmonic currents and also enhances the power factor in utility-grid-connected distribution systems. The effectiveness of the proposed reduced-switch multilevel inverter (RSMLI)-APF is validated by integrating the number of charging units with the MATLAB/Simulink tool, and simulation outcomes are shown along with comparisons.</span>

A Fault-Tolerant Control Strategy for Three-Level Grid-Connected NPC Inverters after Single-Arm Failure with Optimized SVPWM

Three-level NPC inverters have been widely used in grid-connected systems due to their superior performance compared with two-level inverters, but more switches lead to high fault probability. Meanwhile, the neutral point potential (NPP) fluctuation of the DC link is an inherent problem of three-level NPC inverters. To keep the three-level NPC inverter running stably after single-arm failure, a fault-tolerant control strategy based on an optimised space vector pulse width modulation (SVPWM) is proposed in this paper. Firstly, the common-mode voltage (CMV) of the postfault three-level NPC inverter is analysed and then the preliminary synthesis principles of the reference voltage vector are determined. Then, in order to ensure the NPP balance and the quality of the grid-connected currents, the reference voltage vector synthesis rules are optimised, a low-pass filter (LPF) and a hysteresis comparator are designed, respectively, to ensure the quality of grid-connected currents and effectively decrease the DC link NPP deviation. Finally, the simulation results show that the proposed fault-tolerant control strategy can realize the stable and reliable operation of the grid-connected three-level NPC inverter after single-arm failure, and the CMV can be reduced significantly, the quality of grid-connected currents is also improved. The proposed fault-tolerant strategy also shows good performance when the grid-connected currents change.

Implementation of Passivity-based Control of Four-Leg Inverter for Transformerless Three-Phase Solar Photovoltaic Systems

This study explores the application of a passivity-based control technique (PBC) with an artificial neuro-fuzzy inference system (ANFIS) in a grid-connected Solar Photovoltaic (SPV) generating system for estimating reference grid currents. To optimise the tracking of the maximum power point (MPPT) between the solar photovoltaic (SPV) system and the DC bus, a DC – DC boost converter (BC) is utilised. This converter is connected to a four-leg, three-level neutral-point-clamped converter (4-leg 3L-NPC), interfaced with a three-phase, four-wire distribution system. The four-leg 4-leg 3L-NPC of the SPV generating system with Space vector pulse width modulation technique (SVPWM) is utilised for reducing common-mode voltage (CMV), leakage current (LC), reactive power for zero voltage regulation, power factor correction, load balancing, and the elimination of load harmonic currents in the proposed distribution system.The performance analysis of the proposed system is conducted on the Matlab/Simulink platform. Additionally, a comparative analysis is presented, contrasting the proposed system with a 3-phase 4-leg T-type neutral-point-clamped converter (TNPC) employing the PBC technique followed by ANFIS.

Low-frequency operation control method for medium-voltage high-capacity FC-MMC type frequency converter

The application of modular multilevel converters (MMCs) to large drive systems is subject to severe low-frequency operation restrictions. The fluctuation of capacitor voltage and the high amplitude of common mode voltage in sub-modules is a thorny problem. In this paper, a novel fly-across capacitor modular multilevel converter topology is adopted to eliminate low-frequency voltage ripples by using the fly-across capacitor as a power transfer channel between the upper and lower bridge arms of the MMC. A novel finite compensation method is proposed—instead of the traditional full compensation method—that introduces a real-time variable limiting factor to change the amplitude of the mixed injected high-frequency differential-mode voltage and high-frequency differential-mode current and reduce the amplitude of the common-mode voltage on the AC side while lowering the current stress of the power devices. Finally, a complete system simulation model is constructed, and the topology with the proposed control strategy are verified to have good output characteristics under different operating conditions; good results are achieved in suppressing the sub-module fluctuation and common-mode voltage.

Terminal Voltage and Common Mode Voltage Analysis for Various PV Inverter Topologies

The switching function method is critical for understanding the effect of different switching mechanisms or Pulse Width Modulation (PWM) designs on both terminal voltage and common mode voltage. The switching patterns of numerous five-level inverter topologies are determined using modified PWM in this study. The switching function technique is used in this study to investigate the terminal voltage of the PV array and the common mode voltage of the inverter. Notably, as compared to normal PWM approaches, five-level common mode voltage source inverters (CMLIs) need less carrier waves. The study gives thorough insights into the overall architecture of the examined converter, as well as terminal and common mode voltage expressions. When compared to normal PWM, any five-level CMLI requires less carrier waves. This document also details the converter’s overall structure, terminal and common mode voltage expressions, and switching patterns.

Power Conversion Systems with Synchronous Control and Regulation on the Base of Powerful Diode-Clamped Inverters via Pulse Width Modulation

This article provides a brief overview of the development and dissemination of the method of synchronous multi-zone pulse-width modulation (PWM) in relation to the regulation of diode-clamped inverters which are the main executive elements of the medium-power and high-power adjustable speed electric drives. It is shown that the modified schemes and algorithms of synchronous multi-zone PWM, applied for control of diode-clamped inverters, assure providing minimization of the common-mode voltage in systems, as well as continuous synchronization and symmetry of the base phase and linear voltages in drive systems on the base of diode-clamped inverters over the entire control range. There are no even harmonics and subharmonics in the spectra of the phase and line-to-line voltages of three-phase and six-phase drive systems, which helps to reduce losses in systems and increase the efficiency of their operation. As a result of a comparative analysis of the integral spectral characteristics of the main voltage waveforms of adjustable speed drives based on diode-clamped inverters, recommendations are formulated for the rational choice of schemes and algorithms of synchronous multi-zone PWM for the relevant systems and installations, depending on their operating modes.

A 10-bit 160 MS/s Asynchronous SAR ADC design

This study describes a 10-bit 160 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) design in a 40 nm CMOS technical process. The SAR ADC is provided with an improved capacitive digital-to-analog converter (CDAC), and the capacitor array is featured by six split high-bit capacitors and a combination of splitting and monotonic switching schemes. This structure and switching scheme can both save power and improve speed while introducing negligible common-mode voltage change. An improved double-tail comparator and TSPC D flip-flops are implemented to further enhance the speed. Simulation results show that the ADC achieves SFDR 72.17 dB, SNDR 61.37 dB, and ENOB 9.90 bits at Nyquist input frequency. The power consumption of the ADC under a 1.2 V power supply is 2.808 mW, achieving 18.4 fJ/conv FoM.

A Low Common-Mode SVPWM for Two-Level Three-Phase Voltage Source Inverters

In order to reduce the common-mode voltage (CMV) generated by the use of space vector pulse width modulation (SVPWM) in two-level three-phase voltage source inverters, a low common-mode SVPWM method is proposed. In this method, the voltage plane is divided into 12 sectors, and on each sector, two non-zero vectors of the same class and one single zero vector are adopted for synthesis. The action time of the zero vector is placed at both ends of each switching cycle, the currents are sampled at the beginning of each switching cycle, and the action time and sequence of vectors on each sector is provided. Simulation and experimental results show that, in the vector control system of a permanent magnet synchronous motor fed by the inverter, compared with the conventional SVPWM, the proposed method reduces the CMV peak-to-valley value by 33.333%, the CMV jump frequency by three times, and the performance of the line voltage and line current. The electromagnetic torque and rotor speed remain good, which has good application value in high-performance drives.

Enhancing the Performance and Efficiency of Two-Level Voltage Source Inverters: A Modified Model Predictive Control Approach for Common-Mode Voltage Suppression

In this paper, a new modified model predictive control is proposed to improve the performance of the model predictive control for two-level voltage source inverters by alleviating computational burden and the disadvantages associated with the conventional model predictive control strategy. The objective of the proposed method is to reduce the number of candidate voltage vectors in each sector, thereby improving the overall performance of the control system, as well as achieving common-mode voltage reduction for two-level voltage source inverters. Two strategies are introduced to achieve this objective. Firstly, an algorithm is developed based on statistical computational processes to pre-define the candidate voltage vectors. This strategy involves ranking and considering the most frequently used voltage vectors. Consequently, by reducing the computational burden, the search space for the optimal voltage vectors is reduced. Furthermore, based on statistical results, a strategy is proposed to divide the sectors into three sectors instead of the six sectors in the conventional method. This approach effectively reduces the number of candidate voltage vectors. The modified model predictive control strategy aims to improve the efficiency of the control system by reducing the computational burden, and suppressing the common-mode voltage. The simulation and experiments are carried out to verify the effectiveness of the proposed strategy under various operational conditions. The results demonstrate that the modified model predictive control approach significantly reduces the computational burden and complexity of the control system while effectively suppressing the common-mode voltage; this contributes to improving the performance of two-level voltage source inverters and enhancing their applicability for connecting the renewable energies to the grid.

Experimental Study of Radiated Emission Due to Secondary Common-Mode Current in Buck Converters

High switching frequency and fast switching speed of wide bandgap power semiconductor device-based power converters may increase radiated emissions more than conventional silicon-power device-based power converters. Based on the background, this article experimentally investigates radiated emission sources in buck converters. The experimental system constructed in this article has two common-mode noise paths, the primary common-mode and the secondary common-mode. First, this article outlines that a secondary common-mode voltage source is caused by a primary common-mode current and an imbalance of power supply side impedances, and the secondary common-mode current path acts as a monopole antenna. The common-mode currents and the radiated emissions are measured in an anechoic chamber when the common-mode inductor for each mode is connected. The measurement results show that the primary common-mode current generates the secondary common-mode noise, and the secondary common-mode noise is the dominant source of radiated emission in the experimental system.

A Comparative Review of Three Different Power Inverters for DC–AC Applications

This paper presents a comparative review of three different widely used power inverters, namely the conventional six-switch inverter; the reduced switch count four-switch inverter; and the eight-switch inverter. The later inverter can be reconfigured as a neutral-point diode-clamped inverter at the failure of one inverter leg. The three power inverters are compared and discussed with respect to cost, complexity, losses, common mode voltage, and control techniques. The paper is intended to serve as a guide regarding selecting the appropriate inverter for each specific application. Simulation results are presented to demonstrate the performance of the three power inverters, followed by a comprehensive comparison between the three power inverters.

Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

The utilisation of low power SAR (Successive Approximation Register) Analog-to-Digital Converters holds significant importance in the domain of bio-medical signal acquisition. The present study showcases the utilisation of an 8-bit CMOS SAR-ADC for integration into the analog front end of bio-signal acquisition. The focus of this technology pertains to the monitoring of implanted bio-signal devices, with a specific emphasis on ECG/EEG signals. A capacitive digital-to-analog converter (DAC) is suggested as a means to attain power consumption in the microwatt range. This approach enables comparisons to be made without any energy consumption, leading to a substantial enhancement in energy efficiency. Furthermore, a comprehensive theoretical examination of comparator offset voltages has been conducted to enhance the offset performance of the comparator operating at low supply voltage. The analysis indicates that optimization of the comparator is achieved solely through the adjustment of transistor sizes, without the implementation of any specific offset cancellation techniques. Simulations indicate that the optimization of the offset voltage to approximately 5 mV occurs when there is variation in the common-mode input voltage at a 1 V supply. The proposed Analog-to-Digital Converter (ADC) layout has been successfully executed utilizing the 45 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The Analog-to-Digital Converter (ADC) attains a Spurious-Free Dynamic Range (SFDR) of 64.02 dB and consumes 1.9 μW of power at a sampling rate of 1.1 MHz and a supply voltage of 1 V.

Improved virtual SVPWM algorithm for CMV reduction and NPV oscillation elimination in Three-Level NPC inverter

An improved virtual space vector pulse-width modulation (IVSVPWM) strategy is presented to address simultaneously the problem of common mode voltage (CMV) with neutral point voltage (NPV) fluctuations in wind power converters. The proposed IVSVPWM method suppresses the amplitude of the common mode voltage to Udc/6 by discarding the positive small vector. Meanwhile, the new virtual vector is synthesized by selecting a vector whose neutral point current sums to zero among the retained voltage vectors. In addition, a feedback mechanism is established in the proposed strategy. According to the feedback result, the distribution coefficients of each basic vector in the virtual vector are recalculated to suppress the NPV fluctuation. Through the above control strategy, the dual effect of suppressing the CMV and balancing the NPV is achieved in the full modulation. The feasibility and effectiveness of the strategy are verified by simulation and experiment.© 2017 Elsevier Inc. All rights reserved.