Common-mode Voltage Reduction Research Articles

Common mode voltage reduction of cascaded multilevel inverters using carrier frequency modulation

ABSTRACT Cascaded multilevel inverters have been increasingly used in industrial applications. However, the quality of the output voltage of these inverters depends highly on the modulation techniques. One of the factors affecting the quality of the inverter output voltage is the existence of common mode voltage. This affects the life of three-phase electric motors connected to the inverter. This paper presents a method of modulating the carrier frequency for cascaded multilevel inverters to reduce common mode voltage and harmonics. In the proposed method, the carrier frequency modulator is considered an adaptive controller and the carriers are completely controlled by the control signal. Changes of control signals such as amplitude, frequency, and phase angle make the carrier frequency vary accordingly. In addition, the ability to reduce common mode voltage also helps increase the amplitude of the inverter output voltage. Moreover, an algorithm for reduction of switching commutations is also proposed to reduce the switching loss. The simulation and experiment results based on a cascaded 5-level three-phase inverter system with an induction motor load have confirmed the performance of the proposed method compared to that of the methods using unmodulated carriers through the comparison of output harmonics and number of switching commutations.

PWM Strategy to Alleviate Common-Mode Voltage with Minimized Output Harmonic Distortion for Five-Level Cascaded H-Bridge Converters

High-frequency components of common-mode voltage (CMV) induce the shaft voltage and bearing current, which lead to premature failures in motors. In addition, due to non-zero average CMV, the low-frequency components of CMV, particularly the third-order harmonic component, have been reported to cause difficulties in common-mode filter design. Furthermore, the utilization of distant voltage vectors in the pulse-width modulation (PWM) with reduced CMV magnitudes gives rise to high output harmonic distortion compared to PWM ones without CMV reduction. In an attempt to solve the aforementioned issues, this article presents a PWM strategy that features reduced CMV magnitudes, zero average CMV, and improved output harmonic distortion for a five-level cascaded H-bridge (CHB) converter. In addition, the carrier rotation technique based on the phase-leg redundancy of the CHB topology is also combined with the proposed scheme to achieve equal power loss distribution among power switching devices. Both simulation and experimental results confirm that the proposed strategy produces better output harmonic distortion than that of POD-SPWM and APOD-SPWM under the condition of reduced CMV magnitudes, zero average CMV, and equal power loss distribution.

Virtual Voltage Vector-Based Model Predictive Current Control for Five-Phase VSIs With Common-Mode Voltage Reduction

Model predictive current control (MPCC) schemes have been considered as a promising control technique for voltage source inverters (VSIs). However, the computational burden reduction, harmonic currents elimination, and common-mode voltage (CMV) mitigation are special issues when MPCC schemes are applied to five-phase VSIs. Moreover, it is time-consuming to tune weighting factors for the multiple control objectives. To address these problems, this article proposes two computationally efficient MPCC schemes based on virtual voltage vectors ( V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> s), named MPCC-V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> -RCMV1 and MPCC-V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> -RCMV2. The former one achieves lower harmonics, whereas the latter one achieves lower switching frequency. The V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> s are defined with basic voltage vectors that generate small CMV; hence, inherent CMV reduction can be achieved. The proposed MPCC schemes simplify the controller by redefining the cost function and control set, which reduces the computational effort significantly. Besides, the proposed MPCCs can improve the quality of current waveforms. Simulations and experiments are carried out to verify the effectiveness of the proposed control schemes.

Sequential Predictive Current Control of a VSI with Common-Mode Voltage Reduction

Sequential Predictive Current Control of a VSI with Common-Mode Voltage Reduction

Common-Mode Voltage Harmonic Reduction in Variable Speed Drives Applying a Variable-Angle Carrier Phase-Displacement PWM Method

Electric variable speed drives (VSD) have been replacing mechanic and hydraulic systems in many sectors of industry and transportation because of their better performance and reduced cost. However, the electric systems still face the issue of being considered less reliable than the mechanical ones. For this reason, researchers have been actively investigating effective ways to increase the reliability of such systems. This paper is focused on the analysis of the common-mode voltage (CMV) generated by the operation of the VSDs which directly affects to the lifetime and reliability of the complete system. The method is based on the mathematical description of the harmonic spectrum of the CMV depending on the PWM method implementation. A generalized PWM method where the carriers present a variable phase-displacement is developed. As a result of the presented analysis, the CMV reduction is achieved by applying the PWM method with optimal carrier phase-displacement angles without any external component and/or passive filtering technique. The optimal values of the carrier phase-displacement angles are obtained considering the minimization of the CMV total harmonic distortion. The resulting method is easily implementable on mostly off-the-shelf mid-range micro-controller control platforms. The strategy has been evaluated in a scaled-down experimental setup proving its good performance.

Improved Model Predictive Current Control for Three-Phase Three-Level Converters With Neutral-Point Voltage Ripple and Common Mode Voltage Reduction

An improved two-stage model predictive current control (MPCC) for three-phase three-level converters in the paper, which can simultaneously achieve common-mode voltage (CMV) reduction, effective dc-link capacitor voltage control, and decreased computational burden, is proposed. Compared to the other current control strategies, it has the capability of handling multiple control objectives and possesses a simple structure. Furthermore, it greatly reduces the CMV since the peak CMVs of all the candidate voltage vectors are constrained to be less than one sixth of the dc-link voltage. In addition, an optimal two-stage voltage vector selection mechanism is employed in the proposed method. It helps to significantly reduce the computational complexity. Simulation and experimental results are provided to verify the effectiveness of the proposed method.

Common-Mode Voltage Reduction in Capacitive Sensing of Biosignal Using Capacitive Grounding and DRL Electrode.

A capacitive measurement of the biosignals is a very comfortable and unobtrusive way suitable for long-term and wearable monitoring of health conditions. This type of sensing is very susceptible to noise from the surroundings. One of the main noise sources is power-line noise, which acts as a common-mode voltage at the input terminals of the acquisition unit. The origin and methods of noise reduction are described on electric models. Two methods of noise removal are modeled and experimentally verified in the paper. The first method uses a passive capacitive grounding electrode, and the second uses an active capacitive Driven Right Leg (DRL) electrode. The effect of grounding electrode size on noise suppression is experimentally investigated. The increasing electrode area reduces power-line noise: the power of power-line frequency within the measured signal is 70.96 dB, 59.13 dB, and 43.44 dB for a grounding electrode area of 1650 cm2, 3300 cm2, and 4950 cm2, respectively. The capacitive DRL electrode shows better efficiency in common-mode noise rejection than the grounding electrode. When using an electrode area of 1650 cm2, the DRL achieved 46.3 dB better attenuation than the grounding electrode at power-line frequency. In contrast to the grounding electrode, the DRL electrode reduces a capacitive measurement system’s financial costs due to the smaller electrode area made of the costly conductive textile.

A Study on Common Mode Voltage Reduction Strategies According to Modulation Methods in Modular Multilevel Converter

Low level modular multilevel converter (MMC) is a promising candidate for medium voltage applications such as MVDC (medium voltage DC current) transmission and megawatt machine drives. Unlike high-level MMC using nearest level modulation (NLM), the low-level MMC using the pulse width modulation (PWM) or NLM + PWM is affected by a common mode voltage (CMV) due to a frequent change of a switching state. This CMV causes electromagnetic interference (EMI) noise, common mode current (CMC) and bearing current leading to a reduction in the efficiency and durability of the motor drive system. Therefore, this paper provides a mathematical analysis on how the switching state affects the CMV and proposes three software based CMV reduction algorithms for the low level MMC system. To reflect the characteristic of MMC modulation strategy for upper and lower reference voltage independently, two separate space vectors are used. Based on the analysis, three different CMV reduction algorithms (complete CMV reduction (CCR), DPWM CMV reduction (DCR) and partial CMV reduction (PCR)) are proposed using NLC + PWM modulation strategy. The performance of the proposed CMV reduction algorithms was verified by both simulation and experimental result.

A Generalized Selective Harmonic Elimination PWM Formulation With Common-Mode Voltage Reduction Ability for Multilevel Converters

In this article, a generalized selective harmonic elimination pulsewidth modulation (SHE-PWM) formulation with common-mode voltage (CMV) reduction ability for multilevel converters (MLCs) is presented. The CMV is suppressed by regulating the low-order dominant zero-sequence harmonics (ZSHs) of the three-phase SHE-PWM waveforms. Two formulations are included in the proposed model to achieve the full range operation objective, i.e., with zero low-order ZSHs in low and medium modulation index (m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> ) range and with an optimal third-harmonic injection in high m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> range. With the proposed formulation, the amplitude of CMV can be effectively reduced for all types of MLCs over the whole m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> range. Besides, two kinds of solving algorithms, i.e., off-line and real-time based, are introduced to provide efficient solution tools targeted at the proposed model. In this article, a case study with three-level neutral-point clamped inverters is discussed in detail to better illustrate the proposed formulation and the coupling effects between the CMV reduction and capacitor voltage balancing objectives of MLCs. Simulation and experimental results based on multiple MLC topologies are carried out to validate the effectiveness of this generalized SHE-PWM formulation with reduced CMV values.

Reduction of common mode voltage for cascaded multilevel inverters using phase shift keying technique

Demand of cascaded multilevel inverters in industries of electric drives and renewable energy is increasing due to their large-scale capacity and high voltage. The modulation technique of inverters significantly affects the power quality of the inverter output voltage. This paper proposes a new method of carrier wave modulation using the phase shift keying technique for cascaded multilevel inverters. The phase of a constant frequency carrier wave is changed at an accurate time by an input sinusoidal control signal. This modulation technique is simply implemented and only needs a small memory. It also helps reduce the common mode voltage of inverters in order to suppress the output voltage harmonics. Moreover, the ability to reduce switching count also helps the inverters decrease switching loss. The simulated and experienced results on a cascaded 9-level 3-phase inverter and an F28379D DSP kit have validated the performance of the proposed technique compared with that of the APOD and POD methods.

A Fast-Processing Predictive Control Strategy for Common-Mode Voltage Reduction in Parallel Three-Level Inverters

Model predictive control (MPC) is an attractive control scheme, in particular, for multilevel converters. However, MPC suffers from high computational burden and tedious tuning of weighting factors especially for parallel three-level inverters. Moreover, the parallel three-level inverters will unavoidably face the challenge of maintaining low circulating current, reducing common mode voltage (CMV), and balancing neutral point (NP) voltage in practice. Therefore, in this article, a fast-processing predictive control strategy is proposed for reducing the zero-sequence circulating current (ZSCC), NP voltage imbalance and CMV simultaneously in parallel three-level inverters. Based on the selected sector by the reference voltage vector, the proposed fast-processing predictive control takes feasible five or six candidate vectors into account; therefore, the computational burden, which is a disadvantage of the predictive control for inverters, will decrease. In addition, the proposed method eliminates the weighting factor, which avoids tedious tuning work. In the proposed control scheme, the candidate vectors are selected for ZSCC, NP voltage imbalance, and CMV reduction, and then, among them, the optimized switching vector is selected by optimizing the cost function. The performance of the proposed method has been validated by the simulation and experimental results.

A Common-Mode Voltage Reduction Method Using an Active Power Filter for a Three-Phase Three-Level NPC PWM Converter

This article proposes a common-mode (CM) voltage reduction method using an active power filter (APF) and common-mode transformer (CMT) for a grid-connected three-phase three-level neutral-point-clamped (NPC) AC-DC pulsewidth modulation (PWM) converter. The CM voltage can be caused by switching operations of converters and the CM voltage should be reduced because it is one of the main causes of electromagnetic interference (EMI) noises. In this article, the CM voltage of the three-phase converter with the proposed APF is analyzed to explain the CM voltage reduction using the proposed APF. Based on this analysis, the application of a specific PWM method to the three-phase converter for an optimal reduction of the CM voltage is described. Besides, the APF circuit design and its switching method are proposed considering practical problems such as the self-resonance of inductors and the effect of the dead-time on the CM voltage. To prove the effectiveness of the proposed APF on the CM voltage reduction, experimental results for the CM voltage and current are presented in this article. Furthermore, EMI noise measurement results are shown to verify the performance of the noise reduction capability of the proposed APF.

Common-Mode Voltage Reduction and Fault-Tolerant Operation of Four-Leg CSI-Fed Motor Drives

This letter proposes a four-leg current-source inverter (CSI) fed three-phase motor drive. Different from the previous four-leg CSI inverter, the proposed configuration introduces the fourth leg in CSI, which connects to the neutral point of the motor through an extra output filter capacitor. Therefore, the proposed configuration can not only reduce the common-mode voltage (CMV) under the normal condition, but also provide the fault-tolerant operation ability under open-circuit faults in windings and switches. The dedicated space vector modulation (SVM) strategies have been designed. Compared with prior research on CMV reduction, the four-leg method has the full range of modulation index and will not increase any harmonics in the currents. Meanwhile, the fault-tolerant ability is offered, which can further enhance the reliability of the motor drive. A laboratory prototype has been built to experimentally verify the effectiveness of the proposed motor drive topology and the control schemes.

Opposite Triangle Carrier with SVPWM for Common-Mode Voltage Reduction in Dual Three Phase Motor Drives

The common-mode voltage (CMV) generated by the switching operation of the pulse width modulation (PWM) inverter leads to bearing failure and electromagnetic interference (EMI) noises. To reduce the CMV, it is necessary to reduce the magnitude of dv/dt and change the frequency of the CMV. In this paper, the range of the CMV is reduced by using opposite triangle carrier for ABC and XYZ winding group, and the change in frequency in the CMV is reduced by equalizing the dwell time of the zero voltage vector on ABC and XYZ winding group of dual three phase motor.

Common-Mode Voltage Mitigation of Dual Three-Phase Voltage Source Inverters in a Motor Drive Application

Electric variable speed drives (VSDs) based on two VSDs connected to a multiphase machine are an attractive solution to replace high-power mechanic and hydraulic systems in many sectors of industry and transportation because they present high performance with reduced cost, volume and weight. Among the causes which affect the reliability of dual VSDs, the common-mode current flowing through the machine bearing is an important issue. This paper faces the mitigation of the common-mode current by reducing the common-mode voltage (CMV) generated by the operation of a dual VSD. The CMV reduction is carried out without introducing any extra device and/or passive filtering method. This CMV reduction is performed by applying a specific phase-displacement between the modulation strategies of each single inverter drive. The proposed technique has been evaluated in a down scaled experimental setup in order to test its effectiveness.

A Carrier-Based Discontinuous PWM Strategy for T-Type Three-Level Inverter with Reduced Common Mode Voltage and Neutral Point Voltage Control

A novel carrier-based discontinuous pulsewidth modulation (CB_DPWM) strategy for T-type three-level converter is proposed in this article. Because one significant advantage of the proposed CB_DPWM is the reduction of common mode voltage (CMV), it is named as RCMV_CB_DPWM hereafter. It also can reduce switching loss and remove dc offset from the neutral point voltage (NPV) simultaneously. RCMV_CB_DPWM has two design freedoms, one is modulation wave and the other is carrier wave. By injecting zero sequence voltage properly, the corresponding clamping mode can be acquired. Moreover, reduced CMV can be achieved by arranging carrier wave flexibly. The integrity of RCMV_CB_DPWM is analyzed as well as its NPV self-equilibrium ability, and an active NPV control method is then introduced. Moreover, its realization is discussed briefly. Finally, the experiments are carried out to verify the effectiveness of the proposed method.

A Comprehensive Review on Space Vector Modulation Techniques for Neutral Point Clamped Multi-Level Inverters

The Neutral Point Clamped (NPC) Multi-Level Inverters (MLI) have been ruling the power electronics industries for the past two decades. The Multi-Carrier Pulse Width Modulation (MCPWM) is common PWM techniques which are widely used in NPC-MLI applications. However, MCPWM is not having a good impact on the balancing of DC-link voltages, Common Mode Voltage (CMV) and limiting the Total Harmonics Distortion (THD). The Selective Harmonic Elimination (SHE) technique is introduced for reducing the THD, however all the switching angles should be maintained less than π/2 to keep the eliminated harmonics at constant level which narrows down the modulation index range. Hence, in recent days Space Vector Modulation (SVM) technique is widely used in NPC-MLI, which gives better DC-link voltage balancing, self-neutral point balancing, near-zero CMV reduction, better-quality harmonics profile and switching loss minimization. Hence, it is a preferred solution for the majority of electrical conversion applications such as electric traction, high power industrial drives, renewable power generation, and grid-connected inverters, etc. The paper gives a comprehensive review of the SVM for NPC-MLI. First, this paper deliberates the state of art for two-level SVM and extends it to three-level (3L) SVM. Also compares the 3L SVM performance with other MCPWM techniques. Followed by the various modified MLI SVM techniques in terms of their implementations, DC-link capacitor balancing, and reduction of CMV. Further, the review of MLI SVM is widened to open-end winding Inverters and multiphase MLIs. The final part of this paper discussed the future trends and research directions on MLI SVM techniques and its applications.

A four-state CBPWM technique for common-mode voltage reduction in two-level inverter

Common-mode voltage (CMV) leads to a large number of failures in power electronics systems, for example, in two level voltage source inverter (2L VSI)-based circuits. This paper presents a four-state (4S) carrier-based pulse-width modulation (CBPWM) technique which yields the reduced CMV (RCMV) for a 2L VSI. The proposed algorithm is called as 4S RCMV CBPWM. The principle of 4S RCMV CBPWM technique is based on the four-state space vector modulation (4S SVM), which removes the zero vectors in the switching sequence and utilizes the active vectors so that the magnitude of CMV is limited to one-sixth of DC source voltage. In addition, the proposed technique also considers the target of minimizing average CMV values on the whole operation area of the space vector diagram. To implement the proposed algorithm, the CMV function is firstly analyzed so that the requirements for minimized average CMV values are achieved. Control voltages for 2L VSI is deduced from the reference voltages and offset function, thus the required average CMV is achieved. Carrier implementation for proposed algorithm is also analyzed. The theory study is verified by simulation and experiment models the quality of proposed method is evaluated in terms of harmonics distortion factors.

Capacitor Lifetime Extension in a Hybrid Active Neutral-Point-Clamped Inverter With Reduction of DC-Link Ripple Current and Common-Mode Voltage

This paper proposes a reduction method for DC-link ripple current and common-mode voltage (CMV) in a hybrid active neutral-point-clamped (ANPC) inverter. A Si and SiC hybrid ANPC inverter has been developed recently to overcome the extremely high cost of a full-SiC ANPC inverter. A hybrid ANPC requires much fewer SiC MOSFETs than a full-SiC ANPC inverter while providing a comparable power density. Voltage source inverters such as hybrid ANPC inverters utilize electrolytic capacitors, which have a large capacitance per volume, as a DC link. However, an electrolytic capacitor is one of the most vulnerable components in a power electronic converter due to its small allowable ripple current. A large ripple current flowing into the electrolytic capacitor generates a heat loss, which shortens the lifetime of the capacitor. Furthermore, the common-mode voltage (CMV) causes an undesirable leakage current and electromagnetic interference. The CMV depends on the pulse-width modulation of the voltage source inverters. The proposed method enhances the reliability of the hybrid ANPC inverter by reducing the DC-link ripple current and CMV simultaneously. The effectiveness and validity of the proposed method are verified through simulations and experimental results.

Common-Mode Voltage Reduction Method for Three-Level Inverter With Unbalanced Neutral-Point Voltage Conditions

The three-level inverter has been widely researched and adopted in industry. This article further proposes a carrier-based modulation method to reduce the common-mode voltage (CMV) and obtain high-quality output currents for three-level inverter with unbalanced neutral-point voltage conditions. In this method, the zero-sequence voltage is calculated by three-phase modulation waves, three-phase output currents, and voltages across the dc-link capacitors. The limitations of the zero-sequence component are carefully considered in order not to generate the basic voltage vector with high CMV magnitudes. In addition, a deadbeat control scheme for controlling the dc-link voltages asymmetrically with the proposed pulsewidth modulation method is presented, and asymmetrical control of dc-link voltages can be realized with fast response. Compared with the conventional space vector modulation (SVM) and the virtual SVM methods, the proposed scheme can reduce the CMV by half. Simulated and experimental results validate the effectiveness of the proposed method.