Abstract
This paper proposes a reduction method for DC-link ripple current and common-mode voltage (CMV) in a hybrid active neutral-point-clamped (ANPC) inverter. A Si and SiC hybrid ANPC inverter has been developed recently to overcome the extremely high cost of a full-SiC ANPC inverter. A hybrid ANPC requires much fewer SiC MOSFETs than a full-SiC ANPC inverter while providing a comparable power density. Voltage source inverters such as hybrid ANPC inverters utilize electrolytic capacitors, which have a large capacitance per volume, as a DC link. However, an electrolytic capacitor is one of the most vulnerable components in a power electronic converter due to its small allowable ripple current. A large ripple current flowing into the electrolytic capacitor generates a heat loss, which shortens the lifetime of the capacitor. Furthermore, the common-mode voltage (CMV) causes an undesirable leakage current and electromagnetic interference. The CMV depends on the pulse-width modulation of the voltage source inverters. The proposed method enhances the reliability of the hybrid ANPC inverter by reducing the DC-link ripple current and CMV simultaneously. The effectiveness and validity of the proposed method are verified through simulations and experimental results.
Highlights
Multilevel inverters are suitable for high-power and medium-voltage renewable energy generation systems because of their small filter size, gradual dv/dt, and outstanding harmonic characteristics [1]-[3]
This paper presents a switching strategy to suppress the DC-link ripple current and common-mode voltage (CMV) in a hybrid active NPC (ANPC)
The neutral point current IN is reduced from 5.82 ARMS to 2.34 ARMS, which represents a reduction of 58%
Summary
Multilevel inverters are suitable for high-power and medium-voltage renewable energy generation systems because of their small filter size, gradual dv/dt, and outstanding harmonic characteristics [1]-[3]. In [24] and [25], a double modulation wave CBPWM strategy and virtual SVPWM was proposed to reduce CMV for three-level inverter These strategies reduce NP AC voltage ripple and CMV effectively, the number of switching of power semiconductors increases when performing pulse width modulation (PWM). In [27], a common-mode voltage reduction pulsewidth modulation (CMV-R PWM) is proposed This method reduces CMV by using a different voltage vector instead of the existing small vector, and applies a separate controller to control the DC-link capacitor voltage stable. All of these methods do not consider the effect of the DC-link ripple current according to the change in the PWM method. The [N]- and [O–]-states are generated by the switching of the SiC MOSFET
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