Common-mode Voltage Reduction Research Articles

A reduced vector model predictive controller for a three-level neutral point clamped inverter with common-mode voltage suppression

This paper presents a novel, state-of-the-art predictive control architecture that addresses the computational complexity and limitations of conventional predictive control methodologies while enhancing the performance efficacy of predictive control techniques applied to three-level voltage source converters (NPC inverters). This framework's main goal is to decrease the number of filtered voltage lifespan vectors in each sector, which will increase the overall efficiency of the control system and allow for common mode voltage reduction in three-level voltage source converters. Two particular tactics are described in order to accomplish this. First, a statistical approach is presented for the proactive detection of potential voltage vectors, with an emphasis on selecting and including the vectors that are most frequently used. This method lowers the computational load by limiting the search space needed to find the best voltage vectors. Then, using statistical analysis, a plan is presented to split the sectors into two separate parts, so greatly limiting the number of voltage vectors. The goal of this improved predictive control methodology is to reduce computing demands and mitigate common mode voltage. The suggested strategy's resilience is confirmed in a range of operational scenarios using simulations and empirical evaluation. The findings indicate a pronounced enhancement in computational efficiency and a notable diminution in common mode voltage, thereby underscoring the efficacy of the proposed methodology. This increases their ability to incorporate renewable energy sources into the electrical grid.

Common-Mode Voltage Reduction Method-Based Flexible Power Control for Multiport DC–AC Converter in PV–Battery Hybrid System

Common-Mode Voltage Reduction Method-Based Flexible Power Control for Multiport DC–AC Converter in PV–Battery Hybrid System

Mitigation of common mode voltage in ultra sparse matrix converters using auxiliary shoot‐through switches for wind energy systems

SummaryThis paper targets to minimize the peak common mode voltage (CMV) in ultra sparse matrix converters (USMC) by applying new zero vectors for the space vector modulation technique (SVM). Conventional zero vectors in the SVM raise the peak CMV by 42.23%. An increased magnitude of CMV is associated with the occurrence of leakage current, hence resulting in insulation degradation. So, the reduction of peak CMV is necessary for USMC. The proposed method offers suitable switching arrangements using auxiliary shoot through (AST) switches to minimize the peak‐to‐peak CMV. This proposed method holds the advantages of the conventional method, like a wide range of modulation index and zero current switching at the rectifier side, and also reduces the CMV problem. This paper also provides a comparative analysis of the existing reported methods and the proposed method. The effectiveness of the proposed method is validated through both simulation and experimental results.

Multi-objective based Hybrid Artificial Intelligence Controlled Parallel Inverter in Islanded and Grid Connected Operations

Background: The Integration of non-conventional energy systems (NCES), like solar, wind, etc., into the grid with power electronic devices is adapted to meet the demand. Parallel connection of inverters (PCI) is an efficient method to boost power handling capacity, reliability, and system efficiency. However, the main drawback is the unequal power sharing among the inverters while using the conventional droop control technique (CDC). In addition, the circulating currents (CC) flow between these PCI, leading to common mode voltage (CMV), current waveform distortion, and reduction in the system's overall performance. Objectives: This work consists of a photovoltaic system (PVS) and battery energy storage system (BES) as the distributed generation (DG) unit to voltage source inverter (VSI) 1 and 2. The multi- objectives of the suggested work are (a) the equal power/load sharing among two inverters, (b) effective minimization of CC and the CMV, (c) maintaining constant DC-link (DCL) voltage during different solar irradiation and constant temperature, and (d) the reduction in total harmonic distortion (THD) of load current. Methods: A novel approach related to the enhanced droop control (EDC) method with an adaptive neuro-fuzzy hybrid controller (ANFHC) was suggested here to overcome the above issues. The performance analysis of the suggested technique was done in the Matlab/ Simulink platform with islanded and grid-connected modes for different loads. Results: A comparative analysis with the available methods like the proportional integral controller (PIC) and sliding mode controller (SMC) was carried out to exhibit the viability of the developed control technique. Conclusion: This study focused on the operation and control of a PCI with ANFHC in islanded and grid-connected modes to address issues such as uniform power sharing and reduction of CC and CMV.

Improved virtual space vector modulation for neutral point voltage oscillation and common-mode voltage reduction in neutral point clamped three-level inverter

Improved virtual space vector modulation for neutral point voltage oscillation and common-mode voltage reduction in neutral point clamped three-level inverter

Quasi-Z-Source Three-Phase Voltage Source Inverter with Virtual Space Vector Modulation to Increase the Voltage Gain and for the Reduction of Common Mode Voltage

Abstract A quasi-Z-source network is used to boost the DC bus voltage of a voltage source two-level H-bridge inverter to increase the voltage gain. With the increase in the DC bus voltage, the common mode voltage (CMV) also increases. The CMV is reduced using virtual space vector pulse width modulation (SVPWM). Due to the presence of a quasi-Z-source network, the expression of the CMV changes significantly with respect to the conventional voltage source two-level H-bridge inverter fed from a pure DC supply. In this paper, a detailed analysis of the origin of the CMV for the quasi-Z-source two-level H-bridge inverter is presented. Additionally, it is shown how the CMV is affected for a DC input supply taken from a three-phase diode bridge rectifier. The work also details the scheme for suitable placement of shoot-through time intervals required for boosting within the non-active time intervals in virtual SVPWM. The simulation and experimental results show the scheme is effective in increasing the voltage gain and reducing the CMV arising at the third harmonic of the desired output frequency by at least 33.33%.

Minimization of Common Mode Voltage and Capacitor Voltage Unbalance of 3-Phase 4-Wire 3-Level NPC inverter using 4D-SVM

This paper elucidates the implementation of Four-dimensional Space Vector Modulation (4D-SVM) for reduction of Common Mode Voltage (CMV) and Capacitor Voltage Unbalance (CVU) of 3-phase 4-wire 3-level Neutral Point Clamped inverter (3L-NPCI). CMV and CVU are major drawbacks of neutral point clamped inverter circuit; It leads to affect the performance of inverter in terms of bearing failure, unequal voltage stress across various switching devices, the magnitude of load current increases, increases in total harmonic distortion (THD), tripping of ground fault relays and malfunction of various sensitive electronics and control unit. The 4D-SVM algorithm is developed to reduce the CMV and CVU; with help of the nearest state vector (NSV) control method CMV range is reduced and by proper utilization of large and small vector capacitor voltage unbalance is minimized. 4D-SVM for 3-phase 4-wire 3-level includes 81 switching state vectors with a non-redundant switching concept. This algorithm is implemented without using any trigonometric equations, lookup tables, and angle determinations. This proposed system provides a comprehensive analysis of 4D-SVM for reduction of CMV range and CVU for the 3L-NPCI system. The minimization of CMV and CVU is achieved using MatLab-Simulink and FPGA processor for simulation and experimental results respectively.

Modified SVPWM technique for CMV reduction in asymmetrical dual three phase induction machine drive

Due to its advantages, the asymmetrical dual three-phase induction motor drive is a strong choice in high-power applications. However, the common-mode voltage produced by the voltage source inverters affects the winding insulation and damages the bearings. Common-mode voltage is also responsible for electromagnetic interference and leakage currents. This paper, therefore, analyses the common-mode voltage produced by the inverter supplying a dual three-phase induction motor drive and proposes a novel modified space vector decomposition-based Space Vector Pulse Width Modulation (SVPWM) technique for common mode reduction. The vector space decomposition-based space vector modulation technique offers excellent flexibility as it reduces the common-mode voltage (CMV) by exploiting the additional degree of freedom in a dual three-phase system. The common-mode voltage (CMV) can be reduced to one-sixth of the DC link voltage compared to the highest CMV, i.e. half of the DC-link voltage produced in conventional space vector modulation. The proposed method is also validated experimentally to demonstrate the effectiveness of the proposed scheme in terms of the amplitude of CMV, pulsations, and total harmonic distortion(THD) in current.

Common-Mode Voltage Reduction for Back-to-Back Two-Level Converters Based on Zero-Sequence Voltage Injection

High frequency and high amplitude common-mode voltage (CMV) can induce a number of problems on the reliable operations of back-to-back two-level converters, such as shaft voltages and bearing currents. To restrain the CMV for back-to-back two-level converters, a simple and effective CMV reduction method based on zero-sequence voltage (ZSV) injection is proposed in this article. By injecting the optimal amount of ZSV on either the rectifier-side or the inverter-side, the corresponding pulse overlapping areas that result in high CMV amplitudes can be eliminated with the proposed method, then the amplitude of CMV can be reduced by half, and the pulse edges of CMV can be reduced by one-third. Simulation and experimental results are presented to verify the effectiveness of the proposed method in CMV reduction, while some comparisons are also conducted to demonstrate the superiority of the proposed method.

An Improved Modulation Scheme of Isolated Matrix Converter for Common-Mode Voltage Reduction and DC-Bias Current Mitigation

In this paper, an optimized space vector modulation (SVM) method is proposed for the isolated three-phase matrix-type AC/DC converter, where the four-quadrant operation ability of the bidirectional power switch can be fully used. The primary-side transformer current can be eliminated naturally during zero current vectors without extra switching actions. Therefore, the conduction loss of matrix converter (MC) is reduced and the efficiency can be increased. Moreover, the proposed method can avoid the shoot-through operation in MC, and the common-mode voltage can be mitigated effectively. As the zero current vector is kept with the proposed modulation strategy, the current harmonics will not be increased. Thirdly, both the DC-link inductor current and DC-bias current of high-frequency transformer (HFT) are measured through the secondary-side current of HFT. Therefore, the DC-bias current and the saturation of HFT are avoided by closed-loop control with the proposed modulation strategy. The experiments have been carried on a 1-kW laboratory prototype to verify the validity of the proposed modulation scheme.

Enhancing the Performance and Efficiency of Two-Level Voltage Source Inverters: A Modified Model Predictive Control Approach for Common-Mode Voltage Suppression

In this paper, a new modified model predictive control is proposed to improve the performance of the model predictive control for two-level voltage source inverters by alleviating computational burden and the disadvantages associated with the conventional model predictive control strategy. The objective of the proposed method is to reduce the number of candidate voltage vectors in each sector, thereby improving the overall performance of the control system, as well as achieving common-mode voltage reduction for two-level voltage source inverters. Two strategies are introduced to achieve this objective. Firstly, an algorithm is developed based on statistical computational processes to pre-define the candidate voltage vectors. This strategy involves ranking and considering the most frequently used voltage vectors. Consequently, by reducing the computational burden, the search space for the optimal voltage vectors is reduced. Furthermore, based on statistical results, a strategy is proposed to divide the sectors into three sectors instead of the six sectors in the conventional method. This approach effectively reduces the number of candidate voltage vectors. The modified model predictive control strategy aims to improve the efficiency of the control system by reducing the computational burden, and suppressing the common-mode voltage. The simulation and experiments are carried out to verify the effectiveness of the proposed strategy under various operational conditions. The results demonstrate that the modified model predictive control approach significantly reduces the computational burden and complexity of the control system while effectively suppressing the common-mode voltage; this contributes to improving the performance of two-level voltage source inverters and enhancing their applicability for connecting the renewable energies to the grid.

Improved virtual SVPWM algorithm for CMV reduction and NPV oscillation elimination in Three-Level NPC inverter

An improved virtual space vector pulse-width modulation (IVSVPWM) strategy is presented to address simultaneously the problem of common mode voltage (CMV) with neutral point voltage (NPV) fluctuations in wind power converters. The proposed IVSVPWM method suppresses the amplitude of the common mode voltage to Udc/6 by discarding the positive small vector. Meanwhile, the new virtual vector is synthesized by selecting a vector whose neutral point current sums to zero among the retained voltage vectors. In addition, a feedback mechanism is established in the proposed strategy. According to the feedback result, the distribution coefficients of each basic vector in the virtual vector are recalculated to suppress the NPV fluctuation. Through the above control strategy, the dual effect of suppressing the CMV and balancing the NPV is achieved in the full modulation. The feasibility and effectiveness of the strategy are verified by simulation and experiment.© 2017 Elsevier Inc. All rights reserved.

An Improved Reference Voltage Decomposition Method Based on Three-Level NPC Converters With Neutral-Point Voltage Balancing and Common-Mode Voltage Reduction

In this paper, an improved reference voltage decomposition method (RVDM) that takes account of neutral-point (NP) voltage balancing and common-mode voltage (CMV) reduction for neutral-point-clamped three-level converter (NPC-TLC) is proposed. Based on the analysis of space vector diagram (SVD), CMV is simply reduced by injecting zero-sequence voltages at two-level SVD. Then, according to the principle of adjusting zero-state duty cycles to change the NP current, the switching states of a certain phase or two phases are adjusted from two to three. Therefore, two improved methods that take the balancing control of NP voltage and the reduction of CMV into account are introduced and named method I and method II respectively. Both two proposed improved methods are simple in principle and easy to implement. Considering reliability and output performance, method II is selected as the improved strategy. Finally, the superiority of the improved strategy is verified by experiments, and experimental results are consistent with the theoretical analysis.

A Novel Modulation Scheme for Simultaneous Common-Mode Voltage Reduction and Neutral-Point Voltage Balance in the Reduced Switch Count Quasi-Z-Source Three-Level Inverter

The reduced switch count quasi-Z-source three-level inverter (RSC-QZS-TLI) not only maintains the advantages of continuous input current in the conventional quasi-Z-source three-level inverter (C-QZS-TLI), but also reduces the number of power switches and system cost. However, it inevitably faces the challenges of high common-mode voltage (CMV) and neutral-point voltage (NPV) imbalance, which threaten system safety and reliability. Moreover, due to the inherent features of this topology, the medium vectors cannot be generated, which means that the traditional modulation method is not applicable any more. To address the above challenges, a novel modulation method is proposed. The pre-selected basic vectors are optimized primarily, which restrict the CMV magnitude within one-sixth of dc-link voltage. Then, for the particularity of RSC-QZS-TLI, the distribution factor of small vector and its limitation range are introduced for the first time, and an indirect calculating approach is developed to obtain the duty cycles of the pre-selected four vectors, which maintains the correct ac output voltage and dc voltage boosting ability. Meanwhile, according to sector number and output of NPV controller, the distribution factor is modified to control the NPV balance. Compared with the traditional modulation method, the CMV magnitude of the proposed method is reduced by 50 %, and the balanced NPV is controlled actively. Simulated and experimental results verify the feasibility of the proposed scheme.

Three-Stage Duty Cycle-Based Deadbeat Predictive Torque Control for Three-Phase SPMSMs With CMV Reduction

Model Predictive Torque Control (MPTC) is highly regarded for its simple structure, rapid dynamic response, and optimized control performance when applied to actual motor driving systems. However, conventional MPTC techniques often lead to undesirable effects in three-phase inverter-based surface-mounted permanent magnet synchronous motors (SPMSMs), such as high electromagnetic torque, stator flux ripples, and significant current harmonic distortion. Notably, the generalized MPTC approach generates a substantial common mode voltage (CMV) that can cause damage to the motor bearing and winding insulation in SPMSMs. To address these issues, this paper proposes a three-stage duty cycle-based deadbeat predictive torque control (DCDPTC) technique for SPMSMs. The proposed technique leverages the volt-second equilibrium theorem by aligning the duty cycles with the predicted electromagnetic torque, stator flux, and their respective target values while accounting for extreme cases, accordingly electromagnetic torque and stator flux ripples as well as the total harmonic distortion (THD) of the stator current are minimized. In order to improve the system robustness, the duty cycle is limited to avoid the overmodulation. Furthermore, optimized switching sequences are meticulously arranged to ensure the CMV is lowered and the minimum number of switching transitions is maintained while utilizing a fixed switching frequency. The proposed technique is simplified. Its resultant performance is validated by experimental results.

Common-Mode Voltage Reduction for MMC With Consideration of Dead Zone and Switching Delay

Common-Mode Voltage Reduction for MMC With Consideration of Dead Zone and Switching Delay

A Robust Control for Five-level Inverter Based on Integral Sliding Mode Control

The limitations of classical carrier wave-based pulse width modulation (PWM) techniques prevent themfromensuringgoodoutputqualityformulti-levelinverters.Thispaperproposesanewslidingmodecontrol(NSMC)method for controlling cascaded H-bridge multi-level inverters (CHB-MLIs) to improve the output quality of theinverter, reduce the common-mode (CM) voltage with high-order harmonics, and achieve stable and robustnesscontrolfortheCHB-MLIs.TheNSMCmethodmodulatesthePWMpulsesforthemulti-levelinverterbycomparingthecontrolsignalu(t)andthecomparatorlevelswithoutusingcarrierwavetechniques.Thisapproachfacilitatestheformation of a control signal u(t) which can be flexibly adjusted to optimize the generation of PWM pulses. Toreducethechatteringproblemaroundthesliding-modesurfaceathighfrequenciesandtoincreasespeedconvergence, the integral sliding-mode surface integrated with a continuous control law is used to design thecontroller. Additionally, a first-order low-pass filter (LPF) with a variable cut-off frequency is added to the controllawtoimprovestabilityandreduceoscillationcausedbyrapidandlargechangesintheloadcurrentamplitude.ThestabilityofthecontrolsystemisvalidatedbytheLyapunovtheory.Simulationandexperimentaltestswereperformedon the same cascaded H-bridge five-level inverter (CHB-5LI) with an R-L load. The results show that the proposedNSMC method is robust and performs better efficiently for multi-level inverter control systems. Furthermore, theoutput quality of the inverter is significantly improved compared to classical carrier wave-based PWM techniques,with a reduced CM voltage and fewer high-order harmonics, resulting in reduced losses and switching frequency. Therefore, the stability and strong robustness of the CHB-MLIs can b eachieved by the proposed NSMC method.

A Megawatt-Scale Si/SiC Hybrid Multilevel Inverter for Electric Aircraft Propulsion Applications

This paper presents the design and development of a megawatt-scale medium-voltage (MV) hybrid inverter prototype to validate its feasibility and potentials for the electric propulsion on the next-generation electric aircraft system with an onboard MV dc distribution, e.g., 3 kV dc bus in this work. The proposed hybrid converter consists of a three-level active-neutral-point-clamped (ANPC) stage using 3.3 kV silicon IGBTs cascaded with an H-bridge stage using cost-effective 1.2 kV SiC MOSFETs in each phase. Comprehensive design and evaluation of the full-scale prototype are elaborated, including the low-inductance busbar design, converter architecture optimization and system integration. In addition, a low computational cost space vector modulation with common-mode voltage (CMV) reduction feature is proposed to fully exploit the benefits of SiC MOSFET in this hybrid topology. Extensive simulation and experimental results are provided to demonstrate the performance of each power stage and the full converter assembly in both the steady-state operation and variable frequency operations. Compared with the widely adopted IGBT based ANPC converter in MV applications, the proposed 7-L hybrid inverter system features higher power efficiency, reduced harmonics, higher dc voltage utilization, reduced CMV and lower dv/dt, while remains cost effective compared to the solution using MV SiC MOSFETs.

Reduction of common mode voltage for grid-connected multilevel inverters using fuzzy logic controller

Cascaded multilevel three-phase inverters are increasing in industries of electric drives and renewable energy because of their large capacity and suffering from high voltage shock. However, the high magnitude of common mode voltage is one of the drawbacks. Thus, the techniques of modulation and control in these multilevel inverters significantly affect the power quality of the output voltage of inverters. This paper presents a technique using fuzzy logic technique for grid-connected cascaded multilevel 3-phase inverters. This technique has completely removed the current controllers and the conventional modulation using carriers. It also helps reduce the magnitude of common mode voltage and increase the dynamic response. Moreover, the ability to reduce harmonics and switching count also helps decrease the switching loss of inverter. The simulation results on a grid-connected cascaded 5-level 3-phase inverter have validated the effectiveness of the presented technique compared with that of the conventional method using phase opposition disposition (POD) and PI current controllers.

A multi‐criteria methodology with algebraic validation for the design of space vector switching sequences over a fundamental period horizon

AbstractThis paper presents a novel methodology for the design of the Space Vector (SV) switching sequences in order to reduce the output voltage distortion and the common‐mode voltage (CMV) without increasing the number of commutations in comparison to conventional and optimised techniques presented in the literature. Three spaces can be distinguished in a converter, referring to: line‐to‐line voltages, phase voltages and switching states. Consequently, three correspondent sequences of vectors in each space can be verified. The output voltage distortion, CMV and switching count are mainly affected, respectively, by the sequences in the line‐to‐line voltage, phase voltage and switching state spaces. However, the three spaces are interdependent, and the selection of a sequence in one space affects the ones in the other spaces. As a consequence, this paper presents a novel SV approach, where the line‐to‐line voltage sequences are selected over a fundamental period horizon considering the impact in the phase voltages through an algebraic analysis, assuring minimal phase voltage transitions while using VIKOR method to choose the best trade‐off between reduction of output voltage distortion and CMV. In order to validate the proposed strategy, experimental results are given to a three‐phase five‐level Packed U‐Cell (PUC5) converter.