Commodity PC Research Articles

An Analysis of the Cost Effectiveness of an Adaptable Computing Cluster

With a focus on commodity PC systems, Beowulf clusters traditionally lack the cutting edge network architectures, memory subsystems, and processor technologies found in their more expensive supercomputer counterparts. What Beowulf clusters lack in technology, they more than make up for with their significant cost advantage over traditional supercomputers. This paper presents the cost implications of an architectural extension that adds reconfigurable computing to the network interface of Beowulf clusters. This extension is called an intelligent network interface card (INIC). A quantitative description of cost-effectiveness is formulated to compare alternatives. Cost-effectiveness is considered in the context of three applications: the 2D Fast Fourier Transform (2D-FFT), integer sorting, and PNN image classification. It is shown that, for these three representative applications, there is a range of basic hardware costs and cluster sizes for which the INIC is more efficient than a purely serial solution or an ordinary cluster. Furthermore, the cost model has proven useful for designing the next generation INIC.

Uniformization and hypergraph partitioning for the distributed computation of response time densities in very large Markov models

Fast response times and the satisfaction of response time quantile targets are important performance criteria for almost all transaction processing and computer-communication systems. We present a distributed uniformization-based technique for obtaining response time densities from very large unstructured Markov models. Our method utilizes hypergraph partitioning to minimize inter-processor communication while maintaining a good load balance. The resulting algorithm scales well on a distributed-memory parallel computer and, unusually for a problem of this nature, also produces near-linear speed-ups on a network of commodity PCs linked by 100 Mbps ethernet. We demonstrate our approach by calculating passage time densities in a 1.6 million state Markov chain derived from a Generalized Stochastic Petri net model and a 10.8 million state Markov chain derived from a closed tree-like queueing network. We compare the accuracy of our results with simulation and known analytical solutions and contrast the run-time performance of our technique with an approach based on numerical Laplace transform inversion.

Real-time results without real-time systems

The data acquisition system at the National Superconducting Cyclotron Laboratory (NSCL), Michigan State University, East Lansing, is based on commodity PC components running an unmodified Linux kernel. A commercial PCI-VME bus bridge connects the readout processors of this system to digitization hardware. While Linux is not a real-time system, this paper shows how we have structured the readout software to meet the requirements of the NSCL without the use of real-time or embedded components.

Efficient example-based painting and synthesis of 2D directional texture

We present a new method for converting a photo or image to a synthesized painting following the painting style of an example painting. Treating painting styles of brush strokes as sample textures, we reduce the problem of learning an example painting to a texture synthesis problem. The proposed method uses a hierarchical patch-based approach to the synthesis of directional textures. The key features of our method are: 1) Painting styles are represented as one or more blocks of sample textures selected by the user from the example painting; 2) image segmentation and brush stroke directions defined by the medial axis are used to better represent and communicate shapes and objects present in the synthesized painting; 3) image masks and a hierarchy of texture patches are used to efficiently synthesize high-quality directional textures. The synthesis process is further accelerated through texture direction quantization and the use of Gaussian pyramids. Our method has the following advantages: First, the synthesized stroke textures can follow a direction field determined by the shapes of regions to be painted. Second, the method is very efficient; the generation time of a synthesized painting ranges from a few seconds to about one minute, rather than hours, as required by other existing methods, on a commodity PC. Furthermore, the technique presented here provides a new and efficient solution to the problem of synthesizing a 2D directional texture. We use a number of test examples to demonstrate the efficiency of the proposed method and the high quality of results produced by the method.

Evaluation of the Raw Microprocessor

This paper evaluates the Raw microprocessor. Raw addresses thechallenge of building a general-purpose architecture that performswell on a larger class of stream and embedded computing applicationsthan existing microprocessors, while still running existingILP-based sequential programs with reasonable performance in theface of increasing wire delays. Raw approaches this challenge byimplementing plenty of on-chip resources - including logic, wires,and pins - in a tiled arrangement, and exposing them through a newISA, so that the software can take advantage of these resources forparallel applications. Raw supports both ILP and streams by routingoperands between architecturally-exposed functional units overa point-to-point scalar operand network. This network offers lowlatency for scalar data transport. Raw manages the effect of wiredelays by exposing the interconnect and using software to orchestrateboth scalar and stream data transport.We have implemented a prototype Raw microprocessor in IBM's180 nm, 6-layer copper, CMOS 7SF standard-cell ASIC process. Wehave also implemented ILP and stream compilers. Our evaluationattempts to determine the extent to which Raw succeeds in meetingits goal of serving as a more versatile, general-purpose processor.Central to achieving this goal is Raw's ability to exploit all formsof parallelism, including ILP, DLP, TLP, and Stream parallelism.Specifically, we evaluate the performance of Raw on a diverse setof codes including traditional sequential programs, streaming applications,server workloads and bit-level embedded computation.Our experimental methodology makes use of a cycle-accurate simulatorvalidated against our real hardware. Compared to a 180 nmPentium-III, using commodity PC memory system components, Rawperforms within a factor of 2x for sequential applications with a verylow degree of ILP, about 2x to 9x better for higher levels of ILP, and10x-100x better when highly parallel applications are coded in astream language or optimized by hand. The paper also proposes anew versatility metric and uses it to discuss the generality of Raw.

Enabling Gigabit Network Access to End Users

To achieve innovative network architectures capable of delivering high-speed data transfers to end users, considerable efforts have been invested in minimizing or eliminating the bottlenecks that exist in high-speed network environments. These bottlenecks exist primarily at two levels, namely, network data transmission to the end system and data delivery within the end system to the user. For wired networks, improvements in fiber optic technologies have shifted the bottleneck from the underlying physical network to the end system. However, wireless networks still face obstacles at both levels to achieving high, end-to-end performance data delivery, particularly at gigabit per second rates. We first present current wireless communication technologies aimed at delivering gigabit per second transmission rates to end systems. We then investigate the bottleneck at the end system by exploring experimentally the performance benefits of a network interface architecture designed to enable high-performance, low-latency applications using minimal host resources. We compare the performance of our network interface architecture with the traditional one, using commodity PCs connected by gigabit per second local area networks running protocols such as TCP/IP and UDP/IP. We argue that such a network interface architecture can eliminate the bottlenecks prevalent in current end systems and, consequently, enables users to reap the full benefits of the high-speed networks available today.

Integrating IS Curriculum Knowledge through a Cluster-Computing Project: A Successful Experiment

Introduction Business students majoring in areas such as MIS, IS, and IT in business colleges are arriving at college with ever-increasing technical proficiencies. Many businesses, as a result of changing needs, have begun to appreciate the value in employees who have a combination of business and technological skills. Businesses finally realize that hiring individuals, who possess strong technology skills and come from business programs, is not only desirable but reduce their up front training costs. Value-added is a popular term in businesses. How do the MIS courses add value to the ability and knowledge of the MIS graduates? Many programs are devoted to explaining the concepts of building networks and managing IT infrastructures through case analysis. Broad-based lecture-oriented case-supported education cannot prepare students to handle the tasks and responsibilities that they will be expected to take-on (Wrege, 1982). Of course, it prepares students to understand and simulate various business situations in which they may have to work (Korwin & Jones, 1990). However, organizations demand that MIS graduates coming out of business schools not only have the ability to understand and analyze different business situations, but also are proficient in handling and managing technology tools and environments. Organizations spend millions of dollars to train the MIS graduates and to customize to their role and responsibilities. Practitioners frequently claim that MIS curriculums do not prepare students to handle the roles and responsibilities that graduates have to take-on in organizations. As a result, companies have to bear the high cost of training them. Graduates entering the job market today will find employers seeking recruits well versed in theory, but also with networking experiences in a hands-on environment. Many institutions are trying to adjust their course offerings to address this situation (Harvey, Sirna, & Houlihan, 1998; Lane, 1981). From an educational perspective, teaching cluster computing is an ideal way to expose students to theoretical concepts as a foundation to the learning experience, and then providing them with the opportunity to apply what they have learned in a hands-on environment (Boud, 1995; Scanlon, Tounglu, & Jones, 1998). Often, MIS courses are taught from a theoretical point of view with little emphasis on actually using equipment. The use of cluster computing in business requires administrators and analysts with knowledge, skills, and experience in networking to effectively build and operate a system. As cluster computing migrates to an increasing number of business applications, personnel with a unique knowledge of both the technical aspects of cluster computing and the business acumen will become necessary. Thus, there is an increasing need to teach cluster computing in colleges of business (Hyde, 2000). The information curriculum being taught in colleges of business--by whatever name, MIS, IS, IT, etc.--should take a close look at cluster-computers. Such a course could help to provide cluster-administrators to the corporate world, and prepare future employees for the tasks ahead of them (Rice, Wilson, & Bagley, 2001). Cluster Computing Cluster computers are increasingly important elements in mainstream computing. In recent years, cluster computers have emerged as the leaders in high-performance computing (Sterling, 2000). Today's cluster-computers are more than a match for mainframes in terms of both cost and performance (Baker, Fox, & Yau, 1996). Cluster computing harnesses the combined computing power of multiple microprocessors in a parallel configuration. Cluster computers are a set of commodity PC's dedicated to a network designed to capture their cumulative processing power for running parallel-processing applications. Clustered computers are specifically designed to take large programs and sets of data and subdivide them into component parts, thereby allowing the individual nodes of the cluster to process their own individual chunks of the program (Baker, Apon, Buyya, & Jin, 2002; Baker & Buyya, 1999). …

Microbenchmark performance comparison of high-speed cluster interconnects

Today's distributed and high-performance applications require high computational power and high communication performance. Recently, the computational power of commodity PCs has doubled about every 18 months. At the same time, network interconnects that provide very low latency and very high bandwidth are also emerging. This is a promising trend in building high-performance computing environments by clustering - combining the computational power of commodity PCs with the communication performance of high-speed network interconnects. There are several network interconnects that provide low latency and high bandwidth. Traditionally, researchers have used simple microbenchmarks, such as latency and bandwidth tests, to characterize a network interconnects communication performance. Later, they proposed more sophisticated models such as LogP. However, these tests and models focus on general parallel computing systems and do not address many features present in these emerging commercial interconnects. Another way to evaluate different network interconnects is to use real-world applications. However, real applications usually run on top of a middleware layer such as the message passing interface (MPI). Our results show that to gain more insight into the performance characteristics of these interconnects, it is important to go beyond simple tests such as those for latency and bandwidth. In future, we plan to expand our microbenchmark suite to include more tests and more interconnects.

A fully digital real-time power system simulator based on PC-cluster

Many benefits come with the real-time simulation of electric machinery and drives. HYPERSIM, a fully digital real-time power system simulator, originally based on large parallel supercomputer, is now adapted to a new hardware platform, in order to increase its flexibility and accessibility. This paper presents a new hardware architecture, called PC-cluster, for real-time simulation of complex power system networks, including power electronics. A PC-cluster consists of several commodity PC interconnected with high-speed network. This new hardware platform for the HYPERSIM simulator is completely based on components-off-the-shelf (COTS), such as commercial motherboard, PCI input/output (I/O) board and communication board. The general implementation of the real-time parallel simulator is introduced in this paper. All aspects of the simulation, such as communication, calculation, synchronization, I/O access and acquisition, are presented in detail. To evaluate the performance of the new hardware platform in a real simulation, a complete application of electric machine drive is presented. This new hardware technology is bringing interesting benefits to power system engineers. It is now easier to have access to powerful simulation tools, in order to perform precise and complete power system studies.

Scalable visualization using a network-attached video framebuffer

We present a scalable, commodity-based, parallel rendering system for interactive visualization of large polygonal and volumetric data models. Our system utilizes commodity PCs that have multiple CPUs and high-capacity I/O buses, a fast AGP bus, and a commodity interconnect. Rendering occurs in parallel using the Chromium framework with the resulting images displayed over the network on a remote display. A key component of our system is the Scalable Graphics Engine, a network-attached video framebuffer capable of gathering pixels from up to 16 sources and driving multiple displays. Our experimental results show that recent developments in commodity computers favor parallel architectures designed to use framebuffer readback and pixel transfer over commodity networks versus specialized hardware for acquiring and aggregating pixel data.

Solving difficult instances of boolean satisfiability in the presence of symmetry

Research in algorithms for Boolean satisfiability (SAT) and their implementations (Goldberg and Novikov, 2002), (Moskewicz et al., 2001), (Silva and Sakallah, 1999) has recently outpaced benchmarking efforts. Most of the classic DIMACS benchmarks (ftp:dimacs.rutgers.edu/pub/challenge/sat/benchmarks/cnf ) can now be solved in seconds on commodity PCs. More recent benchmarks (Velev and Bryant, 2001) take longer to solve due to their large size, but are still solved in minutes. Yet, relatively small and difficult SAT instances must exist if P /spl ne/ NP. To this end, our paper articulates SAT instances that are unusually difficult for their size, including satisfiable instances derived from very large scale integration (VLSI) routing problems. With an efficient implementation to solve the graph automorphism problem (McKay, 1990), (Soicher, 1993) (Spitznagel, 1994), we show that in structured SAT instances, difficulty may be associated with large numbers of symmetries. We point out that a previously published symmetry extraction mechanism (Crawford et al., 1996) based on a reduction to the graph automorphism problem often produces many spurious symmetries. Our paper contributes two new reductions to graph automorphism, which extract all correct symmetries found previously (Crawford et al., 1996) as well as phase-shift symmetries not found earlier. The correctness of our reductions is rigorously proven, and they are evaluated empirically. We also formulate an improved construction of symmetry-breaking clauses in terms of permutation cycles and propose to use only generators of symmetries in this process. These ideas are implemented in a fully automated flow that first extracts symmetries from a given SAT instance, preprocesses it by adding symmetry-breaking clauses, and then calls a state-of-the-art backtrack SAT solver. Significant speed-ups are shown on many benchmarks versus direct application of the solver. In an attempt to further improve the practicality of our approach, we propose a scheme for fast "opportunistic" symmetry extraction and also show that considerations of symmetry may lead to more efficient reductions to SAT in the VLSI routing domain.

Network processors applied to IPv4/IPv6 transition

We describe a high-speed IPv6-IPv4 gateway on an experimental board containing a pair of Intel IXP network processor chips, an FPGA, and a pair of TCAMs. The device is capable of supporting several hundreds of thousands of concurrent TCP/UDP sessions and sustaining close to the line rate on a GbE link. It provides an order of magnitude improvement in packet throughput over an implementation of the same functionality on a commodity PC. IPv6 is beginning to be adopted by organizations and countries that expect to run critically short of IPv4 addresses. Small-scale trials can rely on dual-stock transition mechanisms, in which both an IPv4 and an IPv6 address are assigned to new hosts, which can therefore talk directly to old and new networks. But full deployment must use network address/port/protocol translation (NAPT-PT), in which new hosts are given only IPv6 addresses and must talk through a gateway in order to speak to old networks. The natural location for these NAPT-PT gateways will gradually shift from very local subnets to the edge of a provider network as IPv6 becomes more widely deployed, increasing the demands on the capacity and availability of such gateways. Network processors have the flexibility custom silicon lacks and the speed generic microprocessors lack, and hence are especially well suited for early implementation of network elements such as this gateway between IPv6 islands and the IPv4 ocean. A major challenge in building a scalable middlebox is redundancy support for stateful failover and load balancing, again putting a premium on programmability.

High level Trigger at CMS with the Tracker

The CMS Collaboration has chosen for the Level 2/3 Trigger a design which uses a farm of commodity PCs. A selection based on the CMS Tracker, not used at Level 1, can be performed on all of the data sent to Level 2/3. The performance is comparable to the performance achieved with offline reconstruction code.

Analysis of a prototype intelligent network interface

AbstractWith a focus on commodity PC systems, Beowulf clusters traditionally lack the cutting edge network architectures, memory subsystems, and processor technologies found in their more expensive supercomputer counterparts. Many users find that what Beowulf clusters lack in technology, they more than make up for with their significant cost advantage. In this paper, an architectural extension that adds reconfigurable computing to the network interface of Beowulf clusters is proposed. The proposed extension, called an intelligent network interface card (or INIC), enhances both the network and processor capabilities of the cluster, which has a significant impact on the performance of a crucial class of applications. Furthermore, for some applications, the proposed extension partially compensates for weaknesses in the PC memory subsystem. A prototype of the proposed architecture was constructed and analyzed. In addition, two applications, the 2D Fast Fourier Transform (2D‐FFT) and integer sorting, which benefit from the resulting architecture, are discussed and analyzed on the proposed architecture. Specifically, results indicate that the 2D‐FFT is performed 15–50% faster when using the prototype INIC rather than the comparable Gigabit Ethernet. Early simulation results also indicate that integer sorting will receive a 21–32% performance boost from the prototype. The significant improvements seen with a relatively limited prototype lead to the conclusion that cluster network interfaces enhanced with reconfigurable computing could significantly improve the Beowulf architecture. Copyright © 2003 John Wiley & Sons, Ltd.

Non-strict execution in parallel and distributed computing

This paper surveys and demonstrates the power of non-strict evaluation in applications executed on distributed architectures. We present the design, implementation, and experimental evaluation of single assignment, incomplete data structures in a distributed memory architecture and Abstract Network Machine (ANM). Incremental Structures (IS), Incremental Structure Software Cache (ISSC), and Dynamic Incremental Structures (DIS) provide nonstrict data access and fully asynchronous operations that make them highly suited for the exploitation of fine-grain parallelism in distributed memory systems. We focus on split-phase memory operations and non-strict information processing under a distributed address space to improve the overall system performance. A novel technique of optimization at the communication level is proposed and described. We use partial evaluation of local and remote memory accesses not only to remove much of the excess overhead of message passing, but also to reduce the number of messages when some information about the input or part of the input is known. We show that split-phase transactions of IS, together with the ability of deferring reads, allow partial evaluation of distributed programs without losing determinacy. Our experimental evaluation indicates that commodity PC clusters with both IS and a caching mechanism, ISSC, are more robust. The system can deliver speedup for both regular and irregular applications. We also show that partial evaluation of memory accesses decreases the traffic in the interconnection network and improves the performance of MPI IS and MPI ISSC applications.

PC Network Cluster를 사용한 대규모 재료 시뮬레이션에 관한 연구

For molecular dynamics requires high-performance computers or supercomputers to handle huge amount of computation, it is not until recent days that the application of molecular dynamics to materials fracture simulations draw some attention from many researchers. With the recent advent of high-performance computers, computation intensive methods become more tractable than ever. However, carrying out materials simulation on high-performance computers costs too much in general. In this study, a PC cluster consisting of multiple commodity PCs is established and computer simulations of materials with cracks are carried out on it via molecular dynamics technique. The effect of the number of nodes, speedup factors, and communication time between nodes are measured to verify the performance of the PC cluster. Upon using the PC cluster, materials fracture simulations with more than 50,000 molecules are carried out successfully.

Terrain simplification simplified: a general framework for view-dependent out-of-core visualization

We describe a general framework for out-of-core rendering and management of massive terrain surfaces. The two key components of this framework are: view-dependent refinement of the terrain mesh and a simple scheme for organizing the terrain data to improve coherence and reduce the number of paging events from external storage to main memory. Similar to several previously proposed methods for view-dependent refinement, we recursively subdivide a triangle mesh defined over regularly gridded data using longest-edge bisection. As part of this single, per-frame refinement pass, we perform triangle stripping, view frustum culling, and smooth blending of geometry using geomorphing. Meanwhile, our refinement framework supports a large class of error metrics, is highly competitive in terms of rendering performance, and is surprisingly simple to implement. Independent of our refinement algorithm, we also describe several data layout techniques for providing coherent access to the terrain data. By reordering the data in a manner that is more consistent with our recursive access pattern, we show that visualization of gigabyte-size data sets can be realized even on low-end, commodity PCs without the need for complicated and explicit data paging techniques. Rather, by virtue of dramatic improvements in multilevel cache coherence, we rely on the built-in paging mechanisms of the operating system to perform this task. The end result is a straightforward, simple-to-implement, pointerless indexing scheme that dramatically improves the data locality and paging performance over conventional matrix-based layouts.

Streaming BDD manipulation

Binary decision diagrams (BDDs) are commonly used for handling Boolean functions because of their excellent efficiency in terms of time and space. However, the conventional BDD manipulation algorithm is strongly based on the hash table technique, so it always encounters the memory overflow problem when handling large-scale BDD data. This paper proposes a new streaming BDD manipulation method that never causes memory overflow or swap out. This method allows us to handle very large-scale BDD stream data beyond the memory limitation. Our method can be characterized as follows: (1) it gives a continuous tradeoff curve between memory usage and stream data length, (2) valid solutions for a partial Boolean space can be obtained if we break the process before finishing, and (3) easily accelerated by pipelined multiprocessing. An experimental result demonstrates that we can succeed in finding a number of solutions to a SAT problem using a commodity PC with a 64 MB memory, where as the conventional BDD manipulator would have required a 100 GB memory. BDD manipulation has been considered as an intensively memory-consuming procedure, but now we can also utilize the hard disk and network resources as well. The method leads to a new approach to BDD manipulation.

1-1 東工大キャンパスグリッドプロジェクト : 次世代ハイエンドコンピューティング基盤へ向けて

Evolving "e-science" requires more and more computing power. Considering power consumption and cooling, it is getting impossible to provide computing resources from a single centralized site, like ordinary "University Computer Center". Global Scientific Information and Computing Center (GSIC) at Tokyo Institute of Technology deployed a new form of the computation infrastructure, called Titech Grid, utillzing Grid technology, commodity PC cluster technology and newly introduced hi-speed network. Here, we give presice description of Titech Grid configuration and operation.

Optimization of magneto-hydrodynamic control of diffuser flows using micro-genetic algorithms and least-squares finite elements

In this paper we consider the problem of multidisciplinary design and optimization (MDO) of a diffuser for a steady, incompressible magnetohydrodynamic (MHD) flow. Given a fixed diffuser shape, the optimizer should find the distribution of the wall magnets that will maximize the static pressure increase from inlet to outlet. This design problem is solved through the use of a genetic algorithm based optimization program coupled with a finite element based MHD simulation program. For MHD simulation, a least-squares finite element method (LSFEM) based program has been developed. The use of LSFEM allows the use of equal order approximation functions for all unknowns and is stable for high Reynolds numbers. Optimization was accomplished using a micro-genetic algorithm (GA) based program. The micro-GA is capable of searching the design space with a population much smaller than that required by classical GA. The optimization was performed on a parallel computer composed of commodity PC components. Results show that an applied magnetic field with the proper strength and distribution can significantly improve the static pressure rise over the case of no magnetic field.