Commercial Processors Research Articles

Computing in Memory With Spin-Transfer Torque Magnetic RAM

In-memory computing is a promising approach to addressing the processor-memory data transfer bottleneck in computing systems. We propose spin-transfer torque compute-in-memory (STT-CiM), a design for in-memory computing with spin-transfer torque magnetic RAM (STT-MRAM). The unique properties of spintronic memory allow multiple wordlines within an array to be simultaneously enabled, opening up the possibility of directly sensing functions of the values stored in multiple rows using a single access. We propose modifications to STT-MRAM peripheral circuits that leverage this principle to perform logic, arithmetic, and complex vector operations. We address the challenge of reliable in-memory computing under process variations by extending error-correction code schemes to detect and correct errors that occur during CiM operations. We also address the question of how STT-CiM should be integrated within a general-purpose computing system. To this end, we propose architectural enhancements to processor instruction sets and on-chip buses that enable STT-CiM to be utilized as a scratchpad memory. Finally, we present data mapping techniques to increase the effectiveness of STT-CiM. We evaluate STT-CiM using a device-to-architecture modeling framework, and integrate cycle-accurate models of STT-CiM with a commercial processor and on-chip bus (Nios II and Avalon from Intel). Our system-level evaluation shows that STT-CiM provides the system-level performance improvements of 3.93 times on average (up to 10.4 times), and concurrently reduces memory system energy by 3.83 times on average (up to 12.4 times).

CSP Hybrid Space Computing

Space is a hazardous environment for electronic systems; therefore, the traditional approach to space computing relies upon radiation-hardened electronics, which are characteristically more expensive, larger, less energy-efficient, and generations behind in performance and functionality of modern commercial processors. Conversely, modern commercial processors, while providing the utmost in performance and energy efficiency, are susceptible to space radiation. The desire for more autonomous missions combined with growing demands for more detailed products from advanced sensors have challenged organizations to stay relevant by “doing more with less” to meet future requirements. To meet this need, researchers at the National Science Foundation Center for High-Performance Reconfigurable Computing have developed a new design concept in hybrid space computing that features fixed and reconfigurable processor architectures merged with an innovative system design that is a combination of three technologies: commercial devices, radiation-hardened components, and fault-tolerant computing. This concept has culminated in the development of several novel research platforms, most significantly the CSPv1 flight computer, which was successfully deployed on the International Space Station. Before flight, this CSPv1 design was analyzed and tested on the ground with reliability models and radiation tests. Recent in-flight data have validated the design and shown that CSPv1 exceeds reliability expectations predicted by models.

Quality of Cucumbers Commercially Fermented in Calcium Chloride Brine without Sodium Salts

Commercial cucumber fermentation produces large volumes of salty wastewater. This study evaluated the quality of fermented cucumbers produced commercially using an alternative calcium chloride (CaCl2) brining process. Fermentation conducted in calcium brines (0.1 M CaCl2, 6 mM potassium sorbate, equilibrated) with a starter culture was compared to standard industrial fermentation. Production variables included commercial processor(n=6), seasonal variation (June–September, 2 years), vessel size (10,000–40,000 L), cucumber size (2.7–5.1 cm diameter), and bulk storage time (55–280 days). Cucumber mesocarp firmness, color, bloater defects, pH, and organic acids were measured. Complete lactic acid fermentation was achieved, resulting in terminal fermentation pH values of 3.23 ± 0.09 and 3.30 ± 0.12 for CaCl2and NaCl processes, respectively. On average, CaCl2brined, fermented cucumbers were 1.8 N less firm, which remained significant in the finished product(P<0.0001). Color differences evidenced by higher hue and lower chroma values(P<0.0269)were consistent with increased photooxidation in CaCl2brined cucumbers. Commercial implementation of CaCl2brines for cucumber fermentation in open tanks variably resulted in texture and color defects that can impact product quality. Additional research is needed to understand the atypical softening observed at the commercial scale and identify process controls for quality improvements.

Adaptive and Resilient Circuits: A Tutorial on Improving Processor Performance, Energy Efficiency, and Yield via Dynamic Variation

Variability in device, circuit, and system parameters is one of the primary challenges in the semiconductor industry. Parameter variations degrade processor performance, energy efficiency, and yield across all market segments, ranging from small embedded cores in systems on chip to large multicore servers. In the design, manufacturing, and testing of commercial processors, there are three major variability classifications: 1) simulation tool uncertainties, 2) static parameter variations, and 3) dynamic parameter variations. Simulation tool uncertainties result from a design tradeoff between the simulation time and accuracy for both static-timing analysis and circuit simulators. In addition, transistor and interconnect model inaccuracies increase simulation tool uncertainties, especially when designing a processor in a new technology.

Privatizing transactions for Lee’s algorithm in commercial hardware transactional memory

Lee’s algorithm solves the path-connection problems that arise in logical drawing, wiring diagramming or optimal route finding. Its parallel version has been widely used as a benchmark to test transactional memory systems. It exhibits transactions of large size and duration that stress these systems exposing their limitations. In fact, Lee’s algorithm has been proved to perform similar to sequential in commercial hardware transactional memory systems due to persistent capacity overflows. In this paper, we propose a novel approach to Lee’s algorithm in the context of commercial hardware transactional memory systems. We show how the majority of the computation of the largest transaction, i.e. grid privatization and path calculation, can be executed out of the boundaries of the transaction, thus reducing the size requirements. We leverage the correctness criteria of lazy subscription fallback locks to ensure a correct execution. This novel approach uses transactional memory extensions from commercial processors from a different point of view, not needing either early release or open-nested transaction features that are not yet implemented in these systems. We propose an application programming interface to facilitate the task of the programmer. Experiments are carried out with the Intel Core and IBM Power8 architectures, showing speedups around 3.5 $$\times $$ over both the standard transactional version of the algorithm and the sequential for certain grid inputs and four threads. We also compare our proposal with a software transactional memory LeeTM approach.

An efficient trade-off between yield and energy for eDRAM caches under process variations

eDRAM cells have been considered as a promising alternative to conventional SRAM cells and already adopted in commercial processors. However, eDRAM cells need to be refreshed periodically, resulting in non-negligible energy and performance overhead. Moreover, under process variations, retention time of eDRAM cells exhibits non-uniform distributions. This phenomenon affects both manufacturing yield and eDRAM refresh burden. In this paper, we first analyze eDRAM module (cache) yield and retention time failure patterns under process variations. Based on our analysis, we disclose most of the failing cache lines have only one faulty cell and propose a cost-efficient technique to save those one-cell failing cache lines. Our technique maintains a one-cell failing line (OFL) buffer which manages the status of the one-cell failing cache lines. By effectively curing one-cell failing lines, our technique significantly improves manufacturing yield by up to 46.1% under the identical refresh intervals. In addition, our technique can be used to loosen refresh intervals with comparable yield. By using the loosened refresh intervals, our technique reduces energy per instruction and improves performance by up to 19.9% and 1.3%, respectively.

Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor

Energy-efficiency optimization occupies an important position in the Internet of Things application. The error-resilience technique has begun to emerge and brought the performance and energy benefits as a new vision for alternative computing, because it eliminates the overconstrained margin in current processor design flow and protects the system from process, supply voltage, temperature, and aging variations through an error-resilient mechanism rather than expensive guardbands. However, as a traditional clock-tree power optimization technique, the clock gating mechanism cannot work in such a system when it faces the timing violation problem. In this paper, we propose an error-resilient integrated clock gate (ERICG) and its automatic integration methodology in error detection and correction (EDAC) system design flow. ERICG can provide the ability of in situ timing EDAC with only four additional transistors compared with a conventional integrated clock gate. The SPICE simulation shows that it is a metastable-hardened cell and can work well in the wide voltage operation (0.5~ 1.1 V) including the near-threshold region. We implement it in a commercial C-SKY CK802 processor based on an SMIC 40-nm technology. The result shows that it improves the energy efficiency by 68% compared with the non-EDAC design and lowers the total power by 28.72% over the conventional EDAC design at 0.6 V.

3D X-ray tech for easy reverse engineering of ICs [News

A team of researchers based in Switzerland is on the way to laying bare much of the secret technology inside commercial processors. They pointed a beam of X-rays at a piece of an Intel processor and were able to reconstruct the chip's warren of transistors and wiring in three dimensions. In the future, the team says, this imaging technique could be extended to create high-resolution, large-scale images of the interiors of chips. The technique is a significant departure from the way the chip industry currently looks inside finished chips to reverse engineer them or check that intellectual property hasn't been misused. Today, reverse engineering outfits progressively remove layers of a processor and take electron microscope images of one small patch of the chip at a time.

Traditional processing, composition, microbial quality and sensory characteristics of Eshabwe (ghee sauce)

Eshabwe is a traditional Ugandan condiment produced from butter or ghee. The traditional formula, proximate composition, microbial quality and sensory characteristics of Eshabwe have previously not been reported. The purpose of this study was to describe the processing and to determine the sensory characteristics, proximate composition and microbial quality of Eshabwe. Ten commercial processors of Eshabwe were interviewed. Samples of Eshabwe obtained from processors were analysed for proximate composition and microbial quality. A lexicon for the sensory attributes of Eshabwe was developed using quantitative descriptive analysis. Eshabwe is prepared by whipping butter or ghee (1 kg) with boiled water (560 ± 0.13 mL), rock salt (37.8 ± 0.13 g) and sodium chloride (5.6 ± 0.09 g). Eshabwe has a shelf life of 3–5 days at room temperature, 3 months under refrigeration and over 6 months under frozen storage. Eshabwe contains 43.10 ± 0.15% dry matter, 1.99 ± 0.13% ash, 0.49 ± 0.02% crude protein, 32.87 ± 0.93% fat and 3.93 ± 0.05 Kcal/g. The total aerobic counts (6.56 ± 0.03 log cfu/mL), yeasts and moulds (2.26 ± 0.02 log cfu/mL) and coliforms (3.16 × 103 MPN/mL) were in excess of microbial specifications. A lexicon of 15 descriptors for the sensory attributes of Eshabwe was developed. Eshabwe processing should be standardised to ensure consistent quality and consumer safety.

Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis

Hardware-based mechanisms for software isolation are becoming increasingly popular, but implementing these mechanisms correctly has proved difficult, undermining the root of security. This work introduces an effective way to formally verify important properties of such hardware security mechanisms. In our approach, hardware is developed using a lightweight security-typed hardware description language (HDL) that performs static information flow analysis. We show the practicality of our approach by implementing and verifying a simplified but realistic multi-core prototype of the ARM TrustZone architecture. To make the security-typed HDL expressive enough to verify a realistic processor, we develop new type system features. Our experiments suggest that information flow analysis is efficient, and programmer effort is modest. We also show that information flow constraints are an effective way to detect hardware vulnerabilities, including several found in commercial processors.

Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis

Hardware-based mechanisms for software isolation are becoming increasingly popular, but implementing these mechanisms correctly has proved difficult, undermining the root of security. This work introduces an effective way to formally verify important properties of such hardware security mechanisms. In our approach, hardware is developed using a lightweight security-typed hardware description language (HDL) that performs static information flow analysis. We show the practicality of our approach by implementing and verifying a simplified but realistic multi-core prototype of the ARM TrustZone architecture. To make the security-typed HDL expressive enough to verify a realistic processor, we develop new type system features. Our experiments suggest that information flow analysis is efficient, and programmer effort is modest. We also show that information flow constraints are an effective way to detect hardware vulnerabilities, including several found in commercial processors.

Household characteristics and market participation competence of smallholder farmers supplying cassava to starch processors in Nigeria

The household head characteristics of smallholder cassava farmers supplying raw materials to the major commercial starch processors in Nigeria were examined alongside their market participation categories. A multi-stage random sampling technique was used to select 96 farmers working in clusters in the eight cassava producing states. Data were analyzed using a combination of descriptive and inferential statistics, including the use of independent sample t-test technique to compare farmer's characteristics for the farmers' market participation categories. Results revealed that majority of the farmers were farming for subsistence with only 19.80% selling up to 50% of their farm produce as against 80.20% who sold less. Average mean values were found to be higher for the high market participants compared with the low participants for the age, farming experiences, education, farm size, gender, marital status, household size, training, season of harvesting and fertilizer use, but lower for use of credit, improved cassava variety, harvesting method, farming time devotion, and road access. Only farm size, gender and harvesting season at p<0.01 level and training at p<0.05 level were found to be statistically significant in distinguishing the high and low market participation categories. Policies and programmes aimed at promoting market participation among cassava farmers in Nigeria should be more impactful if directed at these significant factors.Int. J. Agril. Res. Innov. & Tech. 6 (2): 42-56, December, 2016

Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput

In advanced technology nodes, large timing margins must be added to allow for worse process, voltage, temperature, and aging variations. The error detection and correction (EDAC) technique effectively eliminates these margins by timing speculation, but the high design complexity and large hardware cost make many existing EDAC systems unsuitable for commercial processors. Based on the instruction-level locality of timing errors, a collaborative EDAC approach is proposed to address this issue. The hardware layer adopts simple and low cost EDAC circuits to ensure correct operation when timing error occurs, while a runtime software layer prevents recurring errors of the same instruction by sending timing error alarms to the hardware layer. Cooperation of both layers, accompanied with the proposed profile-guided timing error avoidance algorithm, eliminates more than 95% of errors with small runtime overhead. This significantly improves overall performance and alleviates pressure on the EDAC circuits. Experimental results based on the three-stage commercial CK802 processor in SMIC 40LL process present that the approach has improved the peak performance of the baseline EDAC system (Razor-Lite + half-frequency replay) by 8% and reduced the energy consumption by 25%, with less than 1.4% area overhead.

Time-Temperature Relationships for Sanitizing Meat Processing Equipment

ObjectivesThe current method for in-line sanitation of most meat processing equipment is a brief submersion in hot (> 82°C) water. However, there is no industry or government standard for the time the equipment must remain submerged to be properly sanitized. Previous research has shown this method to be ineffective in killing bacteria on knife surfaces, due to the duration of time the knife was allowed to remain submersed in water. Personal, in-facility observations by the authors, of workers submersing equipment for variable lengths of time led to the hypothesis that differences in equipment mass may warrant differences in dwell time during submersion. Thus, the objective of this research was to develop time-temperature curves for typical red meat slaughter equipment. Materials and MethodsEquipment tested is common to commercial animal harvest facilities and included a shroud pin (16.0g), boning hook (66.9g), lymph node hook (94.1g), lamb skinning knife (99.2g), boning knife (106.2g), beef skinning knife (112.0g), honing steel (249.6g), cleaver (377.0g), weasand rod (490 g), beef trolley hook (525 g), pork gambrel (1,100 g), and pneumatic de-hider (1,345 g) ranged widely in mass. One thermocouple was attached to the surface of each piece of equipment and another was submerged in the water bath. A thermocouple data acquisition module recorded temperature change of the equipment and the water bath each 15 ms during submersion. Time-temperature change data was collected for each piece of equipment submerged in 81, 87, and 95°C water. Logarithmic curves were fitted to each piece of equipment at each sanitation temperature. ResultsGeometric mean (± SEM) dwell times for all equipment to reach 71°C were 9.668 (± 4.603), 5.841 (± 2.545), and 1.614 (± 1.078) seconds in 81, 87, and 95°C water. These results suggest that while the current method of sanitation may be feasible for smaller equipment such as knives, larger equipment with greater mass is unlikely to reach a temperature adequate for sanitation in the time (< 10 s) allowed between carcasses at many commercial processors, thus increasing the potential for cross-contamination between carcasses. ConclusionIn conclusion, these results suggest that equipment sanitation at some points of process may be improved by equipment operators having access to multiple pieces of equipment which can individually be submerged in hot water to achieve dwell times sufficient for surface sanitation.

RESEARCH ON WATER ACTIVITY INDEX IN FROZEN MEAT FOODS

The article deals with a science intensive technology of fast-frozen dishes production with the use of activated liquids and systems. The objective of this research is to investigate the measurement of water activity in the developed frozen meat products. A receipt of fast-frozen dishes includes sausage goods and a vegetable garnish. The sausage goods are made of beef, pork, dried milk, starch, protein-fat emulsion and gel based on the «Kat-gel 95» protein preparation. The water used is treated in the apparatus of «Izumrud» type, obtaining acid and alkaline fractions with a specified level of pH. Their further activation is done using a commercial sound processor «Hielscher Ultrasound Technology UP». Activated liquids obtained have pronounced bactericidal and antiseptic qualities, thus promoting prolonged shelf life of finished goods. The research is done using the analytic and organoleptic methods, the method of measurement, the method of calculation and the expert one. To determine the water activity index we use samples defrosted after thirty days of storing. The values of water activity indices are determined separately for fast-frozen dishes produced with the use of activated liquid systems and for control samples produced with the use of tap potable water. According to the results of the water activity index determination it has been established that the samples produced with the use of activated liquids and systems have the index of 0.9638. The water activity index of the control samples appears to be higher by 0.0198 units in comparison with the samples produced with the use of activated liquids. This fact indicates that water has a stronger connection with non-aqueous components during activation of aqueous systems when producing foods. Consequently, water has a lower possibility to support processes leading to goods spoilage.

A Touch Prediction and Window Sensing Strategy for Low-Power and Low-Cost Capacitive Multitouch Screen Systems

A new multitouch sensing strategy, named the Touch Prediction and Window Sensing (TPWS), is proposed and realized in this paper for projected capacitive touch screens. The detection procedures of TPWS are divided into two stages: a pre-sensing stage for predicting the possible touched regions, and a window sensing stage for obtaining the accurate touched positions. Since the measurements of the untouched sensing cells are reduced significantly, the TPWS strategy needs lower efforts on signal readout and data processing than the traditional strategies. A prototype system was designed and realized, which consists of three identical 48-channel readout chips, a 15-in capacitive touch screen, and a commercial host processor. The readout chip is specially designed for the TPWS strategy using $\hbox{0.13}~\mu\hbox{m}$ 1.8 V/5 V CMOS process. The measurement results show that, the total power consumption of the system is only about 65 mW with a power supply of 5 V, and the reporting rate of the system achieves 500 Hz for no touches and 83 Hz for ten touches. The area of the readout chip is only 0.087 $ ~\hbox{mm}^{2}$ per sensing channel. The proposed TPWS strategy can be used to realize low-power and low-cost multitouch screen system, and it is especially efficient for large-sized screen.

Efficient Security Monitoring with the Core Debug Interface in an Embedded Processor

For decades, various concepts in security monitoring have been proposed. In principle, they all in common in regard to the monitoring of the execution behavior of a program (e.g., control-flow or dataflow) running on the machine to find symptoms of attacks. Among the proposed monitoring schemes, software-based ones are known for their adaptability on the commercial products, but there have been concerns that they may suffer from nonnegligible runtime overhead. On the other hand, hardware-based solutions are recognized for their high performance. However, most of them have an inherent problem in that they usually mandate drastic changes to the internal processor architecture. More recent ones have strived to minimize such modifications by employing external hardware security monitors in the system. However, these approaches intrinsically suffer from the overhead caused by communication between the host and the external monitor. Our solution also relies on external hardware for security monitoring, but unlike the others, ours tackles the communication overhead by using the core debug interface (CDI), which is readily available in most commercial processors for debugging. We build our system simply by plugging our monitoring hardware into the processor via CDI, precluding the need for altering the processor internals. To validate the effectiveness of our approach, we implement two well-known monitoring techniques on our proposed framework: dynamic information flow tracking and branch regulation. The experimental results on our FPGA prototype show that our external hardware monitors efficiently perform monitoring tasks with negligible performance overhead, mainly with thanks to the support of CDI, which helps us reduce communication costs substantially.

A Survey of Techniques for Cache Locking

Cache memory, although important for boosting application performance, is also a source of execution time variability, and this makes its use difficult in systems requiring worst-case execution time (WCET) guarantees. Cache locking is a promising approach for simplifying WCET estimation and providing predictability, and hence, several commercial processors provide ability for locking cache. However, cache locking also has several disadvantages (e.g., extra misses for unlocked blocks, complex algorithms required for selection of locking contents) and hence, a careful management is required to realize the full potential of cache locking. In this article, we present a survey of techniques proposed for cache locking. We categorize the techniques into several groups to underscore their similarities and differences. We also discuss the opportunities and obstacles in using cache locking. We hope that this article will help researchers gain insight into cache locking schemes and will also stimulate further work in this area.

COATCheck

Modern computer systems include numerous compute elements, from CPUs to GPUs to accelerators. Harnessing their full potential requires well-defined, properly-implemented memory consistency models (MCMs), and low-level system functionality such as virtual memory and address translation (AT). Unfortunately, it is difficult to specify and implement hardware-OS interactions correctly; in the past, many hardware and OS specification mismatches have resulted in implementation bugs in commercial processors. In an effort to resolve this verification gap, this paper makes the following contributions. First, we present COATCheck, an address translation-aware framework for specifying and statically verifying memory ordering enforcement at the microarchitecture and operating system levels. We develop a domain-specific language for specifying ordering enforcement, for including ordering-related OS events and hardware micro-operations, and for programmatically enumerating happens-before graphs. Using a fast and automated static constraint solver, COATCheck can efficiently analyze interesting and important memory ordering scenarios for modern, high-performance, out-of-order processors. Second, we show that previous work on Virtual Address Memory Consistency (VAMC) does not capture every translation-related ordering scenario of interest, and that some such cases even fall outside the traditional scope of consistency. We therefore introduce the term transistency model to describe the superset of consistency which captures all translation-aware sets of ordering rules.

COATCheck

Modern computer systems include numerous compute elements, from CPUs to GPUs to accelerators. Harnessing their full potential requires well-defined, properly-implemented memory consistency models (MCMs), and low-level system functionality such as virtual memory and address translation (AT). Unfortunately, it is difficult to specify and implement hardware-OS interactions correctly; in the past, many hardware and OS specification mismatches have resulted in implementation bugs in commercial processors. In an effort to resolve this verification gap, this paper makes the following contributions. First, we present COATCheck, an address translation-aware framework for specifying and statically verifying memory ordering enforcement at the microarchitecture and operating system levels. We develop a domain-specific language for specifying ordering enforcement, for including ordering-related OS events and hardware micro-operations, and for programmatically enumerating happens-before graphs. Using a fast and automated static constraint solver, COATCheck can efficiently analyze interesting and important memory ordering scenarios for modern, high-performance, out-of-order processors. Second, we show that previous work on Virtual Address Memory Consistency (VAMC) does not capture every translation-related ordering scenario of interest, and that some such cases even fall outside the traditional scope of consistency. We therefore introduce the term transistency model to describe the superset of consistency which captures all translation-aware sets of ordering rules.