Commercial Field Programmable Gate Array Research Articles

DICEguard: enhancing DICE security for IoT devices with periodic memory forensics

AbstractThe number of Internet-of-Things (IoT) devices has been increasing rapidly every year. Most of these devices have access to important personal data such as health, daily activities, location, and finance. However, these devices have security problems since they have limited processing power and memory to implement complex security measures. Therefore, they possess weak authentication mechanisms and a lack of encryption. Additionally, there are no widely accepted standards for IoT security. Device Identifier Composition Engine (DICE) was proposed as a standard that enables adding a security layer to low-cost microcontrollers with minimal silicon overhead. However, previous studies show that DICE-based attestation is vulnerable to some remote attacks. In this study, we present a novel method called DICEguard to address the security problems of DICE. One of the key innovations of DICEguard is its incorporation of periodic memory forensics (PMF) technique, leveraging a hardware-based hash engine to detect and mitigate potential security breaches resulting from firmware vulnerabilities. DICEguard enhances the overall resilience of IoT devices against attacks by swiftly detecting alterations indicative of malicious activity through periodic calculation and comparison of firmware digests. Furthermore, DICEguard introduces a one-time programmable (OTP) memory component to safeguard critical security parameters, such as public keys used for signature verification, against tampering by adversaries. This ensures the integrity of essential security measures even in the face of sophisticated attacks. We implemented the enhanced DICE architecture using the open-source RISC-V platform Ibex and the mbedTLS library for cryptographic operations. We performed the hash operations required by DICE in a hardware-based manner on a commercial Field Programmable Gate Array (FPGA) platform rather than firmware, which is more vulnerable to attacks. Our test results show that with negligible area overhead to a standard microcontroller system, the proposed method can detect the simulated attacks.

A low-latency graph computer to identify metastable particles at the Large Hadron Collider for real-time analysis of potential dark matter signatures

Image recognition is a pervasive task in many information-processing environments. We present a solution to a difficult pattern recognition problem that lies at the heart of experimental particle physics. Future experiments with very high-intensity beams will produce a spray of thousands of particles in each beam-target or beam-beam collision. Recognizing the trajectories of these particles as they traverse layers of electronic sensors is a massive image recognition task that has never been accomplished in real time. We present a real-time processing solution that is implemented in a commercial field-programmable gate array using high-level synthesis. It is an unsupervised learning algorithm that uses techniques of graph computing. A prime application is the low-latency analysis of dark-matter signatures involving metastable charged particles that manifest as disappearing tracks.

A continuous ultra-narrow impulse synchronizer using a monolithic field programmable gate array for fast deployment and scalability.

Ultra-narrow pulses serve as critical components in numerous applications. These pulses have ultra-fast leading edges that typically function as precision trigger signals to synchronize various instruments. Ultra-narrow pulses inherently exhibit an ultra-wide bandwidth, gaining significant attention in diverse electronic systems encompassing communications, radar imaging, electronic warfare, and others. Although several techniques have been explored for generating ultra-narrow pulses, field programmable gate arrays (FPGAs) offer a promising alternative in terms of flexibility and integration. This study introduces a scalable delay pulse synchronizer method with a resolution of 23 ps. A programmable, successive, narrow pulse sequence operating at a 1-GHz repetition frequency is implemented within a monolithic FPGA. The performance of the proposed method is evaluated using an existing board with a general commercial FPGA in the laboratory. This new method presents a convenient and efficient approach of achieving ultra-narrow pulse synchronization, being applicable across various fields.

Field-programmable gate array-based residual amplitude modulation suppression and control for compact atomic clocks.

We designed a field-programmable gate array (FPGA) fabric to provide phase modulation techniques to lock lasers to optical frequency references. The method incorporates an active residual amplitude modulation (RAM) suppression scheme that relies on complex modulation. All the required servos to construct an optical atomic clock are incorporated into the same low-cost, commercial FPGA chip. We demonstrate a reliable, long-term RAM suppression of 60 dB with the remaining RAM level at -100 dBc and an improved stability of three decades when applied on a two-photon rubidium clock.

Efficient and Accurate Analog Voltage Measurement Using a Direct Sensor-to-Digital Port Interface for Microcontrollers and Field-Programmable Gate Arrays

Portable sensor systems are usually based on microcontrollers and/or Field-Programmable Gate Arrays (FPGAs) that are interfaced with sensors by means of an Analog-to-Digital converter (ADC), either integrated in the computing device or external. An alternative solution is based on the direct connection of the sensors to the digital input port of the microcontroller or FPGA. This solution is particularly interesting in the case of devices not integrating an internal ADC or featuring a small number of ADC channels. In this paper, a technique is presented to directly interface sensors with analog voltage output to the digital input port of a microcontroller or FPGA. The proposed method requires only a few passive components and is based on the measurements of the duty cycle of a digital square-wave signal. This technique was investigated by means of circuit simulations using LTSpice and was implemented in a commercial low-cost FPGA device (Gowin GW1NR-9). The duty cycle of the square-wave signal features a good linear correlation with the analog voltage to be measured. Thus, a look-up table to map the analog voltage values to the measured duty cycle is not required with benefits in terms of memory occupation. The experimental results on the FPGA device have shown that the analog voltage can be measured with a maximum accuracy of 1.09 mV and a sampling rate of 9.75 Hz. The sampling rate can be increased to 31.35 Hz and 128.31 Hz with an accuracy of 1.61 mV and 2.68 mV, respectively.

Measurements of radiation effects in an antifuse FPGA

This paper presents the irradiation and the measurement analysis for a commercial antifuse Field Programmable Gate Array (FPGA) from Microsemi’s Axcelerator family, part number AX250. Following proton and X-ray beam irradiation, at very high dose rate above 1krad/s, the total ionizing dose (TID) first effects were visible around 260 krad (SiO 2), and this threshold value increases at lower radiation dose rates. We expect for most space and accelerator applications that this value will be at least several Mrads, or even that the FPGA might never reach this threshold. At very high radiation dose rates, TID-induced leakage currents were observed in the device. FPGA data were recorded continuously for more than 100 h after each irradiation with a fully operating FPGA. Quantitatively, the room-temperature annealing of the radiation-induced defects leads to a fast decrease of the device leakage current by a factor of 7 in the first 100 h after irradiation. The last measurements done after three months place the currents to within 30% to 70 % relative to the before-irradiation values in case of two tested FPGA. Several firmware configurations were used to test different logic resources and to measure single event upsets (SEUs). An upper limit of SEU logic cross-section was found to be (2.56 ± 0.51) ⋅ 10−13 cm 2/FPGA for dose rates around 1krad/s. SEU cross-section values for RAM blocks have on average a value of (3.72 ± 0.8) ⋅ 10−14 cm 2/bit. The complete list of results is given and the effects are extrapolated to a high-energy physics experiment environment — LHCb RICH at CERN.

FPGA based telecommand system for balloon-borne scientific payloads

Abstract Telecommand (TC) plays a crucial role in the success of high-altitude balloon experiments. Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes are commonly employed to ensure reliable command operation. The Balloon Facility (BF) of Tata Institute of Fundamental Research (TIFR) uses a TC system based on BCH (31,16) coding technique, to control balloon and payload operations. This paper presents prototyping and implementation of TC encoder and decoder using Spartan 6 Field Programmable Gate Array (FPGA). The code is written in Very high-speed integrated circuit Hardware Description Language (VHDL). Simulation and synthesis are done using Xilinx ISE 14.7 design suite. Simulation results show the design is robust. The TC encoder is implemented in a commercial FPGA development board and the TC decoder is implemented in a specially designed FPGA board, successfully. This paper presents the salient features of the TC system in use and the implementation of the system using FPGA.

An eFPGA Generation Suite with Customizable Architecture and IDE

From edge devices to cloud servers, providing optimized hardware acceleration for specific applications has become a key approach to improve the efficiency of computer systems. Traditionally, many systems employ commercial field-programmable gate arrays (FPGAs) to implement dedicated hardware accelerator as the CPU's co-processor. However, commercial FPGAs are designed in generic architectures and are provided in the form of discrete chips, which makes it difficult to meet increasingly diversified market needs, such as balancing reconfigurable hardware resources for a specific application, or to be integrated into a customer's system-on-a-chip (SoC) in the form of embedded FPGA (eFPGA). In this paper, we propose an eFPGA generation suite with customizable architecture and integrated development environment (IDE), which covers the entire eFPGA design generation, testing, and utilization stages. For the eFPGA design generation, our intellectual property (IP) generation flow can explore the optimal logic cell, routing, and array structures for given target applications. For the testability, we employ a previously proposed shipping test method that is 100% accurate at detecting all stuck-at faults in the entire FPGA-IP. In addition, we propose a user-friendly and customizable Web-based IDE framework for the generated eFPGA based on the NODE-RED development framework. In the case study, we show an eFPGA architecture exploration example for a differential privacy encryption application using the proposed suite. Then we show the implementation and evaluation of the eFPGA prototype with a 55nm test element group chip design.

A Model-Driven Platform for Dynamic Partially Reconfigurable Architectures: A Case Study of a Watermarking System

The reconfigurable feature of FPGAs (Field-Programmable Gate Arrays) has made them a very attractive solution for implementing adaptive systems-on-chip. However, this implies additional design tasks to handle system reconfiguration and control, which increases design complexity. To address this issue, this paper proposes a model-driven design flow that guides the designer through the description of the different elements of a reconfigurable system. It is based on high-level modeling using an extended version of the MARTE (Modeling and Analysis of Real-Time and Embedded systems) UML (Unified Modeling Language) profile. Both centralized and decentralized reconfiguration decision-making solutions are possible with the proposed flow, allowing it to adapt to various reconfigurable systems constraints. It also integrates the IP-XACT standard (standard for the description of electronic Intellectual Properties), allowing the designer to easily target different technologies and commercial FPGAs by reusing both high-level models and actual IP-XACT hardware components. At the end of the flow, the implementation code is generated automatically from the high-level models. The proposed design flow was validated through a reconfigurable video watermarking application as a case study. Experimental results showed that the generated system allowed a good trade-off between resource usage, power consumption, execution time, and image quality compared to static implementations. This hardware efficiency was achieved in a very short time thanks to the design acceleration and automation offered by model-driven engineering.

Unsupervised recycled FPGA detection using exhaustive nearest neighbor residual analysis

Measuring and analyzing aging-induced delay degradation of ring oscillators (ROs) is an effective method to detect recycled field-programmable gate arrays (FPGAs). However, detection methods of conventional recycled FPGAs detection methods assume the existence of known fresh FPGAs (KFFs) as training data for machine-learning-based classification, which is an unrealistic assumption. In this paper, we propose an unsupervised recycled FPGA detection method, where little information on KFF is available. In the proposed method, estimated frequency is calculated from neighboring ROs, and then the residual frequency between the measured and estimated frequencies is used for the detection. Because of the systematic component of process variation, the frequencies of neighboring ROs should be similar when the target FPGA is fresh. Therefore, if the residual is high, the target FPGA is determined as recycled. Experiments using 25 commercial FPGAs under various aging scenarios demonstrate that the proposed method successfully distinguishes between recycled and fresh FPGAs.

Parallel implementation of hardware-efficient adaptive equalization for coherent PON systems

The development of the fifth generation mobile (5G) technique stimulates a higher bandwidth requirement for next generation passive optical network (PON) systems. It is a challenge to further double the data rate from 50 to 100 Gb/s/λ depending on intensity modulation direct detection due to stringent bandwidth constraints on optical and electrical components. Coherent detection technology is a promising candidate for the future 100 Gb/s/λ or higher PON systems. The parallel implementation of hardware-efficient adaptive equalization tailored to PON systems will accelerate the evolution of coherent PON systems. In view of the current situation that logic resources are abundant while hardened multipliers are few for commercial field programmable gate array (FPGA), the purpose of this work is to reduce the number of hardened multiplexers used for FPGA realized signal processing. The waveform distortion caused by chromatic dispersion (CD) and imperfect frequency response of transceiver is rough compensated by using frequency domain equalization, which alleviate the stringent filter length requirement for the following adaptive equalization. Three Coordinate Rotation Digital Computer-based vector rotators are introduced to realize polarization demultiplexing, where the state of polarization is tracing by using a simplified gradient descent algorithm. A non-butterfly equalizer with few taps for each polarization is designed to handle the residual (CD) and the frequency response difference due to external environment variations and manufacturing technology. With the proposed method, the number of hardened multipliers is reduced by 73% compared with conventional 2×2 multiple-input multiple-output equalizer under the case with the similar receiver sensitivity.

FPGA Architecture: Principles and Progression

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster design cycles and lower development costs compared to custom-designed chips. The design of an FPGA architecture involves many different design choices starting from the high-level architectural parameters down to the transistor-level implementation details, with the goal of making a highly programmable device while minimizing the area and performance cost of reconfigurability. As the needs of applications and the capabilities of process technology are constantly evolving, FPGA architecture must also adapt. In this article, we review the evolution of the different key components of modern commercial FPGA architectures and shed the light on their main design principles and implementation challenges.

Proton Beam Validation of a New Single Event Transient Mitigation Technique

A single event transient (SET) filtering technique for non-volatile field programmable gate arrays (FPGAs) are investigated experimentally using the AND-OR-Multiplexer SET filter technique. The technique combines AND – OR gate circuits in parallel with a two input multiplexer to provide a single circuit that can dissipate SETs irrespective of whether the input state is high or low. This paper presents the results of the experimental investigation, with the SET filter applied to various sequential circuit configurations in a commercial Flash-based FPGA, the 0.13-μm ProASIC3E product family (A3PE), by proton beam irradiation. Their implementation and evaluation in-beam show their efficiency in eliminating SETs and single event upsets (SEU) compared to unmitigated designs.

Modification and hardware implementation of cortex‐like object recognition model

Object recognition in the visual cortex of mammals and humans has inspired many computational object recognition models. Hierarchical model and X (HMAX) is a well-known biologically motivated object recognition model with scale and position tolerance and high accuracy. Due to the computational intensive nature, hardware implementation with massive parallel processing is suggested for real-time applications. However, it is important to explore algorithmic trade-offs when mapping an algorithm to are configurable hardware. A direct conversion of the software implementation of an algorithm generally results inefficient hardware resource usage. In this study, the authors propose a novel modification into the HMAX model which makes it suitable for hardware implementation. More precisely, to reduce the number of memory blocks and multipliers of the S2 layer of HMAX produces, they replace the first norm by the second norm, which critically affects the silicon area in an application-specific integrated circuit implementation or the required resources in field-programmable gate array (FPGA). To evaluate the proposed model, they implement a pipelined version of the revised model on a mid-range commercial Xilinx FPGA, i.e. XC6VLX240T platform from a Virtex 6 family of Xilinx using ISE. Compared to the recent hardware implementation of HMAX, the proposed model offers 83% resource degradation in DSP48 slices and 3% in memory blocks.

Reliability Analysis of the SHyLoC CCSDS123 IP Core for Lossless Hyperspectral Image Compression Using COTS FPGAs

Hyperspectral images can comprise hundreds of spectral bands, which means that they can represent a large volume of data difficult to manage with the available on-board resources. Lossless compression solutions are interesting for reducing the amount of information stored or transmitted while preserving it at the same time. The Hyperspectral Lossless Compressor for space applications (SHyLoC), which is part of the European Space Agency (ESA) IP core’s library, has been demonstrated to meet the requirements of space missions in terms of compression efficiency, low complexity and high throughput. Currently, there is a trend to use Commercial Off-The-Shelf (COTS) on-board electronic devices on small satellites. Moreover, commercial Field-Programmable Gate Arrays (FPGAs) have been used in a number of them. Hence, a reliability analysis is required to ensure the robustness of the applications to Single Event Upsets (SEUs) in the configuration memory. In this work, we present a reliability analysis of this hyperspectral image compression module as a first step towards the development of ad-hoc fault-tolerant protection techniques for the SHyLoC IP core. The reliability analysis is performed using a fault-injection-based experimental set-up in which a hardware implementation of the Consultative Committee for Space Data Systems (CCSDS) 123.0-B-1 lossless compression standard is tested against configuration memory errors in a Xilinx Zynq XC7Z020 System-on-Chip. The results obtained for unhardened and redundancy-based protected versions of the module are put into perspective in terms of area/power consumption and availability/protection coverage gained to provide insight into the development of more efficient knowledge-based protection schemes.

Novel Parallel-Processing-Based Hardware Implementation of Baseband Digital Predistorters for Linearizing Wideband 5G Transmitters

In this article, a real-time digital predistortion (DPD) hardware architecture is presented for the linearization of fifth-generation (5G) transmitters with wideband modulation signals. To overcome the linearization bandwidth constraint imposed by the maximum clock frequency of the digital circuit, a new parallel-processing DPD engine architecture is devised to allow multiple samples to be processed per clock cycle. To minimize the complexity and power consumption of the transmitter-observation-receiver that typically scales with the linearization bandwidth, an undersampling scheme using a single low-speed ADC optimized for hardware implementation is devised. The proposed real-time DPD architecture is implemented in a commercial field-programmable gate array that achieves a scalable linearization bandwidth of up to 2.4 GHz with a 300-MHz core clock rate for the digital circuits. The linearization performance and bandwidth scalability of the proposed real-time DPD system were demonstrated experimentally using a silicon-based Doherty power amplifier with a 400-MHz wideband signal operating at 28 GHz and over-the-air measurements using a 64-element beamforming array with an 800-MHz wideband signal also at 28 GHz.

SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs

As the benefits of Moore's Law diminish, computing performance, and efficiency gains are increasingly achieved through specializing hardware to a domain of computation. However, this limits the hardware's generality and flexibility. Field-programmable gate arrays (FPGAs), microchips which can be reprogrammed to implement arbitrary digital circuits, enable the benefits of specialization while remaining flexible. A challenge to using FPGAs is the complex computer-aided design flow required to efficiently map a computation onto an FPGA. Traditionally, these design flows are closed-source and highly specialized to a particular vendor's devices. We propose an alternate data-driven approach, which uses highly adaptable and retargettable open-source tools to target both commercial and research FPGA architectures. While challenges remain, we believe this approach makes the development of novel and commercial FPGA architectures faster and more accessible. Furthermore, it provides a path forward for industry, academia, and the open-source community to collaborate and combine their resources to advance FPGA technology.

Optimizing FPGA Logic Block Architectures for Arithmetic

Hardened adder and carry logic is widely used in commercial field-programmable gate arrays (FPGAs) to improve the efficiency of arithmetic functions. There are many design choices and complexities associated with such hardening, including circuit design, FPGA architectural choices, and the computer-aided design (CAD) flow. However, these choices have not been studied much and hence we explore a number of possibilities. We also highlight front-end elaboration optimization that helps ameliorate the restrictions placed on logic synthesis by hardened arithmetic. We show that hard adders and carry chains increase the performance of simple adders by a factor of 4 or more, but on larger benchmark designs that contain arithmetic improve the overall performance by 15%. Our results also show that for complete application circuits simple hardened ripple-carry adders perform as well as more complex carry-lookahead adders. Our best non-fracturable lookup table (non-fLUT) architecture with hardened arithmetic yields 12% better area-delay product than architectures without hardened arithmetic. We also investigate the impact of fLUTs and their interaction with hardened arithmetic. We find that fLUTs offer significant (12%-15%) area reduction, which is complementary to the delay reduction of hardened arithmetic. Therefore, our best fLUT architectures which use two bits of hardened arithmetic achieve 25% better area-delay product than non-fLUT architectures without hardened arithmetic.

Tunable FPGA Bitstream Obfuscation with Boolean Satisfiability Attack Countermeasure

Field Programmable Gate Arrays (FPGAs) are seeing a surge in usage in many emerging application domains, where the in-field reconfigurability is an attractive characteristic for diverse applications with dynamic design requirements, such as cloud computing, automotive, IoT, and aerospace. The security of the FPGA configuration file, or bitstream , is critical, especially for devices with long in-field lifetimes, where attackers may attempt to extract valuable Intellectual Property (IP) from within. In this article, we propose a tunable obfuscation approach that protects IP from typical bitstream attacks while enabling designers to trade off security with acceptable overhead. We also consider two potential attacks on this protection mechanism: Boolean SAT Attacks on the obfuscation and removal attacks on the protection circuitry. The obfuscation and SAT countermeasure are integrated in a custom CAD framework within a commercial FPGA toolflow and together provide mathematically strong protection against common bitstream attacks. Further, we quantify the difficulty of a removal attack on the protection circuitry through pattern matching and direct bitstream manipulation. The average area, power, and delay overhead for obfuscation with 95% mismatch probability are 18%, 16%, and 8%, respectively, for small combinational circuits, and 1%, 2%, and 5% for larger arithmetic modules.

Fast peak-tracking method for FBG reflection spectrum and nonlinear error compensation

A universal method is proposed for fast tracking the peak wavelength of a fiber Bragg grating (FBG) reflection spectrum, which is the essential procedure of most FBG interrogators. Assuming the FBG reflection spectrum is sampled uniformly, we decompose the Moore–Penrose of the coefficient matrix into a formula that only contains a division and a dozen additions and multiplications; thereby, the cost of computation can be greatly reduced. Based on the analysis of the characteristics of the error introduced by the spectrum’s nonlinearity, we found and defined an error associated with the distance between the sampled peak and actual peak, and the compensating method for the error is also given. After compensation, the proposed method can speed up the tracking process 10 times or more without sacrificing the accuracy. An economical FBG interrogator with a commercial field programmable gate array (FPGA) and a microspectrometer was built up to verify the method, which was able to achieve a measurement frequency of 17 kHz.