Column Parallel Research Articles

A 28.9–38.8 μW dual-mode 10-bit column parallel single-slope ADC with minimum voltage feedback for CMOS image sensors

A dual-mode low-power column parallel single-slope (SS) ADC incorporating Minimum Voltage Feedback (MVF) is proposed for CMOS image sensors. When it works in low-power mode, the ADC utilizes a minimum voltage feedback approach and a dynamic bias structure to minimize the power consumption after the ramp signal surpasses the minimum voltage of a row. In its acceleration mode, it uses the minimum voltages extracted by the MVF circuit to improve the conversion speed. A 10-bit SS ADC with MVF was designed in a 0.18 μm CMOS process. The simulations have been performed to validate the proposed idea. The simulation results show that DNL and INL of the ADC are +0.124/-0.126 LSB and +0.15/-0.12 LSB, respectively. Moreover, the SNDR achieves 61.4 dB, the SFDR is 72.04 dB and the ENOB is 9.9 bit. Under the clock frequency of 100 MHz and the power supply of 3.3 V/1.8 V in the low-power mode, the simulated power consumption of the ADC ranges between 28.9 and 38.8 μW/column, with the column parallel comparator and ramp generator contributing to power reductions of up to 33.0 % and 53.5 %, respectively. The conversion time experiences a notable decrease of up to 65.4 % in the acceleration mode. The power consumption of the added MVF circuit is only 0.15 μW/column.

A 1Gpixel 10FPS CMOS image sensor using pixel array high-speed readout technology

In the very large array CMOS image sensor (CIS), the very large parasitic resistors and capacitors on the column bus cause very slow charging and discharging speeds and affect the readout speed seriously. In order to solve the problem, this work proposed a high-speed readout circuit that can be applied to the very large array of column parallel readout mechanism CIS. Based on 55 nm CIS special process, on the premise of not produce additional bus, by tracking the analog signal settling process in real time, self-acceleration is realized in the terminal of the column bus, then the speed of charging and discharging are improved greatly. In the work, the column bus parasitic parameters of 42,624 × 24,000 pixels CMOS image sensor with 4 μm pixel pitch are analyzed in detail and a method for establishing self-acceleration of column bus is proposed. The experimental results show that the charging time is shortened from 4μs to 790 ns, and the discharging time is shortened from 22.43μs to 1.17μs under 38.3 pF parasitic capacitance and 26.5 kΩ parasitic resistance in the column bus. On the one hand, the frame per second (FPS) of the 1Gpixel CMOS image sensor reach 10FPS, on the other hand, the column bus tail current can be reduced to 1.5 μA, which reducing the power consumption of pixel array, and the sampling interval time of the correlation double sampling (CDS) is compressed, so broadened the frequency of noise suppression. While realizing self-acceleration, the additional power consumption single column is less than 10 μA.

An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing

Computing-In-memory (CIM) accelerators have the characteristics of storage and computing integration, which has the potential to break through the limit of Moore’s law and the bottleneck of Von-Neumann architecture for convolutional neural networks (CNN) implementation improvement. However, the performance of CIM accelerators is still limited by conventional CNN architectures and inefficient readouts. To increase energy-efficient performance, an optimized CNN model is required and a low-power column parallel readout is necessary for edge-computing hardware. In this work, an ReRAM-based CNN accelerator is designed. Mixed-bit operations from 1 bit to 8 bits are supported by an effective bitwidth configuration scheme to implement Neural Architecture Search (NAS)-optimized layer-wise multi-bit CNNs. Besides, column-parallel readout is achieved with excellent energy-efficient performance by a variation-reduction accumulation mechanism and low-power readout circuits. Additionally, we further explore systolic data reuse in an ReRAM-based PE array. Experiments are implemented on NAS-optimized ResNet-18. Benchmarks show that the proposed ReRAM accelerator can achieve peak energy efficiency of 2490.32 TOPS/W for 1-bit operation and average energy efficiency of 479.37 TOPS/W for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\sim 8$ </tex-math></inline-formula> -bit operations with evaluating NAS-optimized multi-bitwidth CNNs. When compared with the state-of-the-art works, the proposed accelerator shows at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$14.18{\times }$ </tex-math></inline-formula> improvement on energy efficiency.

An efficient built‐in error detection methodology with fast page‐oriented data comparison in 3D NAND flash memories

This letter presents an efficient built-in error detection methodology for 3D NAND flash memories, in which fast page-oriented data comparison and column parallel error detection are firstly proposed. The methodology takes advantage of the characteristics of page buffer to perform fast page-oriented comparison between test data and reference data. Thanks to that, both fine error detection mode and column parallel error detection mode can be supported for different test scenarios. Analytical results show that it costs about 164.14 μs and 460 ns in fine and column parallel mode respectively to detect a page which is 16 K bytes. Compared with previous work, the error detection time of the proposed column parallel mode is reduced 99.7% for 3D NAND flash memories.

A self-compensated approach for ramp kickback noise in CMOS image sensor column parallel single slope ADC

A new CMOS image sensor column parallel ADC circuit structure for suppressing the kickback noise of the single slope comparators is proposed in this paper. In order to suppress the kickback noise of the original node, the crosstalk of the shared ramp reference is compensated by detecting the column ramp signal jumping, and the transmission of the noise on the shared reference line is blocked. The proposed approach has been verified and experimented in a 3072(H) × 2560(V) CMOS image sensor based on 55 nm 1P4M CMOS process, and the sensor achieves 12bit precision column parallel digital quantization. In the worst case, when 1 to 1000 columns are flipped simultaneously, the kickback noise can be reduced to less than 1LSB and compensated quickly without additional power consumption and area. The measurement results show that the single slope ADC can be operated at 500 MHz and achieved 4.6μs digital correlated double sampling row time for a 12-bit linear A/D conversion, the DNL is controlled within ±0.48LSB, the INL is not more than ±4LSB, and the SNR is up to 71 dB. It is important that the power consumption of each column is only 24 μW.

Comparison of the performance of oscillating water column devices based on arrangements of water columns

The hydrodynamic performance of oscillating water column (OWC) depends on the depth of the water, the size of the water column and its arrangement, which affects the oscillation of the water surface in the column. An experimental method was conducted by testing 4 water depths with wave periods of 1-3 s. All data recorded by the sensor is then processed and presented in graphical form. The research focused on analyzing the difference in wave power absorption capabilities of the three geometric types of OWC based on arrangements of water columns. The OWC devices designed as single water column, the double water column in a series arrangement which was perpendicular to the direction of wave propagation, and double water column in which the arrangement of columns was parallel to the direction of wave propagation. This paper discussed several factors affecting the amount of power absorbed by the device. The factors are the ratio of water depth in its relation to wavelength (kh) and the inlet openings ratio (c/h) of the devices. The test results show that if the water depth increases in the range of kh 0.7 to 0.9, then the performance of the double chamber oscillating water column (DCOWC) device is better than the single chamber oscillating water column (SCOWC) device with maximum efficiency for the parallel arrangement 22,4%, series arrangement 20.8% and single column 20.7%. However, when referring to c/h, the maximum energy absorption efficiency for a single column is 27.7%, double column series arrangement is 23.2%, and double column parallel arrangement is 29.5%. Based on the results of the analysis, DCOWC devices in parallel arrangement showed the ability to absorb better wave power in a broader range of wave frequencies. The best wave of power absorption in the three testing models occurred in the wave period T = 1.3 seconds.

Low Power CMOS Image Sensors Using Two Step Single Slope ADC With Bandwidth-Limited Comparators &amp; Voltage Range Extended Ramp Generator for Battery-Limited Application

This paper proposes a low-power column-parallel two-step single slope Analog-to-Digital Converter (SS ADC) and voltage range tuned ramp generator for low-power CMOS Image Sensors (CIS). The proposed SS ADC has small bandwidth to drive the low power CMOS Image Sensors, without sacrificing the bandwidth performance. The ADC errors caused by the limited bandwidth can be resolved using dual CDS (Correlated Double Sampling) and using voltage range tuned ramp generator. The proposed two-step structure consists of a resistor DAC (coarse ramp) and a current DAC (fine ramp). The fine ramp has one slope generator, regardless of results of coarse ramp decisions, to remove the mismatch of slope between fine ramp slopes. This sensor of $960\times720$ pixels has been fabricated with 90 nm CMOS process. The measurement results demonstrate that proposed column parallel CDS circuits can achieve the current consumption is about $2~\mu \text{A}$ with 50 MHz main clock frequency, which is less than 33 % of other reports. The frame rate of the proposed CMOS Image Sensors (CIS) is maximum 35 fps. The proposed circuit has a redundancy error correction logic for to calibrate error between coarse and fine conversions. Total power consumption 28 mW from supply voltages of 2.8 V (analog) and 1.5 V (digital).

Mass spectrometric investigation of cardiolipins and their oxidation products after two-dimensional heart-cut liquid chromatography

The anionic phospholipid class of cardiolipins (CL) is increasingly attracting scientific attention in the recent years. CL can be found as a functional component of mitochondrial membranes in almost all living organisms. Changes in the CL composition are favored by oxidative stress. Based on this finding, the investigation of CL and their oxidation products in relation to various disease patterns, including neurodegenerative ones, is moving into the focus of current research. The analysis of this diverse lipid class is still challenging and requires sensitive and selective methods. In this work, we demonstrate an online two-dimensional liquid chromatography (2D-LC) approach by means of a heart-cut setup. In the first dimension, a fast hydrophilic interaction liquid chromatography (HILIC) method was developed for the separation of CL and their oxidation products from other phospholipid classes, but more important from nonpolar lipid classes, such as triacylglycerol and cholesterol. Those classes can negatively affect the electrospray ionization and also the chromatography. For the heart-cut approach, the CL fraction was selectively transferred to a loop using a six-port valve followed by the transfer to a reversed phase (RP) column in second dimension. On the RP column, the transferred CL fraction including the oxidation products were separated according to the hydrophobicity of acyl chain moieties. Matrix effects were significantly reduced compared to the one-dimensional LC-MS method. In addition, the total separation time had not to be prolonged by shifting the equilibration step of the RP column parallel to the separation in first dimension. The heart-cut LC-LC approach was applied to artificially oxidized lipid extracts of bovine heart and yeast by means of Fenton reaction. In summary, 42 species have been identified by high resolution mass spectrometry and database matching. 31 species thereof have been further characterized by MS/MS experiments.

A Test Platform for the Noise Characterization of SiGe Microbolometer ROICs

This paper introduces an in-circuit performance evaluation system for SiGe microbolometer readout integrated circuits (ROICs) that can characterize the overall system noise performance by emulating microbolometers with MOSFETs biased in the triode region. Specifically, the proposed test platform is designed for the testing of imagers with high resistance SiGe microbolometers. The architecture of the ROIC is based on a bridge with active and reference bolometer pixels with a capacitive transimpedance amplifier input stage and column parallel integration with serial readout. Noise measurements along with simulated resistance curves of the dummy detectors are reported. The prototype with 17-μm pixel pitch has been designed and fabricated in a 0.25-μm SiGe BiCMOS process.

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †.

We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.

High resolution X-ray imaging with pnCCDs

Spectroscopic X-ray imaging with semiconductor detectors allows to reconstruct photon events much finer than the pixelsize, if the charge cloud extends over several pixels. To face the challenge of high sensitivity low energy X-ray sensors with (sub)micron resolution and 100% fill factor, MPG HLL developed improved PnCCDs with 36μm pixelsize, very fast frame transfer and column parallel readout. A simple and fast data analysis method to calculate the hit position from event cluster shapes is presented together with measurement results for image and spectral resolution.

An Improved Spinal Neural System-Based Approach for Heterogeneous AUVs Cooperative Hunting

Cooperative hunting by a multi-AUV system in unknown 3D underwater environment is not only a research hot spot but also a challenging task. To conduct this task, each AUV needs to move quickly without obstacle collisions and cooperate with other AUVs considering the overall interests. In this paper, the heterogeneous AUVs cooperative hunting problem is studied, including two main tasks, namely the search and pursuit of targets, and a novel spinal neural system-based approach is proposed. In the search stage, a partition and column parallel search strategy is used in this paper, and a search formation control algorithm based on an improved spinal neural system is proposed. The presented search algorithm not only accomplishes the search task but also maintains a stable formation without obstacle collisions. In the cooperative pursuit stage, a dynamic alliance method based on bidirectional negotiation strategy and a pursuit direction assignment method based on improved genetic algorithm are presented, which can realize the pursuit task efficiently. Finally, some simulations are conducted and the results show that the proposed approach is capable of guiding multi-AUVs to achieve the hunting tasks in unknown 3D underwater environment efficiently.

Hydrogen bonding in goldichite, KFe(SO4)2⋅4H2O: structure refinement

The crystal structure of goldichite KFe(SO4)2⋅4H2O was determined on a single crystal from the Baiyinchang copper deposit, Gansu, China. [P121/c1, a = 10.395(2), b = 10.475(2), c = 9.0875(18) A, β = 101.65(3)°, V = 969.1(3) A3, Z = 4]. All non-H atoms were refined with anisotropic displacement parameters and positions of H-atoms were determined by difference Fourier methods and refined from X-ray diffraction data. The crystal structure of goldichite consists of corrugated sheets parallel to the (100) plane by sharing corners between FeO6 octahedra and SO4 tetrahedra. The interstitial potassium atom exhibits a [KO7(H2O)2] nine-fold coordination, which shares edges to form a column parallel to the c-axis and to build a slab with the corrugated sheet. These slabs are linked in the [100] direction through a network of hydrogen bonds. Three types of hydrogen bonds involve links of slabs: Ow(3)-H(3B)···O(1), Ow(6)-H(6B)···O(11) and Ow(9)-H(9B)···O(11). The FTIR spectrum of goldichite shows a strong absorption between ~3384 cm−1 and ~3592 cm−1, which is in accordance with the O-H···O distances derived from structure data.

Noise reduction effect and analysis through serial multiple sampling in a CMOS image sensor with floating diffusion boost-driving

We have developed a 1/2.3-in. 10.3 mega pixel back-illuminated CMOS image sensor utilizing serial multiple sampling. This sensor achieves an RMS random noise of 1.3e− and row temporal noise (RTN) of 0.19e−. Serial multiple sampling is realized with a column inline averaging technique without the need for additional processing circuitry. Pixel readout is accomplished utilizing a 4-shared-pixel floating diffusion (FD) boost-driving architecture. RTN caused by column parallel readout was analyzed considering the transfer function at the system level and the developed model was verified by measurement data taken at each sampling time. This model demonstrates the RTN improvement of −1.6 dB in a parallel multiple readout architecture.

Octagonal CMOS Image Sensor for Endoscopic Applications

An octagonal shaped CMOS image sensor (CIS) has been developed for endoscopic applications. The octagonal shape of the outlined die is also applied to the pixel matrix which has suppressed corners, resulting in an octagonal pixel matrix of 422'640 effective pixels. The sensor die fits on a circumference of 3.2 mm diameter being this the best die cut ratio between the cut corners and the pixel placement. The missing pixels on the corners are internally compensated by the readout electronics to maintain a rectangular image output format of 680x680 pixels. This paper presents the solutions found to overcome the layout challenges of fitting both row and column logic on the same side of the diagonally cut corners. Furthermore, the sensor features an area efficient column parallel ADC converter, having on the column readout side, only 402 &#x3BC;m overhead total space between the utmost pixel row until the edge of the silicon die. This space is used to place CDS, ADC, column addressing, readout, additional electronics and power routing. The sensor also has a fully autonomous operation, requiring only an external clock supply to drive the internal state machine. The interface requires just 6 connections: 2 for power supply, 2 for bidirectional data and 2 for main clock supply. The frame rate and the exposure are configurable by register. The maximum frame rate is 50 frames per second (FPS) and data is delivered over LVDS serial data link. The integration time can be configured from 147 &#x3BC;s to 20.1 ms. The power supply is 3.3 V with internal Power-On-Reset (POR) and has a power consumption of 91 mW manufactured in 180 nm CIS process.

Parameter estimation of MC-CDMA signals based on modified cyclic autocorrelation

An algorithm, based on frequency domain accumulation for the cyclic autocorrelation of MC-CDMA signals, is proposed to estimate the signal parameters: useful data duration, symbol duration, and chip duration in multipath fading channel. Firstly the cycle autocorrelation of received MC-CDMA signals is computed, then frequency domain accumulation is used to reduce the influence of noise. At last, through interval measurement between the peak pulses in different slices, parameters mentioned above can be estimated. Meanwhile, for the estimation of symbol duration, a novel accumulative average method is developed: by averaging amplitudes of the spectral lines in each column parallel to the time-delay axis in the three-dimensional diagram, the symbol duration can be obtained. The cyclic autocorrelation expression of MC-CDMA signal has been derived, and simulation results show that the proposed algorithm is effective and works well under the condition of low signal-to-noise ratio (SNR).

A 128-Stage CMOS TDI Image Sensor With On-Chip Digital Accumulator

A 128-stage CMOS time delay integration (TDI) image sensor with on-chip digital accumulator was presented in this paper. By using two sets of sampling capacitors and an optimized timing, the on-chip column parallel cyclic analog-to-digital converter (ADC) in the sensor conducts the correlated double sampling, digital program gain amplifying, and A/D conversion all altogether in one ADC’s conversion time simultaneously. An on-chip digital accumulator suitable for this sensor is also proposed. A prototype $1024 \times 128$ CMOS TDI image sensor is fabricated in the 0.18- $\mu \text{m}$ CMOS technology, and the measurement results proof that the pixels and readout circuits in the sensor work properly. With a line rate of 3875 lines/s, the sensor costs a power consumption of 290 mW and a silicon area of $18.2~\textrm {mm}\times 18.9$ mm. The estimated maximum sensitivity of the fabricated sensor is 2010 $\textrm {V}/\textrm {lux}\cdot \textrm {sec}$ . This paper is suitable for applications in low-illumination, high scanning speed, and remote sensing systems.

The Belle II DEPFET pixel detector

The Belle II experiment at KEK (Tsukuba, Japan) will explore heavy flavour physics (B, charm and tau) at the starting of 2018 with unprecedented precision. Charged particles are tracked by a two-layer DEPFET pixel device (PXD), a four-layer silicon strip detector (SVD) and the central drift chamber (CDC). The PXD will consist of two layers at radii of 14mm and 22mm with 8 and 12 ladders, respectively. The pixel sizes will vary, between 50μm×(55–60)μm in the first layer and between 50μm×(70–85)μm in the second layer, to optimize the charge sharing efficiency. These innermost layers have to cope with high background occupancy, high radiation and must have minimal material to reduce multiple scattering. These challenges are met using the DEPFET technology. Each pixel is a FET integrated on a fully depleted silicon bulk. The signal charge collected in the ‘internal gate’ modulates the FET current resulting in a first stage amplification and therefore very low noise. This allows very thin sensors (75μm) reducing the overall material budget of the detector (0.21% X0). Four fold multiplexing of the column parallel readout allows read out a full frame of the pixel matrix in only 20μs while keeping the power consumption low enough for air cooling. Only the active electronics outside the detector acceptance has to be cooled actively with a two phase CO2 system. Furthermore the DEPFET technology offers the unique feature of an electronic shutter which allows the detector to operate efficiently in the continuous injection mode of superKEKB.

Geomagnetic forecasts driven by thermal wind dynamics in the Earth's core

There exists a fundamental as well as practical interest in being able to accurately forecast the future evolution of Earth's magnetic field at decadal to secular ranges. This work enables such forecasts by combining geomagnetic data with an Earth-like numerical model of a convection-driven fluid dynamo. The underlying data assimilation framework builds on recent progress in inverse geodynamo modelling, a method which estimates an internal dynamic structure for Earth's core from a snapshot of the magnetic field and its instantaneous rate of change at the surface, and takes advantage of linear relationships and long-range correlations between observed and hidden state variables. Here the method is further evolved into a single-epoch ensemble Kalman filter, in order to initialise at a given epoch an ensemble of states compatible with the observations and representative of the uncertainties in the estimation of hidden quantities. The ensemble dynamics, obtained by subsequent numerical integration of the prognostic model equations, are found to be governed by a thermal wind balance or equilibrium between buoyancy forces, the Coriolis force and the pressure gradient. The resulting core fluid flow pattern is a quasi-steady eccentric gyre organised in a column parallel to Earth's rotation axis, in equilibrium with a longitudinal hemispheric convective density anomaly pattern. The flow provides induction for the magnetic field, which also undergoes a realistic amount of diffusion. Predictions of the present magnetic field from data taken within the past century show that the ensemble has an average retaining good consistency with the true geomagnetic evolution and an acceptable spread well representative of prediction errors, up to at least a secular range. The predictability of the geodynamo thus appears to significantly exceed previous theoretical expectations based on the chaotic divergence of ensemble members. The assimilation generally outperforms the linear mathematical extrapolations from a 30-yr prediction range onwards, with a 40 per cent improvement in Earth-surface error at a secular range. The geomagnetic axial dipole decay observed over the past two centuries is predicted to continue at a similar pace in the next century, with a further loss of 1.1 ± 0.3 µT by year 2115. The focal (or minimum intensity) point of the South Atlantic geomagnetic anomaly is predicted to enter the South Pacific region in the next century, with the anomaly itself further deepening and widening. By year 2065, the minimum intensity is predicted to decrease by 1.46 ± 0.4 µT at the Earth surface and the focal point to move 12.8 ± 1.4 deg westwards with a slight northward component. This corresponds to a drift rate of 0.26 deg yr −1 , similar to the typical geomagnetic westward drift observed over the past four centuries. The same drift rate is also predicted until 2115 with a further (but more uncertain) intensity decrease

A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory

This paper presents a narrow-pitch readout circuit for multi-level phase change memory (PCM) employing an architecture of two-step 5 bit logarithmic ADC. A single-slope-architecture based fine ADC yields a 15 $\mu$ m-width compact single channel readout circuit for column parallel readout structure. A current-mode 2 bit flash ADC for coarse conversion and the pipelined architecture between the coarse and fine conversion enhance the readout rate up to 13 Mcells/sec. With the enhanced residue accuracy provided by the replica circuit of residue generator, the ADC achieves excellent linearity of 9.96 b (linear ADC equivalent). The integration-based residue generation effectively reduces circuit noise and yields 8.7 ENOB. The prototype chip was fabricated in a 65 nm CMOS process and the measured power consumption from a single channel readout circuit was 105 $\mu$ W at 13 Mcells/sec conversion rate at 1.2 V supply.