Collector-substrate Capacitance Research Articles

Introduction of Airgap Deeptrench Isolation in STI Module for High Speed SiGe : C BiCMOS Technology

AbstractThe impact of capacitive coupling effects increases with scaling down the dimensions and towards higher performances. For bipolar technologies, the introduction of deep trench isolation gives a substantial reduction in the collector substrate capacitance. In this paper a method for the formation of airgap deep trenches (with 1μm – depth 6 μm) is presented. The method is fully compatible with standard CMOS Shallow Trench Isolation (STI) and does not require additional masking steps. The approach is based on a partial removal of the poly-Si filling in the trench. Subsequently, inside D-shape oxide spacers are formed narrowing the opening of the trench down. An SF6 plasma is used to convert the nearly completely incorporated poly-Si to volatile SiF4, such that it desorbs through the opening. In the following steps the opening is sealed by depositing SiO2 resulting in the formation of an airgap (patent pending). The normal module for STI formation continues without any adaptation of the process steps. In total four standard additional process steps are needed.The absence of the common oxide/poly filling in the deep trench decreases the peripheral collector substrate capacitance with an order of magnitude to a value of 0.02fF/μm. As a consequence the low power available bandwidth is improved with 90%.

The comparison of isolation technologies and device models on SiGe bipolar low noise amplifier

Junction isolation is promising for cost reduction and high power circuit applications due to its relatively lower fabrication complexity and thermal conductivity, but larger area and collector-substrate capacitance ( C cs) seem drawbacks as compared to the deep trench isolation (DTI) technology. A simulation work is proposed for the size selection guide of unit cell to have the low cost benefit of junction isolation without sacrificing the gain and noise performance of the low noise amplifier (LNA) operated at 5.2 GHz.

A novel lateral bipolar transistor with 67 GHz f/sub max/ on thin-film SOI for RF analog applications

In this paper, a novel lateral bipolar transistor on thin film silicon-on-insulator (SOI) is presented. With a small emitter size of 0.12/spl times/3.0 /spl mu/m/sup 2/, low base resistance of 270 /spl Omega/ due to a novel Co silicided base electrode and low base-collector parasitic capacitances of 1.4 fF due to SOI material, it achieves the highest f/sub max/ of 67 GHz among SOI bipolar transistors. Also, the low emitter-base capacitance of 1.5 fF and the low collector-substrate capacitance of 2.5 fF are realized. The transistor has a simple structure, which is fabricated with simplified processes without any new sophisticated technologies, excluding trench isolation and epitaxial base used in current bipolar transistors. This can lower the fabrication cost of transistors. We have demonstrated the possibility of lateral bipolar transistor on thin film SOI as next-generation device for RF analog applications.

A 60-GHz f/sub T/ super self-aligned selectively grown SiGe-base (SSSB) bipolar transistor with trench isolation fabricated on SOI substrate and its application to 20-Gb/s optical transmitter ICs

A 60-GHz cutoff frequency (f/sub T/) super self-aligned selectively grown SiGe-base (SSSB) bipolar technology is developed. It is applied to 20-Gb/s optical fiber transmitter ICs. Self-aligned bipolar transistors mutually isolated by using a BPSG-filled trench were fabricated on a bond-and-etchback silicon-on-insulator (SOI) substrate to reduce the collector-substrate capacitance C/sub CS/. The SiGe base was prepared by selective epitaxial growth (SEG) technology. A 0.4-/spl mu/m wide emitter was used to reduce the junction capacitances. The maximum cutoff frequency f/sub T/ and the maximum frequency of oscillation f/sub max/ were 60 and 51 GHz, respectively. By using this technology, Si-ICs for an optical transmitter system were made, such as a selector (a multiplexer without input and output retiming D-type flip-flops (D-F/Fs)), a multiplier, and a D-F/F. An internal high-speed clock buffer circuit achieves stable operation under a single clock input condition in the selector and the multiplier ICs. Their stable operation was confirmed up to 20 Gb/s. The selector IC for data multiplexing operates at over 30 Gb/s.

A model for the dependence of maximum oscillation frequency on collector to substrate capacitance in bipolar transistors

Parasitic effects associated with the collector degrade the frequency performance of a bipolar transistor. These effects include collector series resistance and collector-substrate capacitance. A simple analytical model has been derived to show the dependence of the maximum oscillation frequency f max on these parameters. The significance of using bonded SOI material to reduce collector-substrate capacitance is discussed. The analytical model is used to predict the factor of improvement of this technology over conventional diffusion isolated bulk silicon technology. By considering the impact of process optimisation, an improvement in f max by a factor of between two and three is predicted at maximum power output. By trading off this improvement in f max for lower power operation, it is possible to achieve a significant reduction in power-delay product.

Rapid Thermal Epitaxy for Device Applications

AbstractRapid thermal epitaxy (RTE) is studied for a variety of applications including transistors as well as optoelectronic devices. Two transistor applications are discussed here. First, the growth of n-type epitaxial layers over n+ buried layers for low power BiCMOS, and second, the growth and fabrication of charge injection transistors (CHINTs) from a multi-layer structure including strained Si1−xGex layers.Scaled bipolar transistors for BiCMOS integrated circuits require low collector-substrate capacitance in order to minimize power consumption. The unintentional incorporation of dopant into a growing epitaxial layer, known as autodoping, can affect the ultimate lower limit of the collector-substrate capacitance. In this work, we studied the effects of epitaxial layer growth rate, arsenic buried layer implant dose, and pre-epitaxial bake temperature on autodoping using RTE. To begin, we experimented with the buried layer implant dose to check its affect on lateral autodoping. The amount of autodoping increased when the buried layer implant dose increased, confirming the source of the arsenic autodoping as the buried layer. Also, in contrast to data from conventional reactors, we found the peak interface concentration and integrated dose in regions adjacent to the buried layer to be linearly dependent on the growth rate (i.e. low growth rates trap less arsenic at the substrate/epi layer interface). Next, by adjusting the pre-bake temperature over a range from 800 to 1050°C without changing the growth conditions, we first observed a rise in autodoping with temperature to 950°C at which point the incorporated autodoping dose and peak concentration began to fall. Through simulation of the evaporated arsenic from the buried layer and data for arsenic desorption from the silicon surface, we explain this behavior. Finally, using the data gathered on the autodoping characteristics of RTE, we show a process using two growth rate steps and a low temperature pre-bake step which completely eliminates the lateral autodoping peak. Using this new growth process, epitaxial silicon films over arsenic doped buried layers for low power BiCMOS are possible.Charge injection transistors and logic elements have been successfully implemented in a Si/Si0.7Ge0.3 heterostructure grown by RTE on a Si substrate. Shallow p+ source and drain ohmic contacts are obtained by a boron diffusion from a selectively deposited boron doped Ge layer. Room temperature operation of the charge injection transistor is demonstrated for the first time. High frequency measurements indicate a short circuit current gain cutoff frequency of 6 GHz.

A low-capacitance bipolar/BiCMOS isolation technology. I. Concept, fabrication process, and characterization

A device isolation structure for low-parasitic bipolar transistor integration is presented. The concept involves two selective epitaxial growth steps (SEG) and two polishing cycles which replace the collector-epitaxy and the deep/shallow trench formation in conventional device isolation. With an optimum device layout, the collector-substrate capacitance is reduced to /spl sime/30%, the collector-base capacitance to /spl sime/70%, and the extrinsic base contact resistance to >

The use of parasitic nonlinear capacitors in class E amplifiers

The most common class E amplifier configuration uses a single transistor with a shunt capacitor and a series resonant output filter. Until now a linear shunt capacitance has been assumed. However, to achieve operation at 900 MHz and above, it is of interest to rely solely upon the nonlinear parasitic collector-substrate capacitance of the transistor. An analytical theory for operation at 50% duty cycle and nonlinear capacitance is presented in this correspondence, and the effects on the power capability of the amplifier are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A high-performance 0.5- mu m BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5- mu m BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 mu m/sup 2/ by creating self-aligned bit-sense and V/sub ss/ contacts. A WSi/sub x/ polycide emitter n-p-n transistor with an emitter area of 0.8*2.4 mu m/sup 2/ provides a peak cutoff frequency (f/sub T/) of 14 GHz with a collector-emitter breakdown voltage (BV/sub CFO/) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f/sub T/ and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process. >

The design and characterization of nonoverlapping super self-aligned BiCMOS technology

An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L/sub eff/=1.1 mu m and W/sub n//W/sub p/=10 mu m/10 mu m exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f/sub T/, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated. >

Suppression of lateral autodoping from arsenic buried layer by selective epitaxy capping

An effective way to suppress lateral autodoping from the heavily arsenic-doped buried layer during silicon epitaxy is described. By using this simple technique, collector-substrate capacitance (C/sub cs/) is minimized. This process is ideal for high-speed BiCMOS and bipolar technology. A thin epilayer is first grown selectively on the buried layer. This selectively grown film suppresses the release of arsenic during the subsequent epi growth. High-performance bipolar devices have been fabricated in this epi material. Electrical measurements indicate that the crystalline quality is excellent.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>