A low-capacitance bipolar/BiCMOS isolation technology. I. Concept, fabrication process, and characterization

Abstract

A device isolation structure for low-parasitic bipolar transistor integration is presented. The concept involves two selective epitaxial growth steps (SEG) and two polishing cycles which replace the collector-epitaxy and the deep/shallow trench formation in conventional device isolation. With an optimum device layout, the collector-substrate capacitance is reduced to /spl sime/30%, the collector-base capacitance to /spl sime/70%, and the extrinsic base contact resistance to >