Coefficient Of Thermal Expansion Mismatch Research Articles

In-situ monitoring of carbon fiber/epoxy composite with FBG sensors under curing and thermal cycling conditions

Residual strains from curing process as well as thermal expansion behaviors in application process are critical to structural design of composites. Here we demonstrate the applicability of fiber Bragg grating (FBG) sensors for in-situ measurements of strain evolution in epoxy resin and unidirectional (UD) laminate under curing and thermal cycling conditions. The validity of the FBG sensors was verified by the TMA tests. From the data recorded by the sensors, the information about real-time gel point, strain/temperature evolution and residual strains during curing can be obtained. The epoxy resin and UD laminates have distinct curing histories and characteristics under the same curing conditions because of the exothermic reaction. During thermal cycling, we found that the coefficient of thermal expansion (CTE) of the UD laminate is directional dependent as is the residual strain, i.e., it increases with fiber orientation angle. In addition, the relaxation of partial residual strains, attributed to the mismatch in CTE between the specimen and the mold, was captured by FBG sensors around the glass transition temperature during the first thermal cycle.

Effect of Dew Point on the Selective Oxidation and Reactive Wetting of DP980 Steel during Hot‐Dip Galvanizing

The hot‐dip galvanizing behavior of an advanced high‐strength steel DP980 is investigated, focusing on selective oxidation and reactive wetting, as compared with interstitial‐free (IF) steel. The steels are annealed with varying dew points of −50, −25, and 0 °C, and then immersed in a galvannealing bath containing 0.13 wt% dissolved Al. The results show that higher concentrations of Mn and Si elements in DP980 steel result in an increase of nonwettable Mn2SiO4/MnSiO3. The increase in dew point does not promote the internal oxidation of alloying elements in DP980 as in IF steel, and DP980 displays the lowest external oxidation at −50 °C. After galvanizing, Mn and Si oxides are observed above the inhibition layer, which is due to the oxide cracking caused by the mismatch of thermal expansion coefficient between the surface oxides and the steel, and then the oxide flaking and incorporation are caused by the interfacial infiltration through cracks and the formation of intermetallic crystals of Fe–Al and subsequent Fe–Zn. Therefore, IF steel maintains good wetting in the presence of external oxides, while DP980 steel exhibits more external film oxides and poor coating quality at high dew points.

Production-related effects on the adhesive bondline performance of structural adhesives joining dissimilar materials

Adhesive bonding is a commonly used technology for joining dissimilar materials. However, production-related effects on the performance of the bondline have to be considered for an accurate joint design. In case of an adhesive joint in an automotive multi-material body in white, these effects arise from the so-called mismatch in thermal expansion coefficients, which leads to distortions of the adhesive in an uncured state or even damage in the cured one. The distortion of the uncured adhesive in the normal direction is called the ‘viscous fingering effect’, which reduces the adhesively bonded cross section by changing the adhesive bondline's shape to thin ‘fingers’ and therefore influences the materials properties. To investigate the effect of viscous fingering on the modulus, strength and energy release rate, linear butt bonded specimens and Tapered Double Cantilever Beams (TDCB) with different elongations of the adhesive bondline in the viscous state are investigated. The results are used to parameterize a cohesive zone model (CZM) and perform numerical analysis of the TDCB specimen for validation and to build up a model of a dissimilar joint consisting of a steel hatprofile and an adhesively bonded aluminum panel subjected to thermal distortions.

Numerical Study on the Influence of Polyimide Thickness and Curing Temperature on Wafer Bow in Wafer Level Packaging

In wafer level packaging, polyimide and electroplated copper are dielectric and conducting materials respectively in the so-called redistribution layers. During the wafer fabrication process large amount of stress is generated in those layers due to curing shrinkage of the polyimide and the coefficient of thermal expansion mismatch of both materials to silicon which can lead to severe wafer bow after a high temperature curing. In different applications polyimide can be used either only as passivation layer over electroplated copper, or polyimide is applied before the redistribution layer and then a second polyimide layer is applied as passivation. In the current study the effect of different polyimide integrations is investigated. In-situ wafer bow measurements and finite element method studies were conducted with samples, with and without polyimide below redistribution layer, exposed to different curing temperatures to understand the change in wafer bow and copper residual stress. It is observed that wafers with polyimide before redistribution layer show higher stress relaxation in copper with decreasing curing temperature, resulting therefore in a lower wafer bow. A good agreement is achieved between the experimentally measured and the simulated wafer bow.

Assembly of Large Flip Chip Die in Ceramic Packages

Hermetic packaging is required to ensure the reliability of processors and application specific integrated circuit (ASIC) chips that are used in strategic systems, whose operating lifetimes typically exceed thirty years. Performance requirements for emerging system applications are dictating the need for one thousand or more I/O, which precludes the use of wire bonded devices. These packaging requirements can be met by flip chip bonding die onto multilayer, high temperature cofired ceramic substrates. The hermetic environment is provided by a Kovar metal ring that is brazed onto the ceramic and sealed in the final assembly step, by welding on a metal cover. Several process and design requirements must be met to achieve high reliability flip chip assemblies. Reflowed devices must be free of flux residues because they are corrosive, provide a path for ion diffusion, are a source of moisture and degrade the adhesion of underfill to chip and substrate. Removal of flux residues by cleaning is problematic because the gap between chip and substrate is very small relative to chip area. A better approach is to bond chips without flux, as we do, by reflowing them in a formic acid environment. An important reliability requirement for strategic hardware is the ability to sustain many cycles over extended temperature ranges. Temperature cycles induce plastic deformation in the solder connections as a result of stresses generated by the mismatch in thermal expansion coefficients of the chip and package. These stresses can be reduced significantly by underfilling the bonded chip with a filled adhesive. Choice of material as well as process execution impact the effectiveness of underfill enhancement of reliability. Optimization of both the physical design and composition of the solder connections is essential to producing reliable flip chip assemblies. We make extensive use of finite element analyses (FEA) in which we track the accumulation of plastic strain energy in the solder connections as they are subjected to temperature cycle induced stresses. Good correlations between the energy accumulated per cycle and the number of cycles to failure can be achieved if accurate state models of the solder are used. We have a catalog of Anand models for the solder compositions that we use in our FEA simulations. One of the more challenging aspects of designing high performance flip chip packages is matching the size and pitch of the bond pads on the ceramic with those on the chip. Current devices use 90 micron diameter pads on 200 micron pitch, but newer designs are migrating towards 80 micron diameter pads on 180 micron pitch. It challenging to maintain tight tolerances on pad geometries in these higher density packages and to route all the additional signals. Thermal management is also an important component of the package design. Thermal vias and thermally conductive underfills are used to remove heat from the front side of the chip. On the backside of the chip, the gap between chip and cover is minimized and filled with a high thermal conductivity interface material. High fidelity FEA modeling is necessary to ensure that the chip can be adequately cooled in its hermetic environment. This paper discusses the impact of these design and assembly factors on the reliability of high performance, hermetically packaged flip chip assemblies.

DIC to evaluate a model composite system cracking due to CTE mismatch

Coefficient of thermal expansion (CTE) mismatch in composites under temperature variation can lead to the system cracking. In this study, Digital Image Correlation (DIC) was used to investigate this phenomenon in a model composite system (MCS) composed of a single cylindrical inclusion into a ceramic mortar matrix. Temperature variation experiments assisted by DIC were conducted to evaluate the CTE mismatch of the MCS and to observe its cracking. An analytical model was used to fit the experimental radial displacement field of the MCS, which allowed the computation of the inelastic maximum principal strain field, highlighting the radial crack pattern. The crack initiation and propagation were evaluated via damaged elements in the interface region and the computation of the average Mean Crack Opening Displacement and Surface Crack Density for crack regions. This methodology is appliable for a single inclusion MCS, with improvement perspectives for application in multiple inclusions MCS.

A strategy to improve the thermal fatigue resistance of solder joints based on amorphous Co-P coating to spontaneously build skeleton of CoSn3 laths

Integrated circuit systems are always suffering the temperature cycling environment caused by frequent power on and off. Mismatch in thermal expansion coefficients among chip package components will cause severe cyclic stress to the solder joints. During thermal fatigue, β-Sn grains tended to generate thermal fatigue cracks at the grain boundaries. This work proposed a strategy of using amorphous Co-15 at.% P coating as the interface layer to inhibit the initiation and propagation of thermal fatigue cracks and improve the shear strength of solder joints by numerous endogenous CoSn3 laths. Mechanistically, based on the amorphous structure of the Co-P coating, Co atoms would massively and rapidly diffuse into the molten solder during the liquid-solid diffusion stage of reflow soldering, and the eutectic solidification together with β-Sn spontaneously precipitated numerous laths of CoSn3 intermetallic compounds (IMC), which were evenly distributed and became the skeleton of the solders. The skeleton-like CoSn3 laths with high elastic modulus were the reinforcing phase of Sn-based solder, but also refined the grains of β-Sn. The refinement of β-Sn grains and the strengthening of CoSn3 laths played an important role in inhibiting the initiation and propagation of thermal fatigue cracks. In addition, a discontinuous Co-Sn IMC layer was formed between the amorphous Co-P and the solder. The alternating appearance of CoSn3 and relatively soft β-Sn at the interface avoided the generation of cracks at the interface during temperature cycling.

Study on the Manufacturability of X Dimension Fan Out Integration Package with Organic RDLs (XDFOI-O)

The concept of chiplet was proposed in the post- Moore era. How to layout the multiple chips with different processes and sizes in the package structure is a problem that needs to be considered as different layouts may significantly affect the manufacturability during the packaging process. XDFOI-O is a 2.5D organic interposer structure with a significant coefficient of thermal expansion mismatch in it. Different layouts may cause excessive stress concentration in the package structure, as well as large wafer warpage, which can affect the normal operations of the production line. Stress accumulation on specific chiplet during the wafer thinning process is another manufacturability problem, leading to chip cracking. Prospective finite element analysis can be applied to evaluate the various layouts. In simulation work, different placement processes of dummy chips as stiffeners, as well as different chiplet thicknesses and underfill coverage, can be used as factors for simulation studies, thereby making a reference for further chiplet package design.

Low temperature recovery of OFF-state stress induced degradation of AlGaN/GaN high electron mobility transistors

Thermal annealing is a widely used strategy to enhance semiconductor device performance. However, the process is complex for multi-material multi-layered semiconductor devices, where thermoelastic stresses from lattice constant and thermal expansion coefficient mismatch may create more defects than those annealed. We propose an alternate low temperature annealing technique, which utilizes the electron wind force (EWF) induced by small duty cycle high density pulsed current. To demonstrate its effectiveness, we intentionally degrade AlGaN/GaN high electron mobility transistors (HEMTs) with accelerated OFF-state stressing to increase ON-resistance ∼182.08% and reduce drain saturation current ∼85.82% of pristine condition at a gate voltage of 0 V. We then performed the EWF annealing to recover the corresponding values back to ∼122.21% and ∼93.10%, respectively. The peak transconductance, degraded to ∼76.58% of pristine at the drain voltage of 3 V, was also recovered back to ∼92.38%. This recovery of previously degraded transport properties is attributed to approximately 80% recovery of carrier mobility, which occurs during EWF annealing. We performed synchrotron differential aperture x-ray microscopy measurements to correlate these annealing effects with the lattice structural changes. We found a reduction of lattice plane spacing of (001) planes and stress within the GaN layer under the gate region after EWF annealing, suggesting a corresponding decrease in defect density. Application of this low-temperature annealing technique for in-operando recovery of degraded electronic devices is discussed.

Impact of asymmetric electrodes on ferroelectricity of sub-10 nm HZO thin films

In this study, platinum (Pt) and tungsten (W), two materials with dissimilar coefficients of thermal expansion (CTE) and work functions (WF), are used as the top electrode (TE) and the bottom electrode (BE) in metal/ferroelectric/metal (MFM) structures to explore the ferroelectricity of hafnium zirconium oxide (HZO) with a thickness less than 10 nm. The electrical measurements indicate that a higher CTE mismatch between HZO and TE/BE is beneficial for enhancing the ferroelectric properties of nanoscale HZO thin films. The different WFs of TE and BE generate a built-in electric field in the HZO layer, leading to shifts in the hysteresis loops and the capacitance–voltage characteristics. The structural characterizations reveal that the preferred formation of the orthorhombic phase in HZO is dominated by the W BE. The device in which W is used as the TE and BE (the W/HZO/W MFM structure) presents the optimal ferroelectric performance of a high remanent polarization (2P r = 55.2 μC cm−2). The presence of tungsten oxide (WO x ) at the W/HZO interfaces, as revealed by high-resolution transmission microscopy, is also responsible for the enhancement of ferroelectric properties. This study demonstrates the significant effects of different CTEs and WFs of TE and BE on the properties of ferroelectric HZO thin films.

A novel insight into Au-Au thermosonic flip chip joint under extreme thermal cycles: Defect characterization and failure analysis

Au-Au thermosonic flip chip joints are regarded as a promising chip-substrate interconnect structures and their reliability has been a concern. Compressing the top of Au stud bumps during the coining process would result in plastic deformation of Au; During the bonding process, plastic deformation took place at the interface of Au stud bump and substrate under the impact of ultrasonic vibration, elevated temperature, and bonding pressure; additionally, due to different Coefficient of Thermal Expansion (CTE) between various components of the joint, the mismatch of CTE caused by the thermal cycling process would also result in plastic deformation. For Au element with extraordinary ductility, plastic deformation would inevitably lead to various material defects. This research first performed thermal cycling tests on Au-Au thermosonic flip chip joints, and found that a crack developed after 500 cycles and it propagated along the interface to the entire width of the joint, which seriously injured the joint. Here, for the first time, this research characterized all types of material defects (dislocations, stacking fault, twin, and amorphization) at the bonding interface of the Au-Au flip chip joint which underwent 500 thermal cycles. Their causes and effects on cracking were investigated individually, finally a novel failure mechanism was proposed from the perspective of material defects and a technique to prevent cracking was proposed. This research is anticipated to provide an in-depth study of the microstructure at the bonding interface of Au-Au flip chip joints and the impact of various defects on their reliability.

Microstructure and oxidation behavior of SiOC coatings on C/C composites co-deposited with HMDS and TEOS by using CVD process

Silicon oxycarbide (SiOC) coatings were prepared through isothermal chemical vapor co-deposition by using two precursors of hexamethyldisilane (HMDS) and tetraethyl orthosilicate (TEOS). The microstructure, composition and the protectiveness on C/C composite against oxidation of the coatings prepared at temperatures ranging from 1423 K to 1563 K and pressures ranging from 500 Pa to 1200 Pa were investigated, respectively. After oxidation, cracks and defects were formed in the coatings of all conditions due to the volume shrinkage of amorphous SiO2 crystallization and the mismatch of thermal expansion coefficient (CTE) between SiOC coatings and substrate. The most oxidation-resistant SiOC coating was obtained at 1563 K and 500 Pa, which exhibited the lowest weight loss rate of 4.87 % after 12 h of oxidation at 1673 K in air condition.

Tuning the ORR catalytic activity of LaFeO3-δ-based perovskite cathode for solid oxide fuel cells by doping with alkaline-earth metal elements

Co-based perovskite cathodes have demonstrated impressive catalytic activity for oxygen reduction reaction (ORR) at intermediate temperatures. However, these cathodes face the challenges such as high cost and thermal expansion coefficient (TEC) mismatch. On the other hand, Fe-based perovskite oxides like LaFeO3 exhibit more stable properties and lower TEC, but their ORR activity is not as remarkable as that of Co-based cathodes. In this study, La3+ at the A-site of LaFeO3 was substituted by aliovalent alkaline-earth metal cations. The research findings reveal that the doping of alkaline-earth metal ions induces the formation of structural defects and alters the valence state of Fe. This leads to an increase in the conductivity and oxygen vacancy concentration, which are critical for ORR kinetics in both H–SOFC and O–SOFC. Among the various dopants, Sr doped LaFeO3 (LSrF) exhibits the most outstanding ORR catalytic activity. This can be attributed to its highest total conductivity, O2− conductivity, oxygen surface exchange coefficient, and oxygen bulk diffusion coefficient. At 700 °C, single cell with LSrF cathode achieves peak power densities of 0.781 and 0.894 W cm−2, for O2--conducting solid oxide fuel cell (SOFC) and H+-conducting SOFC, respectively. These performances are essentially twice that of single cell with LaFeO3 cathode. The findings of this study provide valuable insights into doping strategies for Fe-based perovskite cathodes and contribute to the advancement of IT-SOFC cathode research.

Improving efficiency of silicon solar cells by integrating SiO2-coated lead-free Cs3Bi2Br9 perovskites quantum dots as luminescence down-shifting layer

Lead-based perovskite quantum dots (QDs) have promising applications in optoelectronic devices, but commercial applications are limited by the potential toxicity and poor stability of lead. Meanwhile, there are lattice, polarity, and thermal expansion coefficient mismatches in integrating semiconductor materials onto the surface of photoelectronic circuit devices, resulting in high-density defects limiting the reliability of photoelectronic devices. Therefore, there is a need to investigate perovskite alternatives that are non-toxic, stable, and can be effectively coupled to silicon photonic circuits. In this paper, lead-free perovskite Cs3Bi2Br9/SiO2 QDs were synthesized. The emission wavelength falls within the 400–560 nm range, exhibiting vibrant blue photoluminescence and demonstrating exceptional air stability for a duration exceeding 60 days. Optical tests and density-functional theory (DFT) calculations show that the silica shell layer effectively binds the electron and hole wave functions, prevents photon-generated carriers from escaping, reduces surface defects, and improves the carrier recombination probability. Meanwhile, using Cs3Bi2Br9/SiO2 QDs as a luminescent down-shifting (LDS) layer in combination with a conventional silicon solar cell, the photovoltaic conversion power was increased by 1.82%. Hence, the core-shell structure is designed by the green environmental protection method to control the improvement of the PL characteristics of QDs, which opens a window for the synthesis of new barrier materials in ethanol and water systems, making the Cs3Bi2Br9/SiO2 QDs have great potential for the application of novel optoelectronic devices in the future.

Effective Strategies for Electron Beam Additive Manufacturing of Graded Metal Interfaces between Stainless Steel and Vanadium

This work examines the feasibility of joining two dissimilar metals, vanadium (V) and wrought Nitronic 40 stainless steel, through electron beam additive manufacturing (EBAM). Depositing V on Nitronic 40 led to mixed results with some builds exhibiting microcracking and other builds exhibiting severe cracking resulting in delamination. These build failures are thought to be caused by a large coefficient of thermal expansion (CTE) mismatch and solubility issues, demonstrating the challenges associated with this material combination. The large melting temperature discrepancy between Nitronic 40 and V was thought to exacerbate the issues with CTE mismatch and solubility. Four strategies could be employed by EBAM to mitigate the observed issues to successfully deposit V on Nitronic 40: (1) adjust wire feed speed, (2) use dual wire feeders, (3) use different wire feedstocks to control composition, and (4) create a transition layer known as buttering to accommodate CTE mismatch.

Effect of High Al Content AlGaN Buffer Layer on the Properties of GaN‐on‐Silicon Materials

The lattice parameter and thermal expansion coefficient mismatch between the silicon substrate and GaN lead to high tensile stress, which makes the GaN epitaxial layer prone to cracking. Effective compensation of tensile stress on GaN to prevent cracking is an important issue in GaN epitaxial growth. In this work, GaN‐on‐silicon materials with different AlGaN buffer layer structures are prepared by metal‐organic chemical vapor deposition (MOCVD). The GaN epitaxial material with a smooth and crack‐free surface is fabricated by inserting 7 AlGaN buffer layers. The crystal quality of GaN is characterized using high resolution X‐ray diffraction (HRXRD). The full‐width half maximum (FWHM) value of GaN(002) and GaN(102) crystal plane is 398 and 780 arcsec, respectively. The surface root mean square (RMS) roughness of GaN material is 0.31 nm, and the vertical breakdown voltage (BV) of the epitaxial wafer reaches 918 V. The results show that high Al content of the AlGaN buffer layer can effectively reduce the tensile stress and dislocation density of the GaN layer when the entire AlGaN layer thickness remains constant. Suppressing the generation of surface cracks and improving the crystal quality can improve the vertical breakdown voltage and two‐dimensional electron gas (2‐DEG) characteristics of GaN epitaxial wafers.

High-temperature strain-mediated oxidation of 2D MoS2

MoS2 is 2D material applicable for electronics, photo-detectors, light-emitting diodes, and solar cells. Since these applications operate at elevated temperatures, determining and controlling the environmental stability of MoS2 is essential. This study uses Raman spectroscopic experiments at elevated temperatures to observe reversible and irreversible changes in 2D MoS2 films with varying thickness, morphology, and substrate to explore the limits of its thermal stability. Molecular dynamics simulations and in-situ X-ray diffraction confirm that thermal expansion causes the Raman reversible spectral shifts. Further analysis reveals irreversible spectral shifts associated with oxidation and strain effects caused by oxidation with two distinct modes. The former is due to the general homogenous thinning of layers from the top layer down through randomly spaced sulfur vacancies. The latter is due to inhomogeneous oxidation, which known to occur as localized pitting at grain boundaries, void formation from nucleation centers, or stress corrosion cracking starting from edges under strain. Segregation of doping and strain contributions confirms higher strain in the edges. Annealing increases the spread of the strain distribution. These results highlight the critical role of strain, resulting from thermal expansion coefficient mismatch between substrates and 2D MoS2 films, on their environmental stability.

Calibration for determination of compressive stress in glass‐to‐metal seals via photoluminescence spectroscopy

AbstractCompressive stress in glass‐to‐metal seals is crucial to ensure sealing quality and service reliability. Photoluminescence spectroscopy (PS), which relies on the piezospectroscopic effect of Cr‐doped α‐Al2O3, shows promise for stress detection owing to its rapid detection, non‐destruction, and high resolution. The premise of the PS technique is to fill a glass matrix with alumina particles and detect signals from the alumina. In this study, the interaction between alumina particles and the glass matrix was analyzed to calibrate the measured stresses and investigate the stress state in the glass. Test results for glass‐to‐metal seals are believed to consist of simultaneous internal residual stress and external applied stress. The internal residual stress is formed due to the coefficient of thermal expansion mismatch between glass and alumina and is assumed to transfer by radial compression. In the experiment, it was detected by the PS technique and verified by X‐ray diffraction using an unstressed sample without metal housing. The external applied stress is formed due to metal housing compaction and possibly transferred by the shear effect. The stress distribution within the pre‐stressed sample containing metal housing was also measured by the PS technique. Then, calibrations were conducted on the measured stresses based on the deduced stress transfer relationships. Finally, finite element models were established to simulate the internal residual stress and external applied stress respectively to prove the validity of the calibration method, and mutually anastomotic results were obtained within the target margin of error.

Ablation performance of rare earth oxide (REO)-stabilized tetragonal and cubic zirconia coatings as a thermal protection system (TPS) for carbon/carbon composites

To protect carbon/carbon (C/C) composites from severe oxidation and ablation at temperatures exceeding 500 ℃ during the hypersonic applications, a novel Sm2O3-stabilized ZrO2 coating is applied using atmospheric plasma spray. The surface was pre-treated with an oxyacetylene flame to increase the surface roughness and, therefore, to create geometric textures known as anchors. The non-equilibrium tetragonal (t΄) ZrO2 coating stabilized with 6 mol% Sm2O3 offered the best ablation resistance, with survivability maintained through 120 seconds of ~390 W/cm2 heat flux oxyacetylene ablation heating without any denudation from the C/C substrate. The coating significantly improved the ablation resistance of C/C by reducing the mass ablation rate by ~71% and the linear ablation rate by ~94%. Despite a significant thermal expansion coefficient mismatch between the substrate and the coating, a well-defined mechanical adhesion characterized by the anchors was observed in pre- and post-ablated coating microstructures, indicating its influence in improving ablation resistance.

Thermal expansion studies of Li2TiO3 by dilatometry and in-situ high-temperature X-ray diffraction

Li2TiO3 (lithium titanate) is a material of interest in the field of fusion reactors due to its potential application as a tritium breeder material. Because of the extreme working conditions and temperature gradients involved, thermal expansion properties are critical to consider when assessing a material for a fusion reactor. The reactor is subjected to severe neutron flux, high temperature and thermal cycling, which can cause significant stress on the material. A low coefficient of thermal expansion (CTE) of Li2TiO3 is important as it mitigates mechanical stress and minimized the risk of structural damage resulting from thermal cycling. Material degradation, cracking, or delamination might result from a mismatch in CTE between different materials in the reactor. Therefore the estimations of material's thermal expansion properties hold significance for the designing and fabrication of structural material. In this study, Li2TiO3 material was compacted into pellets and high-temperature X-ray diffraction (HT-XRD) was employed to obtain X-ray diffraction patterns from room temperature to 1273 K at 100 K intervals. The lattice parameters (a, b, and c) of Li2TiO3 polycrystals were determined and corresponding unit cell volumes were estimated at each temperature. The thermal expansion percentages for the lattice parameters a, b, and c between room temperature and 1273 K were found to be 1.21%, 1.84%, and 1.83% respectively. The calculated coefficient of thermal expansion (CTE) were determined as 12.5 × 10−6 K−1, 19 × 10−6 K−1, and 18.9 × 10−6 K−1for lattice parameters a, b and c respectively. The crystallographic density at room temperature was estimated to be 3.42 g/cm3. The molar volume was calculated to range between 32.12 and 33.72 cm3/mol from room temperature to 1273 K. Additionally, high-temperature dilatometry was employed to measure the thermal expansion of Li2TiO3, resulting in the estimation of coefficient of thermal expansion. From room temperature to 1290 K, the thermal expansion percentage and mean coefficient of thermal expansion were calculated to be 1.91% and 19.64 × 10−6 1/K, respectively. Furthermore, the temperature dependent mean and instantaneous thermal expansion values were also determined. The differential scanning calorimetry (DSC) method was used to estimate the temperature of the monoclinic to cubic transformation, which was determined to be 1416 K. This paper provides a comprehensive description of the conducted experiments, accompanied by the detailed analysis of the thermal expansion properties derived through the use of High-Temperature X-Ray Diffraction (HT-XRD) and HT-dilatometry (High-Temperature Dilatometry).