Burst-error-correcting Codes Research Articles

New three- and four-dimensional toric and burst error-correcting quantum codes

New three- and four-dimensional toric and burst error-correcting quantum codes

Construction Technique and Evaluation of High Performance t-bit Burst Error Correcting Codes for Protecting MCUs

The occurrences of Multiple Cell Upset (MCU) are more liable to arise in modern memory systems with the continuous upgradation of microelectronics technology from micron to deep submicron scales. These MCUs are mainly induced due to radiations in memory systems. Error Correcting Codes (ECCs) with lower design complexity are generally preferred for the mitigation of MCUs. The major drawback of the existing ECC is requiring higher overheads as error correction capability increases. In this paper, authors have proposed a new class of high performance [Formula: see text]-bit Burst Error Correcting (BEC) codes. Parity check matrices ([Formula: see text]) have been proposed for 3-bit and 4-bit BEC codes with word lengths of 16-bit, 32-bit and 64-bit. Also a simplified decoding scheme has been introduced for these codes. The proposed codecs have been designed and implemented in FPGA and ASIC platforms. The proposed codecs are compact in area, faster in speed and efficient in power compared to existing related schemes. But these lower design constrains are achieved at the cost of increase in redundancy. So, the proposed codecs can be employed in applications where redundancy is not the only constrain for correcting [Formula: see text]-bit burst errors caused by MCUs.

Securing a Wireless Network-on-Chip Against Jamming-Based Denial-of-Service and Eavesdropping Attacks

Wireless networks-on-chips (NoCs) (WiNoCs) have emerged as a possible solution to the nonscalable multihop data transmission paths in traditional wired NoC architectures. Using low-power transceivers in NoC switches, novel WiNoC architectures have been shown to achieve higher energy efficiency with improved peak bandwidth and reduced on-chip data transfer latency. However, using wireless interconnects for intrachip data transfer over an unguided medium introduces additional security vulnerabilities in on-chip communication arising from either external attackers or internal hardware Trojans. In this article, we propose a mechanism to make the wireless communication in a WiNoC secure against persistent jamming-based denial-of-service (DoS) attacks and eavesdropping (ED) from both external and internal attackers. Persistent jamming attacks on the on-chip wireless medium will cause interference in data transfer over the duration of the attack resulting in errors in contiguous bits, known as burst errors. Therefore, we use a burst-error correction code to monitor the rate of burst errors received over the wireless medium and deploy a machine-learning (ML) classifier to detect the persistent jamming attack and distinguish it from random burst errors. In the event of a persistent jamming attack, alternate routing strategies are proposed to avoid the DoS attack over the wireless medium, so that a secure data transfer can be sustained even in the presence of persistent jamming. In the event of an external ED attack, we deploy a low-latency and lightweight data scrambling method to secure communication over the wireless channel. In the case of an internal ED, we propose a mechanism to identify the attacker and prevent the attack. We evaluate the proposed techniques on a WiNoC in the presence of DoS and ED attacks from both internal and external attackers. On an average, 99.87% of the attack on DoS detection was achieved with the chosen ML classifier. A bandwidth degradation of < 3% is experienced in the event of both DoS and ED internal attacks. The wireless interconnects are disabled in the presence of a persistent external jamming DoS attack for security, therefore eliminating the advantages of the wireless interconnections making the performance of the WiNoC comparable with that of a wired NoC. Although scrambling overheads are incurred in the presence of an external ED attack, the overheads are minimized by adopting simple XOR-based encoding and decoding.

Two-Dimensional Algebraic Codes for Multiple Burst Error Correction

We construct native binary 2D binary cyclic codes capable of correcting multiple occurrences of multiple non-overlapping pre-defined 2D error shapes using frequency domain techniques. The starting location of each error shape is determined using a novel decoding algorithm based on a careful selection of the common zero set. The proposed code construction is generic and offers superior coding rates compared to the native 2D BCH code with the same error correction ability.

Low Delay 3-Bit Burst Error Correction Codes

The increasing importance of Multiple Cell Upsets (MCUs) in modern memories has spurred research on error correction codes that can correct adjacent bit errors. For example, Double Adjacent Error Correction (DAEC), 3-bit burst and 4-bit burst codes have been proposed in the last years. However, as the error correction capabilities are increased so is the complexity of the encoder and decoder circuits. This directly impacts the encoding and decoding delay and thus limits the use of the codes in high speed memories. To reduce the complexity, some techniques have been proposed recently. Those include more advanced optimization programs to find codes with a lower number of ones in the parity check matrix or the interleaving of data and parity check bits to simplify the decoding. In this paper, those techniques are combined to design more efficient 3-bit burst error correction codes. The encoders and decoders for the proposed codes have been implemented and compared with the state of the art 3-bit burst error correction codes. The results show that the new codes reduce the encoder and decoder delay significantly. Therefore, the proposed codes provide memory designers with a more efficient option to implement protection against 3-bit burst errors for high speed memories.

Optimum shortened cyclic codes for multiple burst-error correction

Optimum shortened cyclic codes for multiple burst-error correction

Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links

We propose an energy efficient error control code for the on chip interconnection link capable of correcting any type of error patterns including random and burst errors up to five (i.e. 1, 2, 3, 4, and 5 errors). The proposed code is based on single error correction–double error detection (SEC–DED) extended Hamming code and standard triplication error correction scheme. Using single error correction–double error detection (SEC–DED) extended Hamming code and standard triplication error correction scheme a new decoding algorithm is proposed to correct multiple errors up to five in on-chip interconnection link. Triplication error correction scheme provides crosstalk avoidance by reducing the coupling capacitance of the interconnection wire. The proposed code provides high reliability compared to other error control codes. The performance of the proposed code is evaluated for codec area, codec power, codec delay, residual flit error rate, link swing voltage and link power. For the given reliability requirement of 10−5 and 10−20, the proposed code achieves low residual flit error rate and low swing voltage. The low swing voltage results in the reduction of the link power consumption up to 68% compared to the existing error control codes for on chip interconnection link. The low residual flit error rate and low link power make the proposed code appropriate for on chip interconnection link.

Two-dimensional interleaving with burst error-correcting codes

Binary two-dimensional arrays are considered, where the patches of errors contain more than one symbol from the same codeword, i.e. arrays with repetitions. The relative digit positions in each codeword are taken into account when performing interleaving, and burst error-correcting codes are used instead of random error-correcting codes.

Coding theory and cryptography - the essentials (2nd edn), by D. R. Hankerson, D. G. Hoffman, D. A. Leonard, C. C. Lindner, K. T. Phelps, C. A. Rodger and J. R. Wall. Pp. 350. $85. 2000. ISBN 0 8247 0465 7 (Marcel Dekker).

Coding theory and cryptography - the essentials (2nd edn), by D. R. Hankerson, D. G. Hoffman, D. A. Leonard, C. C. Lindner, K. T. Phelps, C. A. Rodger and J. R. Wall. Pp. 350. $85. 2000. ISBN 0 8247 0465 7 (Marcel Dekker). - Volume 85 Issue 504

Performance evaluation of burst-error-correcting codes on a Gilbert-Elliott channel

The performance of single burst-error-correcting (BEC) codes used over bursty channels is evaluated. The channel is represented by the Gilbert-Elliott (1960, 1963) model, which has been used by numerous authors to evaluate the performance of random-error-correcting (REC) codes over bursty channels. Recursive expressions are derived, which are used in evaluating the probability of a codeword error. These expressions and an approximate closed-form expression are applied to the performance of a single (23,12) BEC code.

Codes for multiple localized burst error correction

A new construction method for codes correcting multiple localized burst errors is proposed. The codes obtained by this method improve upon codes presented by Larsson (1995) in size, while keeping the encoding and decoding complexity low. Like the Larsson codes, the proposed codes are asymptotically optimal when the number of bursts to he corrected is fixed and the correctable burst length grows linearly with the codelength. Unlike the Larsson codes, the proposed codes are also asymptotically optimal when the number of bursts to be corrected and the correctable burst length are both fixed.

Two new classes of compound-error correcting codes and their performance

The major errors that occur in a communication channel are the random error and the burst error. The codes considered in the past are mostly to correct one of those errors. The errors that occur in an actual channel, however, are not necessarily restricted to either the random or the burst error. It is obviously more general to consider the case where both types of error occur in a mixed way. This paper considers the case where the random and the burst errors occur in the same code word, and proposes the construction of the code, together with the decoding method, to enable errors to be corrected with a sufficiently high probability. The proposed code is constructed by combining the BCH code with the Fire code, which is the burst error-correcting code. Hence, the random error-correcting ability also is provided. The property that the burst error pattern can approximately be derived is utilized even if there exists a random error, and both errors can be corrected. Then, a code with a higher efficiency is given and is compared to the Reed-Solomon code. It is shown, as a result, that the coding/decoding method proposed in this paper is useful in the bursty compound-error channel. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 3, 80(1): 91–103, 1997

Two new classes of compound‐error correcting codes and their performance

The major errors that occur in a communication channel are the random error and the burst error. The codes considered in the past are mostly to correct one of those errors. The errors that occur in an actual channel, however, are not necessarily restricted to either the random or the burst error. It is obviously more general to consider the case where both types of error occur in a mixed way. This paper considers the case where the random and the burst errors occur in the same code word, and proposes the construction of the code, together with the decoding method, to enable errors to be corrected with a sufficiently high probability. The proposed code is constructed by combining the BCH code with the Fire code, which is the burst error-correcting code. Hence, the random error-correcting ability also is provided. The property that the burst error pattern can approximately be derived is utilized even if there exists a random error, and both errors can be corrected. Then, a code with a higher efficiency is given and is compared to the Reed-Solomon code. It is shown, as a result, that the coding/decoding method proposed in this paper is useful in the bursty compound-error channel. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 3, 80(1): 91–103, 1997

Burst error correcting 2k‐ary cyclic an codes generated by natural number A1·p

AbstractCyclic an codes are considered to be suitable for error detection and error correction in arithmetic operations. Cyclic an codes using radix 2k representation are called 2k‐ary cyclic an codes. This paper is concerned with 2k‐ary cyclic an codes for burst error correction. After describing the structure of these codes and arithmetic burst errors, the smallest code generator A1 that provides a 2k‐ary cyclic an code with the burst error correcting ability b is presented. We also suggest burst error correcting 2k‐ary cyclic an codes generated by A1.p. Furthermore, error‐trapping decoding for 2k‐ary cyclic an codes is shown.

Throughput analysis method for hybrid ARQ schemes over burst error channels

A definition of a burst error channel using a Markov model was presented by T. Sato et al. in a previous paper (1991). A throughput analysis method of hybrid automatic repeat request (ARQ) under the burst error channel using the three-state Markov model is described. The hybrid ARQ is studied for the random and burst error correction codes as the forward error correction (FEC) code, and multiframe rejection (MREJ) as the ARQ. The throughput efficiency is obtained with both an infinite buffer memory and a finite buffer memory. The applicable range of the burst error channel is clarified for the hybrid ARQ using random and burst error correction codes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Runlength limited codes for random and burst error correction

A product code approach to the design of multiple error correcting runlength limited codes is presented. In contrast to recent coding schemes of this type they are based entirely on binary coding operations and are therefore relatively simple to realise in hardware. A table of some illustrative codes is presented.

A class of binary burst error-correcting quasi-cyclic codes

A class of binary quasi-cyclic burst error-correcting codes based upon product codes is studied. An expression for the maximum burst error-correcting capability for each code in the class is given. In certain cases, the codes exist in the class which have the same block length and number of check bits as the Gilbert codes, but correct longer bursts of errors than Gilbert codes. By shortening the codes, it is possible to design codes which achieve the Reiger bound. >

Rate 1/2 and 2/3 Majority Logic Decodable Binary Burst Error-Correcting Codes

A new design procedure is described for constructing rate 1/2 and rate 2/3 majority logical decodable burst error-correcting codes. The rate 1/2 codes are closely related to the codes of Srinivasan [1].

Fast Burst Error-Correction Scheme with Fire Code

A fast burst error-correction decoder is proposed. It can be used for high-speed decoding of a burst error-correcting Fire code having the generator polynomial G(x) = (1 + x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sup> )p(x), where p(x) is irreducible and of degree m and the degree of G (x) is r = c + m, r being the number of redundancy bits. The decoder needs at most r -1 cycles to find both the error burst pattern and its location, whereas conventional decoding needs up to n cycles [1] (n is the number of bits in a codeword), or a fraction of n [2]. The decoding scheme is based on new aspects of the structure of the error syndrome and the parity check matrix of Fire code recently observed by the author. These aspects allow partial syndrome processing in the decoding process. This makes hardware costs relatively low and enables very high-speed decoding. The decoding scheme makes use of modern mapping devices such as programmable read only memories (PROM's) and field programmable logic arrays (FPLA's), resulting in relatively compact and cheap hardware. The encoder/decoder could probably be implemented as a single-chip LSI circuit.

Efficient burst-correcting cyclic codes

A class of single burst error-correcting cyclic codes is introduced. The binary version of these codes has block length n = 2m − 1, number of parity check digits n − k = 2m−1, and correct bursts of length b = 2m−2, where m is an integer. These codes achieve the upper bound b ≤(n − k)/2, and normally have more information digits than interleaved codes of the same burst-correcting power. The multilevel case is also treated in the letter.