Code Size Reduction Research Articles

Reducing TCB complexity for security-sensitive applications

The large size and high complexity of security-sensitive applications and systems software is a primary cause for their poor testability and high vulnerability. One approach to alleviate this problem is to extract the security-sensitive parts of application and systems software, thereby reducing the size and complexity of software that needs to be trusted. At the system software level, we use the Nizza architecture which relies on a kernelized trusted computing base (TCB) and on the reuse of legacy code using trusted wrappers to minimize the size of the TCB. At the application level, we extract the security-sensitive portions of an already existing application into an AppCore. The AppCore is executed as a trusted process in the Nizza architecture while the rest of the application executes on a virtualized, untrusted legacy operating system. In three case studies of real-world applications (e-commerce transaction client, VPN gateway and digital signatures in an e-mail client), we achieved a considerable reduction in code size and complexity. In contrast to the few hundred thousand lines of current application software code running on millions of lines of systems software code, we have AppCores with tens of thousands of lines of code running on a hundred thousand lines of systems software code. We also show the performance penalty of AppCores to be modest (a few percent) compared to current software.

High-quality ISA synthesis for low-power cache designs in embedded microprocessors

Energy efficiency, performance, area, and cost are critical concerns in designing microprocessors for embedded systems, such as portable handheld computing and personal telecommunication devices. This work introduces framework-based instruction set architecture (ISA) synthesis, which reduces code size and energy consumption by tailoring the instruction set to the requirement of a targeted application. This is achieved by replacing the fixed instruction and register decoding of general-purpose embedded processors with programmable decoders that can achieve application-specific processor performance, low energy consumption, and smaller code size while maintaining the fabrication advantages of a mass-produced single-chip solution. Experimental results show that our synthesized instruction set results in significant power reduction in the L1 instruction cache compared with ARM® instructions.

Reducing code size through address register assignment

In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance, since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55%). This work presents a compiler-based optimization strategy to “reduce the code size in embedded systems.” Our strategy maximizes the use of indirect addressing modes with postincrement/decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring). Experimental results on a set of benchmark codes show the effectiveness of our solution and indicate that our approach outperforms the previous approaches to the problem. In addition to resulting in significant reductions in instruction memory (storage) requirements, the proposed technique improves execution time.

Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)

For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a “dual instruction set”, where processor architectures support a normal (usually 32-bit) Instruction Set, and a narrow, space-efficient (usually 16-bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This feature however, requires compilers that can reduce code size by compiling for both Instruction Sets. Existing compiler techniques operate at the routine-level granularity and are unable to make the trade-off between increased register pressure (resulting in more spills) and decreased code size. We present a compilation framework for such dual instruction sets, which uses a profitability based compiler heuristic that operates at the instruction-level granularity and is able to effectively take advantage of both Instruction Sets. We demonstrate consistent and improved code size reduction (on average 22%), for the MIPS 32/16 bit ISA. We also show that the code compression obtained by this “dual instruction set” technique is heavily dependent on the application characteristics and the narrow Instruction Set itself.

Applyinq AspectJ to J2EE application development

(AOP) programming is a technique that allows programmers to modularize crosscutting concerns (behavior that cuts across the typical divisions of responsibility, such as concurrency or security). Aspect-oriented programming and the AspectJ language can reduce code size and defects while increasing understandability. Video Monitoring Services of America (VMS) began to investigate the adoption of AOP into the development of Adbase, the Java 2 Enterprise Edition-based application. Adbase supplies a Web-based search and e-commerce interface on VMS's library of advertising data. It uses a wide range of J2EE technologies, both commercial and open source. The Adbase team varied from four to seven full-time developers during the time frame covered by this article. We followed a modified version of extreme programming with a focus on emergent design and adherence to XP practices such as programmer testing-and pair programming

Design optimization and space minimization considering timing and code size via retiming and unfolding

The increasingly complicated DSP processors and applications with strict timing and code size constraints require design automation tools to consider multiple optimizations such as software pipelining and loop unfolding, and their effects on multiple design parameters. This paper presents an Integrated Framework for Design Optimization and Space Minimization (IDOM) toward finding the minimum configuration satisfying timing and code size constraints. We show an effective way to reduce the design space to be explored through the study of the fundamental properties and relationships among retiming function, unfolding factor, timing, and code size. We present theorems to show that a small set of feasible unfolding factors can be obtained effectively to produce high-quality designs. The IDOM algorithm is proposed to generate a minimal configuration of the design by integrating software pipelining, unfolding, and code size reduction techniques. The experimental results on a set of DSP benchmarks show the efficiency and effectiveness of our technique.

Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions

Existing trend of processors shows a progress toward customizable and reconfigurable architectures. In this paper, we study the benefit of combining the architectural design of a VLIW DSP and the concepts of modern customizable processors like ASIPs (application specific instruction set processors) for code size reduction. VLIW DSP architectures exhibit heterogeneous connections between functional units and register files for speeding up special tasks. Such architectural characteristics can be effectively exploited through the use of complex instruction set extensions (ISEs). Although VLIWs are increasingly being used for DSP applications to achieve very high performance, such architectures are known to suffer from increased code size. This paper also addresses how to generate and use ISEs that can result in significant code size reduction in VLIW DSPs without degrading performance. Unfortunately, contemporary techniques for generation of ISEs when applied before resource-binding fail to generate legal ISEs for VLIW architectures with heterogeneous connectivity between the functional units and register files. We propose a heuristic-based approach to generate ISEs for a generalized heterogeneous-connectivity-based VLIW DSP architecture. We achieve an average code size reduction of 25 percent on the MiBench suite with no penalty in performance by applying our ISE generation algorithms on the Tl TMS320C6xx, a representative VLIW DSP. We also show that the overhead of the required architectural assists for our approach is minimal: The TMS320C6xx pipeline meets the required timing with only a limited overhead in area.

Link-time binary rewriting techniques for program compaction

Small program size is an important requirement for embedded systems with limited amounts of memory. We describe how link-time compaction through binary rewriting can achieve code size reductions of up to 62% for statically bound languages such as C, C++, and Fortran, without compromising on performance. We demonstrate how the limited amount of information about a program at link time can be exploited to overcome overhead resulting from separate compilation. This is done with scalable, cost-effective, whole-program analyses, optimizations, and duplicate code and data elimination techniques. The discussed techniques are evaluated and their cost-effectiveness is quantified with Squeeze++, a prototype link-time compactor.

An efficient and secure protocol for sensor network time synchronization

The emerging field of wireless sensor networks offers countless possibilities for achieving large scale monitoring in a distributed environment. These networks of resource constrained nodes require time synchronization for various distributed operations, but traditional protocols have significant overhead and rapidly deplete battery power. This paper addresses the challenges of sensor network engineering by proposing an efficient and secure time synchronization protocol named Tempest. The protocol reduces overhead and conserves power by using passive participation. It allows a node to infer the canonical time by simply overhearing the communication of its neighbors. It also authenticates protocol messages, and uses cross-layer control to manipulate counters in an encryption module to prevent attacks. Its implementation uses only minimal processing and negligible state, while an emphasis on reuse and modularity reduces code size. The protocol is implemented on embedded sensor node hardware, and is shown to substantially reduce overhead while maintaining the synchronization accuracy of recent related work. This reduction in overhead saves valuable energy, extending the lifetime of each sensor node and the lifetime of the sensor network itself.

HiDRA—A reactive multiprocessor architecture for heterogeneous embedded systems

Embedded systems are typically heterogeneous requiring interacting hardware and software components, are locally synchronous while being globally asynchronous and combine both control and data dominated blocks. Conventional architectures and hardware–software platforms do not directly support such heterogeneity leading to complex design flow and verification process for such systems. This paper presents a new architecture for heterogeneous embedded systems called HiDRA based on multiple reactive processor cores. The architecture supports globally asynchronous locally synchronous systems with a mix of data-dominated and control-dominated behaviors. The reactive processor cores implement Esterel-like computation with architectural support for signal polling, emission and preemption. HiDRA also provides primitives for communication and synchronization between concurrent processes. A low level (concurrent reactive assembly) language has been specified to model embedded applications, which are executable directly on the HiDRA platform. The first implementations with up to four reactive processors have been done on the standard FPGAs. Performance comparison with a typical application realized from system level language ECL reveals significant speedup and reduction in code size.

The design, implementation, and evaluation of adaptive code unloading for resource-constrained devices

Java Virtual Machines (JVMs) for resource-constrained devices, e.g., hand-helds and cell phones, commonly employ interpretation for program translation. However, compilers are able to produce significantly better code quality, and, hence, use device resources more efficiently than interpreters, since compilers can consider large sections of code concurrently and exploit optimization opportunities. Moreover, compilation-based systems store code for reuse by future invocations obviating the redundant computation required for reinterpretation of repeatedly executed code.However, code storage required for compilation can increase the memory footprint of the virtual machine (VM) significantly. As a result, for devices with limited memory resources, this additional code storage may preclude some programs from executing, significantly increase memory management overhead, and substantially reduce the amount of memory available for use by the application.To address the limitations of native code storage, we present the design, implementation, and empirical evaluation of a compiled-code management system that can be integrated into any compilation-based JVM. The system unloads compiled code to reduce the memory footprint of the VM. It does so by dynamically identifying and unloading dead or infrequently used code; if the code is later reused, it is recompiled by the system. As such, our system adaptively trades off memory footprint and its associated memory management costs, with recompilation overhead. Our empirical evaluation shows that our code management system significantly reduces the memory requirements of a compile-only JVM, while maintaining the performance benefits enabled by compilation.We investigate a number of implementation alternatives that use dynamic program behavior and system resource availability to determine when to unload as well as what code to unload. From our empirical evaluation of these alternatives, we identify a set of strategies that enable significant reductions in the memory overhead required for application code. Our system reduces code size by 36--62%, on average, which translates into significant execution-time benefits for the benchmarks and JVM configurations that we studied.

An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs

Energy efficiency, performance, area, and cost are critical concerns in designing microprocessors for embedded systems such as portable handheld computing and personal telecommunication devices. This work introduces the concept of framework-based instruction set synthesis (FITS), which is a new instruction synthesis paradigm that falls between a general-purpose embedded processor and a synthesized application specific processor (ASP). FITS processors reduce code size and energy consumption by tailoring the instruction set to the requirement of a target application. This is achieved by replacing the fixed instruction and register decoding of a general purpose embedded processor with programmable decoders that can achieve ASP performance, low energy consumption, and smaller code size with the fabrication advantages of a mass produced single chip solution. Experimental results show that our synthesized instruction sets result in significant power reduction in the level one instruction cache compared to ARM instructions. The instruction cache is one of the most predominant sources of power dissipation on the processor. For instance, in Intel's StrongARM processor, 27 percent of total chip power loss goes into the instruction cache. For 21 MiBench benchmarks, our simulation results, indicate, on average, a 49.4 percent saving for switching power, a 43.9 percent saving for internal power, a 14.9 percent saving for leakage power, a 46.6 percent saving for total instruction cache power with up to 60.3 percent saving for peak power.

Reducing coding redundancy in LZW

LZW is a widely used text compression algorithm. It has been known for a long time that its flat coding method causes redundancy. In this article, we identify three sources of redundancy: (1) Flat coding does not use the code space fully. (2) LZW considers the entire dictionary, including leaf nodes, for computation of codeword size, where as leaf nodes would not be encoded. (3) LZW assigns index to a node much ahead of the time it would use the node for output. For (1), we present an elegant implementation of an approach known as phase-in binary coding. A characteristic of our formulation is that it incurs virtually no overhead and that it can be applied for integer sequence coding, as well. For (2) and (3), we assign double indices to dictionary nodes to identify nodes which should not be considered for coding. Our method generates some extra code symbols. To reduce the coding cost of these symbols, we use arithmetic coding for the final output. Experimental results are given for several benchmark datasets to compare code size reduction of our methods with some published results.

The implementation and evaluation of dynamic code decompression using DISE

Code compression coupled with dynamic decompression is an important technique for both embedded and general-purpose microprocessors. Postfetch decompression , in which decompression is performed after the compressed instructions have been fetched, allows the instruction cache to store compressed code but requires a highly efficient decompression implementation. We propose implementing postfetch decompression using a new hardware facility called dynamic instruction stream editing (DISE). DISE provides a programmable decoder---similar in structure to those in many IA-32 processors---that is used to add functionality to an application by injecting custom code snippets into its fetched instruction stream. We present a DISE-based implementation of postfetch decompression and show that it naturally supports customized program-specific decompression dictionaries, enables parameterized decompression allowing similar-but-not-identical instruction sequences to share dictionary entries, and uses no decompression-specific hardware. We present extensive experimental results showing the virtue of this approach and evaluating the factors that impact its efficacy. We also present implementation-neutral results that give insight into the characteristics of any postfetch decompression technique. Our experiments not only demonstrate significant reduction in code size (up to 35%) but also significant improvements in performance (up to 20%) and energy (up to 10%).

Dynamic coalescing for 16-bit instructions

In the embedded domain, memory usage and energy consumption are critical constraints.Embedded processors such as the ARM and MIPS provide a 16-bit instruction set, (called Thumb in the case of the ARM family of processors), in addition to the 32-bit instruction set to address these concerns. Using 16-bit instructions one can achieve code size reduction and instruction cache energy savings at the cost of performance. This paper presents a novel approach that enhances the performance of 16-bit Thumb code. We have observed that throughout Thumb code there exist Thumb instruction pairs that are equivalent to a single ARM instruction. We have developed enhancements to the processor microarchitecture and the Thumb instruction set to exploit this property. We enhance the Thumb instruction set by incorporating Augmenting eXtensions (AX). A Thumb instruction pair that can be combined into a single ARM instruction is replaced by an AXThumb instruction pair by the compiler. The AX instruction is coalesced with the immediately following Thumb instruction to generate a single ARM instruction at decode time. The enhanced microarchitecture ensures that coalescing does not introduce pipeline delays or increase cycle time thereby resulting in reduction of both instruction counts and cycle counts. Using AX instructions and coalescing hardware we are also able to support efficient predicated execution in 16-bit mode.

Compiler transformations for effectively exploiting a zero overhead loop buffer

A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequence of instructions that will be executed a specified number of times without incurring any loop overhead. Unlike loop unrolling, a loop buffer can be used to minimize loop overhead without the penalty of increasing code size. In addition, a ZOLB requires relatively little space and power, which are both important considerations for most DSP applications. This paper describes strategies for generating code to effectively use a ZOLB. We have found that many common code improving transformations used by optimizing compiler on conventional architectures can be easily used to (1) allow more loops to be placed in a ZOLB, (2) further reduce loop overhead of the loops placed in a ZOLB, and (3) avoid redundant loading of ZOLB loops. The results given in this paper demonstrate that this architectural feature can often be exploited with substantial improvements in execution time and slight reductions in code size for various signal processing applications.

Static Analysis of OpenMP Directive Nesting Types and Its Application

Because of the rules of dynamic directive nesting and binding, some of the thread context in OpenMP programs can only be totally determined at runtime. However, by compiling time static analysis, nesting type can be partly determined and this information can be passed to other compiling phases to guide later translation and optimizations. Since the binding and nesting may span the procedure boundaries through calls, local and global analyses are not enough. It is the interprocedural analysis that provides the most required ability. By integrating information into traditional interprocedural analysis, the nesting type information of procedures is propagated along call graphs. And later translation and optimization phases can bind this global information with local information inside the procedure to determine the nesting types at compiling time. The results demonstrate that in typical science and engineering workload the nesting type is highly determinable at compiling time, and the application of this information may achieve less runtime overhead and the reduced code size.

Adaptive code unloading for resource-constrained JVMs

Compile-only JVMs for resource-constrained embedded systems have the potential for using device resources more efficiently than interpreter-only systems since compilers can produce significantly higher quality code and code can be stored and reused for future invocations. However, this additional storage requirement for reuse of native code bodies, introduces memory overhead not imposed in interpreter-based systems.In this paper, we present a Java Virtual Machine (JVM) extension for adaptive code unloading that significantly reduces the memory requirements imposed by a compile-only JVM. The extension features an unloader that uses execution behavior to adaptively determine when to unload as well as what code to unload. We implement and empirically identify a set of unloading strategies that enable significant code size reduction (43%-61%). This reduction translates into significant execution time benefits for the benchmarks and JVM configurations that we studied. As such, by using adaptive code unloading, we make compile-only JVMs for embedded devices more feasible.

NDL

Device drivers are difficult to write and error-prone. They are usually written in C, a fairly low-level language with minimal type safety and little support for device semantics. As a result, they have become a major source of instability in operating system code.This paper presents NDL, a language for device drivers. NDL provides high-level abstractions of device resources and constructs tailored to describing common device driver operations. We show that NDL allows for the coding of a semantically correct driver with a code size reduction of more than 50% and a minimal impact on performance.

Link-time optimization of ARM binaries

The overhead in terms of code size, power consumption and execution time caused by the use of precompiled libraries and separate compilation is often unacceptable in the embedded world, where real-time constraints, battery life-time and production costs are of critical importance. In this paper we present our link-time optimizer for the ARM architecture. We discuss how we can deal with the peculiarities of the ARM architecture related to its visible program counter and how the introduced overhead can be eliminated to a large extent. Our link-time optimizer is evaluated in two tool chains. In the Arm Developer Suite tool chain, average code size reductions with 14.6% are achieved, while execution time is reduced with 8.3% on average, and energy consumption with 7.3%. On binaries from the GCC tool chain the average code size reduction is 16.6%, execution time is reduced with 12.3% and the energy consumption with 11.5% on average. Finally, we show how the incorporation of link-time optimization in tool chains may influence library interface design.