Error Detection Codes Research Articles

Theoretical proof for the number of errors that one linear code detects/corrects when linear quasigroups of order 4 are used for coding

In this paper we will analyze one linear code from the theoretical point of view. Namely, the code definition is based on linear quasigroups. In the previous work we classified the quasigroups of order 4 according to their probability of undetected errors. Now, in this paper we will conclude whether the linear quasigroups that are in the same class in this classification obtain equal number of surely detected incorrectly transmitted bits. Also, we will classify the linear quasigroups of order 4 according to the number of errors that the code surely detects when they are used for coding. At the end we will make conclusion which quasigroups of order 4 are overall best for coding having in mind both important parameters for every code for error detection: the number of errors that the code surely detects and the probability of undetected errors.

APPLICATION OF CODING IN DATA TRANSMISSION AND INFORMATION STORAGE

Coding theory plays a crucial role in modern data transmission and information storage systems, ensuring the efficient and reliable handling of digital information. This article explores the fundamental principles of coding theory, focusing on its applications in both data transmission and storage contexts. Beginning with an introduction to encoding and decoding techniques, the article delves into how various coding methods, such as error detection and correction codes, enhance data integrity during transmission. It further examines the implementation of coding in storage devices to safeguard against data loss and corruption.

Two-Dimensional Protection Code for Virtual Page Information in Translation Lookaside Buffers

Severe conditions such as high-energy particle strikes may induce soft errors in on-chip memory, like cache and translation lookaside buffers (TLBs). As the key component of virtual-to-physical address translation, TLB directly affects processor performance. To protect the virtual page information stored in TLB, several studies have introduced error detection or correction codes. However, most schemes proposed for data TLB cannot support the detection of multi-bit upsets, which is reported as a serious issue in modern fault-tolerant processors due to the downscaling of CMOS process technology. In this paper, we propose a new two-dimensional protection technique, called the matrix protection tag (MaP-Tag), to provide stronger error detection and correction capability to TLB virtual page information. Our proposal reorganizes virtual page information into a matrix and employs adjacent check bits and interleaved check bits for error detection. The two-dimensional design offers one-bit error detection, burst multi-bit error detection, and even multi-bit error correction in some cases. The simulation results show that our proposal can detect almost all error patterns when injected with up to eight bit-flips. Furthermore, the technique provides a better error correction rate than conventional single error correction (SEC) codes. The reliability calculation shows that our proposal is powerful in both error detection and correction with affordable storage overhead.

Better-than-classical Grover search via quantum error detection and suppression

We report better-than-classical success probabilities for a complete Grover quantum search algorithm on the largest scale demonstrated to date, of up to five qubits, using two different IBM platforms. This is enabled by error suppression via robust dynamical decoupling. Further improvements arise after the use of measurement error mitigation, but the latter is insufficient by itself for achieving better-than-classical performance. For two qubits, we demonstrate a 99.5% success probability via the use of the [[4, 2, 2]] quantum error-detection (QED) code. This constitutes a demonstration of quantum algorithmic breakeven via QED. Along the way, we introduce algorithmic error tomography (AET), a method that provides a holistic view of the errors accumulated throughout an entire quantum algorithm, filtered via the errors detected by the QED code used to encode the circuit. We demonstrate that AET provides a stringent test of an error model based on a combination of amplitude damping, dephasing, and depolarization.

Protecting expressive circuits with a quantum error detection code

Protecting expressive circuits with a quantum error detection code

Application of Entropy for Modular Code Error Detection in Reliable Distributed Storage Systems

Application of Entropy for Modular Code Error Detection in Reliable Distributed Storage Systems

An optimal channel coding scheme for high-speed data communication

This paper presents a novel channel-coding scheme called Binary to Gray Code Conversion based Error Detection and Correction (BGCC-EDAC) code to correct the maximum number of errors that occur at the receiving end during wireless transmission. The proposed method adds the parity bit using Binary to Gray Code Conversion (BGCC). The decoding algorithm proposed in this paper will not perform the regular Gray-to-Binary code conversion. Instead, a novel decoding algorithm is proposed to detect and correct most of the errors in the message bits. It will require retransmission only if any parity error occurs. The efficiency of the proposed channel code stems from its redundant bit calculation and decoding algorithm. The simulation results using Cadence 90 nm technology show that the proposed BGCC-EDAC code consumes low power, less area, and less propagation delay. Simulation analysis using MATLAB reveals that the proposed BGCC-EDAC outperforms the existing error-correcting codes in terms of BER performance. This makes the proposed BGCC-EDAC code, with a shorter code word length, highly suitable for high-speed, reliable data communications.

Exploring the potential of ChatGPT in assessing L2 writing accuracy for research purposes

This study investigates ChatGPT's potential for measuring linguistic accuracy in second language writing for research purposes. We processed 100 L2 essays across five proficiency levels with ChatGPT-4 and manually coded for precision and recall with regard to ChatGPT's identification of errors. Our findings indicate a strong correlation (ρ = 0.97 using one method and .94 using another method) between ChatGPT's error detection and human coding, although this correlation diminishes with lower proficiency levels. While ChatGPT infrequently misidentifies errors, it often underestimates the total error count. The study also highlights ChatGPT's limitations, such as the issue of consistency, and provides guidelines for future research applications.

Reconfigurable linear feedback shift register for wireless communication and coding

<p>Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.</p>

Escaping Printable Encoded Streams to Embed Out-of-Band Data

In this paper, we propose to exploit the unused configurations of a printable encoding such as Base41, Base45 or Base85 to create a side channel that can store extra data such as error detection or correction codes, integrity verification and authentication information or application defined data. After introducing the encoding of binary octet strings in printable form, we present some case studies that show possible applications of the unused configurations.

Decision Algorithm Based on the Modified Bellman Equation to Deal With EMI-Induced Errors in Hamming-Based Communications

This article presents a decision-making algorithm based on a modified version of the Bellman equation to deal with electromagnetic interference errors in a communication channel inside a harsh electromagnetic reverberant environment. The Bellman equation is a fundamental concept in decision-making problems such as Markov decision processes. Such processes model decision making in situations where the outcomes are partly random and partly controlled by an agent (decision maker). Recent studies have implemented Markov decision processes as a tool for risk assessment in areas such as robotics or aviation. However, so far, no research has been reported that uses the Bellman equation or Markov decision processes to deal with risks related to electromagnetic disturbances. In our study, a wired communication channel that uses non-return-to-zero-level data encoding and Hamming code for error detection and correction is disturbed. First, the packet error rate (PER) is calculated and compared with and without the proposed algorithm for different electromagnetic disturbance frequencies and bit rates. The gain is compared at different PERs when the algorithm's parameters (called rewards) are optimized and when these are set as random. Finally, the influence of the rewards and the maximum number of resends on the algorithm's performance is also studied.

Improving the number of T gates and their spread in integer multipliers on quantum computing

Quantum circuits performing arithmetic operations are critical in quantum computing because of the need for such operations in proven quantum algorithms. Although quantum computers are becoming increasingly resourceful, the number of qubits currently available is still limited. Furthermore, these qubits are heavily affected by internal and external noise. It has been proven that quantum circuits built using Clifford $+T$ gates can be made fault tolerant. However, the use of the $T$ gates comes at a very high cost. If the number of $T$ gates used in a circuit is not optimized, the cost of the circuit will be increased excessively. As a consequence, it is essential to optimize the circuits so that they are as resource efficient as possible and also noise tolerant. This paper presents the design of a circuit to perform the multiplication of two integers. The circuit is built using only Clifford $+T$ gates for compatibility with error detection and correction codes. It outperforms the circuits in the state of the art in terms of $T$ count and $T$ depth.

Block-Wise Computation of Cyclic Redundancy Code Using Factored Toeplitz Matricesin Lieu of Look-Up Table

Cyclic Redundancy Check (CRC) or Cyclic Redundancy Code is a Cyclic Error Detection Code used to preserve the integrity of data in storage and transmission applications. CRC of a stream of message bits is usually calculated block-wise in parallel with the help of a Look-Up Table (LUT) in software or State Space transformation matrix in hardware. Presented here is a novel method and architecture of parallel computation of Cyclic Redundancy Codes without any Look-Up Table for an arbitrary generating polynomial which is programmable at runtime. The method reduces computational complexity and storage requirements by implicitly factorizing the transformation matrix needed to compute the remainder into two simpler Toeplitz matrices. The resulting hardware architecture is suitable for embedded applications.

Fault-tolerant quantum algorithm for dual-threshold image segmentation

The intrinsic high parallelism and entanglement characteristics of quantum computing have made quantum image processing techniques a focus of great interest. One of the most widely used techniques in image processing is segmentation, which in one of their most basic forms can be carried out using thresholding algorithms. In this paper, a fault-tolerant quantum dual-threshold algorithm has been proposed. This algorithm has been built using only Clifford+T gates for compatibility with error detection and correction codes. Because fault-tolerant implementation of T gates has a much higher cost than other quantum gates, our focus has been on reducing the number of these gates. This has allowed adding noise tolerance, computational cost reduction, and fault tolerance to the state-of-the-art dual-threshold segmentation circuits. Since the dual-threshold image segmentation involves the comparison operation, as part of this work we have implemented two full comparator circuits. These circuits optimize the metrics T-count and T-depth with respect to the best circuit comparators currently available in the literature.

Generalized Code-Abiding Countermeasure

The widely used countermeasures against fault attacks are based on spatial, temporal, or information redundancy. This type of solution is very efficient, but it can be very expensive in terms of implementation cost. Thus, trying to propose a secure and efficient countermeasure for a lightweight cipher is a hard challenge, as the goal of a lightweight cipher is to be the lightest possible. This paper considers information redundancy based on parity bit code, with code-abiding transformations of the operations. This error detection code, with the code-abiding notion added, is very efficient against single fault injection and has a small overcost. The solution is tested on the LED lightweight cipher to measure its overhead. Moreover, a bitslice version of the cipher is used with the parity bit code applied to be robust against all the single-word fault injections. The challenge is to adapt the cipher functions in a way in which the parity bit is always considered, but without considering a heavy implementation. The advantage of our solution is that this countermeasure leads to a 100% fault coverage, with a reasonable overhead.

Modified Hamming Codes in Computing Devices Technical Diagnostic Systems

Previously unknown error detection characteristics by types and multiplicities in modified Hamming codes code words are established. The rules for constructing this modification of Hamming codes are described. Detailed characteristic tables of codes with data vectors lengths m = 4...16 are given. The considered code's error detection properties brief analysis is given. The results obtained in the study can be effectively used in the digital computing devices with controllable structures synthesis, as well as in the self-checking concurrent error-detection (CED) circuit synthesis using the Boolean complement method. The modified Hamming codes key property is the impossibility of 100 % double error detection in all code word bits when any single and double errors that occur only in data bits are detected. That is why it is recommended, when synthesizing a CED circuit using the Boolean complement method, to convert only those functions that describe the operating functions of the diagnostic object that will form the modified Hamming code control bits, and to separate the converted and non-convertible outputs into two groups of independent outputs. The experiment results with test combinational circuits presented in the article confirm the effectiveness of their use in the CED circuit synthesis by the Boolean complement method.

Event-Triggered Sensor Scheduling for Remote State Estimation With Error-Detecting Code

This letter addresses the problem of remote state estimation subject to packet dropouts, focusing on the use of an event-triggered sensor scheduler to conserve communication resources. However, packet dropouts introduce significant challenges, as the remote estimator cannot distinguish between packet loss caused by poor channel conditions and the event trigger. To overcome this issue, we propose a novel formulation that incorporates error-detecting codes. We prove that the Gaussian property of the system state, commonly utilized in the literature, does not hold in this scenario. Instead, the system state follows an extended Gaussian mixture model (GMM). We present an exact minimum mean-squared error (MMSE) estimator and an approximate estimator, which significantly reduces algorithm complexity without sacrificing performance. Our simulation results show that the approximate estimator achieves nearly the same performance as the exact estimator while requiring much less computation time. Moreover, the proposed event trigger outperforms existing schedulers in terms of estimation accuracy.

A Reviewing Approach to Analyze the Advancements of Error Detection and Correction Codes in Channel Coding With Emphasis on LPWAN and IoT Systems

A Reviewing Approach to Analyze the Advancements of Error Detection and Correction Codes in Channel Coding With Emphasis on LPWAN and IoT Systems

On the Positional Single Error Correction and Double Error Detection in Racetrack Memories

In the era of non-volatile memories, the racetrack memory is a promising technology to pack hundreds of bits in a magnetic nanowire. A solid-state read head is grown alongside the nanowire to sense individual bits which are pushed across the head by a shifting force. However, the probabilistic nature of this shifting movement inflicts positional errors. Therefore, robust and low-cost error correcting codes are essential for a reliable alternative in on-chip memories and storage applications. Recent works focus on Varshamov-Tenengolts (VT) codes which can correct all single bit insertions and deletions. However, VT codes are incapable of detecting multiple deletions/insertions. Because a positional error corrupts multiple data words, multi-bit positional error detection is critical for racetrack memories. In this article, we propose a novel positional single error correction and double error detection (P-SECDED) code in the context of racetrack memories with a single read head. In particular, we adopt a postamble-based approach where a VT-encoded codeword appends a carefully selected bit-pattern, stored on the racetrack. We rigorously analyze the limitations of the postamble method, and deduce a criterion for postamble selection. We further provide a methodology to optimize this postamble selection in order to correct all single-bit errors and as much of two-bit errors as possible. Finally, we prove that all incurable two-bit errors are successfully detected. To the best of our knowledge, this work is the first attempt to provide P-SECDED fault-tolerance to three-dimensional racetrack memories which cannot afford multiple read heads.

DNA technology for big data storage and error detection solutions: Hamming code vs Cyclic Redundancy Check (CRC)

There is an increasing need for high-capacity, highdensity storage media that can retain data for a long time, due to the exponential development in the capacity of information generated. The durability and high information density of synthetic deoxyribonucleic acid (DNA) make it an attractive and promising medium for data storage. DNA data storage technology is expected to revolutionize data storage in the coming years, replacing various Big Data storage technologies. As a medium that addresses the need for high-latency, immutable information storage, DNA has several potential advantages. One of the key advantages of DNA storage is its extraordinary density. Theoretically, a gram of DNA can encode 455 exabytes, or 2 bits per nucleotide. Unlike other digital storage media, synthetic DNA enables large quantities of data to be stored in a biological medium. This reduces the need for traditional storage media such as hard disks, which consume energy and require materials such as plastic or metals, and also often leads to the generation of electronic waste when they become obsolete or damaged. Additionally, although DNA degrades over thousands of years under non-ideal conditions, it is generally readable. Furthermore, as DNA possesses natural reading and writing enzymes as part of its biological functions, it is expected to remain the standard for data retrieval in the foreseeable future. However, the high error rate poses a significant challenge for DNA-based information coding strategies. Currently, it is impossible to execute DNA strand synthesis, amplification, or sequencing errors-free. In order to utilize synthetic DNA as a storage medium for digital data, specialized systems and solutions for direct error detection and correction must be implemented. The goal of this paper is to introduce DNA storage technology, outline the benefits and added value of this approach, and present an experiment comparing the effectiveness of two error detection and correction codes (Hamming and CRC) used in the DNA data storage strategy.