Code Density Research Articles

DC-Free Four-Ary (2,8) Run-Length Limited Code for Multi-level Recording Channels

A new high efficient DC-free (2,8) run-length limited (RLL) code for four-level optical recording channels is proposed. The proposed code can be represented by a finite state diagram (FSM) with three states and implemented easily. The code rate and density ratio of the code are 5/6 bits/symbols and 2.50 bits/minimum-recorded-mark, respectively. On the basis of the experimental results, the performances of the code are evaluated by using partial-response maximum-likelihood (PRML) technology, which is suitable for detecting multi-level RLL signals. By using four-ary (2,8)RLL modulation and PRML technology, one can increase the recording density 66.7% relative to conventional binary RLL modulation currently used in digital versatile disc (DVD), meanwhile the bit error rate (BER) still be acceptable.

Scalable Image Searching Method based on Orientation Code Density

This paper aims to propose a fast image searching method from environmental observation images even in the presence of scale changes. A new scheme has been proposed for extracting feature areas based on a robust image registration algorithm called Orientation code matching. Extracted areas are stored as template images and utilized in image searching. As the number of template images grows, the searching cost becomes a serious problem. Additionally, changes of viewing positions cause scale change of an image and matching failure. In our scheme, richness in features is important for feature area generation and the entropy is used to evaluate the variety of edge directions which are stable to scale change of the image. This characteristic contributes to limitation of searching area and reduction in calculation costs. Scaling factors are estimated by orientation code density which means the percentage of effective codes in fixed size areas. An estimated scaling factor is applied to matching a scale of template images to one of observation images. Some experiments are performed in order to compare computation time and verify effectiveness of estimated scaling factor using real scenes.

A background comparator calibration technique for flash analog-to-digital converters

This paper presents a background calibration technique for trimming the input-referred offsets of the comparators in a flash analog-to-digital converter (ADC) without interrupting the ADC's normal operation. For a random-chopping comparator, the polarity of its offset is detected by observing the code density of its comparison results. Binary feedback is then used to digitally adjust the comparator's offset so that the offset is minimized. All calibration procedures are performed in the digital domain. The calibration performance is characterized by the converging speed of the feedback loop and the offset fluctuation due to the disturbance of the ADC's input. These two performance indexes of a background-calibrated comparator (BCC) are determined by three parameters: the probabilistic distribution of the ADC's input, the BCC's offset quantized step size, and the threshold of an internal bilateral peak detector. The offset fluctuation of a BCC can be drastically reduced by employing a windowing mechanism. The use of windowed BCCs in a flash ADC can introduce nonmonotonic-threshold (NMT) effects which include an increase in calibration settling time and an increase in /spl sigma/(V/sub OS/). The use of uncorrelated random chopping for neighboring BCCs can ensure the validity of offset detection and mitigate the NMT effects.

Properties of Numeric Codes for the Scheme of Random Subspaces RSC

Properties of coarse coding obtained by using the random subspace coding (RSC) scheme with random hyperrectangular receptive fields are considered. Characteristics of codes are provided such as the dimensionality of receptive fields, code density at various points of the input space, code overlapping, and others. The results of theoretical analysis are illustrated by experiments with high-dimensional codes.

A scalable instruction buffer and align unit for xDSPcore

Increasing mask costs and decreasing feature sizes together with productivity demand have led to the trend of platform design. Software programmable embedded cores are used to provide the necessary flexibility in integrated systems. Facing increasing system complexity, single-issue digital signal processors (DSPs) have been replaced by cores providing the execution of several instructions in parallel. The most common programming model for multi-issue DSP core architectures is Very Long Instruction Word (VLIW) which is based on static scheduling, and enables minimization of the worst case execution time and reduces core complexity. The drawback of traditional VLIW is poor code density, which leads to high program memory requirements and, therefore, requires a large silicon area of the DSP subsystem. To overcome this problem without limiting the core performance, a scalable long instruction word (xLIW) is introduced. A special align unit is used for implementing the xLIW program memory interface. In this paper, the align unit and its main architectural feature, a scalable instruction buffer, is introduced in detail. xLIW is part of a project for a parameterized DSP core.

Flash A/D converter based on Vernier caliper design

This study presents a method for the design of an N−bit flash analog-to-digital (A/D) converter which employs the main-scale Vernier-scale characteristics of a Vernier caliper. The proposed design is similar to a half flash design where the main half flash A/D converts the N/2 most significant bits (MSBs) from comparisons of the input signal with all of the quantization thresholds, while the Vernier (scale) half flash A/D converts the N/2 least significant bits (LSBs). Relative to previous designs, this architecture reduces the number of comparators while maintaining high resolution and speed. A 12 bit prototype is tested by code density analysis, showing integral nonlinearity within ±1.0 LSB and differential nonlinearity within ±0.5 LSB. Resolution is strongly dependent on precision current sources and resistor ladders, and analog switch ON resistance must be far less than resistor ladder resistance. Such requirements, however, are easily met with very-large-scale integrated technologies, making the Vernier flash A/D converter a good candidate for high-performance, low-cost, low-power flash A/D converter designs.

Scalable vector processors for embedded systems

For embedded applications with data-level parallelism, a vector processor offers high performance at low power consumption and low design complexity. Unlike superscalar and VLIW designs, a vector processor is scalable and can optimally match specific application requirements.To demonstrate that vector architectures meet the requirements of embedded media processing, we evaluate the Vector IRAM, or VIRAM (pronounced "V-IRAM"), architecture developed at UC Berkeley, using benchmarks from the Embedded Microprocessor Benchmark Consortium (EEMBC). Our evaluation covers all three components of the VIRAM architecture: the instruction set, the vectorizing compiler, and the processor microarchitecture. We show that a compiler can vectorize embedded tasks automatically without compromising code density. We also describe a prototype vector processor that outperforms high-end superscalar and VLIW designs by 1.5x to 100x for media tasks, without compromising power consumption. Finally, we demonstrate that clustering and modular design techniques let a vector processor scale to tens of arithmetic data paths before wide instruction-issue capabilities become necessary.

AE32000B: a Fully Synthesizable 32-Bit Embedded Microprocessor Core

In this paper, we introduce a fully synthesizable 32-bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35-·m library and a 0.18-·m library. With the 0.35-·m library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18-·m library.

VISTA

Software designers face many challenges when developing applications for embedded systems. A major challenge is meeting the conflicting constraints of speed, code density, and power consumption. Traditional optimizing compiler technology is usually of little help in addressing this challenge. To meet speed, power, and size constraints, application developers typically resort to hand-coded assembly language. The results are software systems that are not portable, less robust, and more costly to develop and maintain. This paper describes a new code improvement paradigm implemented in a system called vista that can help achieve the cost/performance trade-offs that embedded applications demand. Unlike traditional compilation systems where the smallest unit of compilation is typically a function and the programmer has no control over the code improvement process other than what types of code improvements to perform, the vista system opens the code improvement process and gives the application programmer, when necessary, the ability to finely control it. In particular, vista allows the application developer to (1) direct the order and scope in which the code improvement phases are applied, (2) manually specify code transformations, (3) undo previously applied transformations, and (4) view the low-level program representation graphically. vista can be used by embedded systems developers to produce applications, by compiler writers to prototype and debug new low-level code transformations, and by instructors to illustrate code transformations (e.g., in a compilers course).

Numerical simulations of ultrashort laser pulse ablation and plasma expansion in ambient air

Using a self-consistent one-dimensional Cartesian Lagrangian fluid code, we modeled the ultrashort laser pulse ablation of solid aluminum and the subsequent plasma expansion in ambient air. A laser fluence of approximately 10 J/cm 2 is considered. The code axial plasma temperature and density are strongly inhomogeneous and the maximum radiation emission generally occurs in the front of the plasma. The code average plasma temperature is in good agreement with the experiments for all times, while larger discrepancies with respect to the experiments are observed at late times for the plasma density. Experimental results are in reasonable agreement with the condition of thermodynamic equilibrium, which is an important assumption in the model.

The efficiency of methods for measuring A/D converter linearity

In this paper, the efficiency of three methods commonly used to measure the linearity characteristics of precision Nyquist-rate analog-to-digital (A/D) converters is evaluated. The efficiency of each method, which is determined by the time required to obtain linearity estimates at a specified level of accuracy, is compared to the maximum efficiency that is theoretically achievable, as given by the Cramer-Rao bound. Simulation results are presented for two open-loop measurement methods, the tally and weight method and the code density method, demonstrating that the code density method obtains an efficiency close to the theoretical optimum over a wide range of measurement times and converter noise levels, whereas the tally and weight method falls short of the optimum for converters with noise levels exceeding 1/4 LSB. The efficiency of the servo loop method, a common closed-loop method for measuring linearity, is similarly evaluated, and is found to fall short of the maximum efficiency that is theoretically achievable in the closed-loop configuration. A modified closed-loop measurement method is described that obtains an efficiency close to the theoretical optimum through the use of maximum-likelihood estimation.

A high-resolution time interpolator based on a delay locked loop and an RC delay line

An architecture for a time interpolation circuit with an rms error of /spl sim/25 ps has been developed in a 0.7-/spl mu/m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology.

Paged Absolute Addressing Mode Optimizations for Embedded Digital Signal Processors Using Post-pass Data-flow Analysis

We address the problem of code generation for embedded DSP systems. In such systems, it is typical for one or more digital signal processors (DSPs), program memory, and custom circuitry to be integrated onto a single IC. Consequently, the amount of silicon area that is dedicated to program memory is limited, so the embedded software must be sufficiently dense. Additionally, this software must be written so as to meet various high-performance constraints, which may include hard real-time constraints. Unfortunately, existing compiler technology is unable to generate dense, high-performance code for DSPs since it does not provide adequate support for the specialized architectural features of DSPs. These specialized features not only allow for the fast execution of common DSP operations, but they also allow for the generation of dense assembly code that specifies these operations. Thus, system designers often hand-program the embedded software in assembly, which is a very time-consuming task. In this paper, we focus on providing compiler support for one particular specialized architectural feature, namely the paged absolute addressing mode --- this feature is found in two commercial DSPs, the Texas Instruments' TMS320C25 and TMS320C50 fixed-point DSPs; however, it may also be featured in application-specific processors (ASIPs). We present some machine-dependent code optimizations that improve code density by exploiting this architectural feature. Experimental results demonstrate that for a set of typical DSP benchmarks, some of our optimizations reduce overall code size and data memory consumption by an average of 5.0% and 16.0%, respectively. Our experimental vehicle throughout this research is the TMS320C25.

Signal to noise ratio scaling and density limit estimates in longitudinal magnetic recording

A simplified general expression is given for SNR for digital magnetic recording for transition noise dominant systems. High density media are assumed in which the transition parameter scales with the in-plane grain diameter. At a fixed normalized code density, the SNR varies as the square of the bit spacing times the read track width divided by the grain diameter cubed. This scaling law is shown to be quite general and useful for error rate analysis. Density optimization argues for track width narrowing rather than bit length reduction, limited by edge track considerations. Utilization of Arrhenius thermal signal decay yields limiting density estimates, neglecting electronics noise, in the range 50-100 Gbit/in/sup 2/ increasing with an increase in medium thickness/grain diameter ratio.

The impact of Mpact 2

Mpact media processors enable powerful, flexible and cost-effective multimedia in a PC. A single chip replaces today's multiboard, multichip solutions for graphics, video, audio, and communications. The architecture combines a high-bandwidth RAMBUS memory, VLIW/SIMD (single instruction, multiple data) processing, standard buses, and software programmability for the cost of a modern graphics chip. Mpact architecture uses a modified VLIW style with two RISC-like instructions per VLIW. The instructions are either executed sequentially or concurrently based on a tag in the VLIW. Classical VLIW suffers from low code density due to unused instruction fields, but the Mpact modified VLIW has the same code density as RISC instructions. Additionally, the SIMD instructions improve code density by increasing the work done by each instruction. An 8 byte word size was chosen to balance vector and scalar performance and also to balance data and instruction bandwidth. A 9 bit byte was chosen to represent color-component differences in one byte and to represent 18 bit color or 18 bit audio samples in two bytes. Hardware-dithered rounding of quantization noise allows most audio to be processed in two byte precision. The maximal multiplier precision of 24/spl times/24 was chosen for audio requirements. The article reviews the first-generation Mpact media processor and then describes the multimedia performance goals and architecture of Chromatic's second-generation media processor architecture. It then presents newer modules of the architecture in more detail.

The use of linear models in A/D converter testing

This paper demonstrates how a linear modeling technique can be applied to three common methods for testing analog-to-digital converters (ADC's)-the servo-loop method, the tally-and-weight method, and the code density method-to improve their efficiency and accuracy. In order to compare the accuracy of the test procedures that incorporate the linear modeling technique with the corresponding procedures that do not, confidence intervals are derived for the integral and differential nonlinearity (INL and DNL) estimates obtained in both cases. Since the linear model may itself introduce some error in the estimates, the accuracy of the model must be determined in order to make the comparisons meaningful. This is accomplished by using a nested experimental design to determine how much of the variance in the transition levels is accounted for by the model.

Analysis of distortion in A/D converters by time-domain and code-density techniques

Two new methods for measuring the total harmonic distortion of an A/D converter are described. One is based on time-domain analysis, the other on modified code density analysis. Experiments show that these methods give results comparable to the ones provided by FFT analysis. It is then shown, by both experiments on a flash converter and computer simulations, that the conventional code density analysis does not provide accurate signal-to-noise-plus-distortion ratio (SNDR) estimates at the highest frequencies, while the proposed methods do.

Interfering contexts of regulatory sequence elements.

Although one would normally expect a given regulatory element to perform best when it fully matches its consensus sequence, this is generally far from being the case. Usually, almost none of the actual sites fits the consensus exactly, and some of those that do fit do not perform well. The main reason for that is the very nature of the sequences and the messages (codes) they contain. Normally, any given stretch of the sequence with one or another regulatory site not only carries this regulatory message, but several more messages of various types as well. These messages overlap with the regulatory element in such a way that the letter (base) which actually appears in any given sequence position simultaneously belongs to one or more additional codes. Apart from numerous individual codes (sequence patterns) specific for a given species or gene, there are many different general (universal) sequence codes all interacting with one another. These are the classical triplet code, DNA shape code, chromatin code, gene splicing code, modulation code and many more, including those that have not yet been discovered. Examples of overlapping of different codes and their interaction are discussed, as well as the role of degeneracy of the codes and the sequence complexity as a function of code density.

SH3: high code density, low power

Hitachi's SH series microprocessors feature 32-bit RISC architecture with a 16-bit, fixed-length instruction set. We describe SH3, a pipelined implementation of the SH architecture with on-chip cache, MMU, and software-programmable power management. Its higher code density and corresponding improvement in instruction-fetch latency lead to higher performance than typical 32-bit RISC architectures achieve. These features, small die size, and low power consumption make SH3 an ideal microprocessor for portable computing systems or multimedia systems.

An improved code density test for the dynamic characterization of flash A/D converters

An improved code density test for flash A/D converters is proposed, revealing some dynamic phenomena (e.g., missing codes) hidden by the conventional approach. Formulas are reported for obtaining, from code density, effective noise estimates fully consistent with those provided by waveform analysis. Finally, it is shown that the variance of noise estimates obtained by time-domain analysis may be unacceptably large if the observation window is not properly chosen.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>