Code Density Research Articles

Effects of experimental ulcerative colitis on the P2X 7 receptor of the enteric neurons of rat distal colon

Background/Aims: In the digestive tract the ulcerative colitis and Crohn´s disease presenting as pathophysiological bowel necrosis. This project aimed to study the P2X7 receptor and chemical coding of the distal colon myenteric plexus of the rats subjected to ulcerative colitis experimental. The chemical code, area and neuronal density were analyzed in the enteric neurons immunoreactive to nitric oxide synthase (NOS), choline acetyl transferase (ChAT), calbindin, calretinin and the P2X7 receptor.

Using LDPC coding and AMC to mitigate received power imbalance in carrier aggregation communication system

When a carrier aggregation communication system suffers from receiving power imbalance (RPI) in its antenna array due to design flaw, operator's negligence etc. the system performance may be degraded to an unacceptable level. Specifically in this paper a carrier aggregation communication system with two carrier links while one link suffers RPI is considered, various modulation techniques, such as QPSK, 16 QAM and 64 QAM and/or coding schemes, Convolution Code (CC) and Low Density Parity Check Code (LDPC) are implemented in the system performance simulation to investigate the system behavior when it has the design request to maintain the same system performance in each link when the RPI has values of 7 or 10dB.

DisIRer

This article proposes an alternative yet effective way of constructing a multiplatform binary translator, by converting a retargetable compiler into a binary translator. The rationale is that a retargetable compiler usually parses source programs into an Intermediate Representation (IR), and then translates IR into object code of different targets after performing analysis and optimizations. Specifically, the mechanism of code generation for multiple platforms from IR is already in place, and the missing link of building a multiplatform binary translator is a tool to transform binary programs back into IR. In order to fill in this missing link, this article presents a tool, called thedisIRer. Just as a translator from machine language to assembly language is called a disassembler, a tool that translates executable binary programs to IR is called here a disIRer. The unique feature of this approach is that the retargetability of the binary translator is inherited directly from the retargetable compiler. A prototype multiplatform binary translator has been implemented upon GCC (the GNU Compiler Collection). DisIRer first converts binary programs back into GCC IR (Intermediate Representation), and afterward the GCC backend translates the IR to target binary programs of specified platforms. Experimental results show that x86 binary programs can be translated by this technique into ARM and Alpha binaries with reasonable code density and quality.

The Maximum-Likelihood Noise Magnitude Estimation in ADC Linearity Measurements

Analog-to-digital-converter (ADC) linearity measurement is recently featured as the estimation of the code-transition (CT) level. This paper carries out the maximum-likelihood (ML) estimation directly to the output sequence for a ramp input signal. The derived ML equations determine not only the CT level but also its standard deviation, i.e., noise magnitude. Our method does not necessarily assume a Gaussian noise distribution. Rather, we introduce a logistic distribution that makes ML equations simple. One solution of the ML equations for logistic noise verifies the code density method to be optimal. Another solution provides an explicit formula of the noise variance. The formula is practically important because it denotes some kind of malfunctions of the ADC that the code density method cannot inherently detect.

EXPLOITING CHAOTIC DYNAMICS FOR A-D CONVERTER TESTING

In this paper we discuss the possible use of chaotic signals for testing Analog-to-Digital Converters (ADCs), with particular reference to the well-known Code Density Test (CDT, also called Histogram Test). In detail, we discuss the implementation of a chaos-based discrete-time noise generator circuit, providing the theoretical analysis of its statistical characterization. The implementation of the chaos-based device is discussed with reference to a generic hardware architecture, taking into account the nonidealities introduced by the presence of noise and the variability of the circuit parameters. Based on this device, we propose a method for generating noisy samples that are distributed, over a target subinterval of the circuit output range, according to a probability density function (pdf) that can be made arbitrarily close to the ideal uniform pdf, in exchange for an acceptable reduction of the uniform-distributed samples generation rate. Theoretical results, also supported by two experiments, confirm the reliability of the proposed solution, showing that chaotic systems can represent an alternative with respect to traditional methods for the generation of signals to be used in the Code Density Test of ADCs.

Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

This work presents a static method implemented in a compiler for extracting high instruction level parallelism for the 32-bit QueueCore, a queue computation-based processor. The instructions of a queue processor implicitly read and write their operands, making instructions short and the programs free of false dependencies. This characteristic allows the exploitation of maximum parallelism and improves code density. Compiling for the QueueCore requires a new approach since the concept of registers disappears. We propose a new efficient code generation algorithm for the QueueCore. For a set of numerical benchmark programs, our compiler extracts more parallelism than the optimizing compiler for an RISC machine by a factor of 1.38. Through the use of QueueCore's reduced instruction set, we are able to generate 20% and 26% denser code than two embedded RISC processors.

New Space–Time Code Constructions for Two-User Multiple Access Channels

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper addresses the problem of constructing multiuser multiple-input multiple-output (MU-MIMO) codes for two users. The users are assumed to be equipped with <formula formulatype="inline"><tex Notation="TeX">$n_{t}$</tex> </formula> transmit antennas, and there are <formula formulatype="inline"> <tex Notation="TeX">$n_{r}$</tex></formula> antennas available at the receiving end. A general scheme is proposed and shown to achieve the optimal diversity-multiplexing gain tradeoff (DMT). Moreover, an explicit construction for the special case of <formula formulatype="inline"><tex Notation="TeX">$n_{t}=2$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">$n_{r}=2$</tex></formula> is given, based on the optimization of the code shape and density. All the proposed constructions are based on cyclic division algebras and their orders and take advantage of the multi-block structure. Computer simulations show that both the proposed schemes yield codes with excellent performance improving upon the best previously known codes. Finally, it is shown that the previously proposed design criteria for DMT optimal MU-MIMO codes are sufficient but in general too strict and impossible to fulfill. Relaxed alternative design criteria are then proposed and shown to be still sufficient for achieving the multiple-access channel diversity-multiplexing tradeoff. </para>

Instruction Fusion Technology for the MIPS

As a typical representative of RISC architecture,MIPS has the problem of low code density and ineffective utilization of instruction fields,making procedure volume expansion.The authors made some extensions to the existing MIPS Instruction Set,called exMIPS ISA.The authors propose an instruction fusion technology for the MIPS architecture.The pre-fetched instructions was converted into exMIPS ISA,and multiple sequential instructions was compressed and merged into a single instruction when meeting the fusion-condition.A fused instruction′s execution is equivalent to multiple instructions running at the same time,and will gain extra CPU performance.The process of instruction fusion also enhances the effective utilization of the instruction fields and improves code density.Experimental results from SimpleScalar simulation platform show that great improvement can be achieved.

Architecture Design of a Variable Length Instruction Set VLIW DSP

The cost of the central register file and the size of the program code limit the scalability of very long instruction word (VLIW) processors with increasing numbers of functional units. This paper presents the architectural design of a six-way VLIW digital signal processor (DSP) with clustered register files. The architecture uses a variable length instruction set and supports dynamic instruction dispatching. The one-level memory system architecture of the processor includes 16-KB instruction and data caches and 16-KB instruction and data on-chip RAM. A compiler based on the Open64 was developed for the system. Evaluations show that the processor is suitable for high performance applications with a high code density and small program code size.

A Novel instruction stream buffer for VLIW architectures

The instruction compression mechanism used to solve the drawbacks of traditional very long instruction word (VLIW) architectures often leads to poor code density in the instruction cache, which causes the irregular lengths of long instructions to cross the different cache line. These split long instructions cannot be fetched simultaneously, which creates a bottleneck for VLIW architectures. This paper proposes a buffing mechanism which can slide the split long instruction as a continuous form to offer better efficiency in instruction fetching. This approach helps maintain the behaviors of the software pipeline technology, which schedules iterative instructions to enhance the performance of streaming processing for VLIW architectures. In the proposed mechanism, the instruction stream buffer stores the repeat block completely and suspends as far as possible the cache access to reduce access time. The advantages of repeatedly issuing instructions in the instruction buffer and preventing split long instructions, can substantially improve the performance in fetching instructions. Simulation results show that the mechanism is efficient at the instruction level for the basic DSP/IMG library by improving performance by 35% on average.

Pseudorandom Stimuli Generation for Testing Time-to-Digital Converters on an FPGA

This paper presents a pulse generator circuit that produces a stream of pulses at pseudorandom time intervals. The proposed circuit may serve as a stimulus generator for code density testing of time-to-digital converters (TDCs). The functional behavior of the circuit was first investigated with a software model coded in C ++. The software simulation showed that the interpulse intervals only uniformly cover their domain at a given resolution if the greatest common divisor between the intervals and the observation window is 1 with respect to a common reference clock. In a second step, the circuit was implemented in hardware using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) and tested on a Xilinx Spartan-3 field-programmable gate array (FPGA) platform. The pulse density histograms obtained from the software and hardware test cases show pulse distributions with nonlinearity values within one least significant bit (LSB). In the end, the circuit was used as a stimulus generator for code density testing of a TDC circuit on an FPGA.

Code Compression with Split Echo Instructions

Code density is often a critical issue in embedded computers, since the memory size of embedded systems is strictly limited. Echo instructions have been proposed as a method for reducing code size. This paper presents a new type of echo instruction, split echo, and evaluates an implementation of both split echo and traditional echo instructions on a MIPS R3000 based processor. Evaluation results show that memory requirement is reduced by 12% on average with small additional hardware cost.

Association between Residential Proximity to PERC Dry Cleaning Establishments and Kidney Cancer in New York City

Perchloroethylene (PERC) is commonly used as a dry cleaning solvent and is believed to be a human carcinogen, with occupational exposure resulting in elevated rates of kidney cancer. Living near a dry cleaning facility using PERC has been demonstrated to increase the risk of PERC exposure throughout the building where the dry cleaning is conducted, and in nearby buildings. We designed this study to test the hypothesis that living in an area where there are many PERC dry cleaners increases PERC exposure and the risk of kidney cancer. We matched the diagnosis of kidney cancer from hospitalization discharge data in New York City for the years 1994–2004 by zip code of patient residence to the zip code density of dry cleaners using PERC, as a surrogate for residential exposure. We controlled for age, race, gender, and median household income. We found a significant association between the density of PERC dry cleaning establishments and the rate of hospital discharges that include a diagnosis of kidney cancer among persons 45 years of age and older living in New York City. The rate ratio increased by 10 to 27% for the populations in zip codes with higher density of PERC dry cleaners. Because our exposure assessment is inexact, we are likely underestimating the real association between exposure to PERC and rates of kidney cancer. Our results support the hypothesis that living near a dry cleaning facility using PERC increases the risk of PERC exposure and of developing kidney cancer. To our knowledge, this study is the first to demonstrate an association between residential PERC exposure and cancer risk.

Efficient Code Compression for Embedded Processors

Code density is of increasing concern in embedded system design since it reduces the need for the scarce resource memory and also implicitly improves further important design parameters like power consumption and performance. In this paper we introduce a novel, hardware-supported approach. Besides the code, also the lookup tables (LUTs) are compressed, that can become significant in size if the application is large and/or high compression is desired. Our scheme optimizes the number and size of generated LUTs to improve the compression ratio. To show the efficiency of our approach, we apply it to two compression schemes: ldquodictionary-basedrdquo and ldquostatisticalrdquo. We achieve an average compression ratio of 48% (already including the overhead of the LUTs). Thereby, our scheme is orthogonal to approaches that take particularities of a certain instruction set architecture into account. We have conducted evaluations using a representative set of applications and have applied it to three major embedded processor architectures, namely ARM, MIPS, and PowerPC.

Compiling for Reduced Bit-Width Queue Processors

Embedded systems are characterized by the requirement of demanding small memory footprint code. A popular architectural modification to improve code density in RISC embedded processors is to use a ...

Dictionary-based program compression on customizable processor architectures

The size of the program code has become a critical design constraint in embedded systems, especially in handheld devices. Large program codes require large memories, which increase the size and cost of the chip. In addition, the power consumption is increased due to higher memory I/O bandwidth. Program compression is one of the most often used methods to reduce the size of the program code. In this paper, dictionary-based program compression is evaluated on a customizable processor architecture with parallel resources. In addition to code density, the effectiveness of the method is evaluated in terms of area and power consumption. Furthermore, a mechanism is proposed to maintain the programmability after compression. Up to 77% reduction in area and 73% reduction in power consumption of the program memory and the associated control logic were obtained.

Design of Vector Register Architecture in DSP Processor for Efficient Multimedia Processing

In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrixvector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.

Creating protein models from electron-density maps using particle-filtering methods

One bottleneck in high-throughput protein crystallography is interpreting an electron-density map, that is, fitting a molecular model to the 3D picture crystallography produces. Previously, we developed ACMI (Automatic Crystallographic Map Interpreter), an algorithm that uses a probabilistic model to infer an accurate protein backbone layout. Here, we use a sampling method known as particle filtering to produce a set of all-atom protein models. We use the output of ACMI to guide the particle filter's sampling, producing an accurate, physically feasible set of structures. We test our algorithm on 10 poor-quality experimental density maps. We show that particle filtering produces accurate all-atom models, resulting in fewer chains, lower sidechain RMS error and reduced R factor, compared to simply placing the best-matching sidechains on ACMI's trace. We show that our approach produces a more accurate model than three leading methods--Textal, Resolve and ARP/WARP--in terms of main chain completeness, sidechain identification and crystallographic R factor. Source code and experimental density maps available at http://ftp.cs.wisc.edu/machine-learning/shavlik-group/programs/acmi/

Teaching Computer Organization and Architecture Using Simulation and FPGA Applications

This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemented to write assembly programs in this teaching tool. In addition to the micro- operation simulation, the complete configuration can be run on Xilinx Spartan-3 FPGA board. Such implementation offers good code density, easy customization, easily developed software, small area, and high performance at low cost.

Parallelizing load/stores on dual-bank memory embedded processors

Many modern embedded processors such as DSPs support partitioned memory banks (also called X--Y memory or dual-bank memory) along with parallel load/store instructions to achieve higher code density and performance. In order to effectively utilize the parallel load/store instructions, the compiler must partition the memory-resident values and assign them to X or Y bank. This paper gives a postregister allocation solution to merge the generated load/store instructions into their parallel counterparts. Simultaneously, our framework performs allocation of values to X or Y memory banks. We first remove as many load/stores and register--register moves as possible through an excellent iterated coalescing based register allocator by Appel and George [1996]. We then attempt to parallelize the generated load/stores using a multipass approach. The basic phase of our approach attempts the merger of load/stores without duplication and web splitting. We model this problem as a graph-coloring problem in which each value is colored as either X or Y. We then construct a motion scheduling graph (MSG), based on the range of motion for each load/store instruction. MSG reflects potential instructions that could be merged. We propose a notion of pseudofixed boundaries so that the load/store movement is less affected by register dependencies. We prove that the coloring problem for MSG is NP-complete and solve it with two different heuristic algorithms with different complexity. We then propose a two-level iterative process to attempt instruction duplication, variable duplication, web splitting, and local conflict elimination to effectively merge the remaining load/stores. Finally, we clean up some multiple-aliased load/stores. To improve the performance, we combine profiling information with each stage coupled with some modifications to the algorithm. We show that our framework results in parallelization of a large number of load/stores without much growth in data and code segments. The average speedup for our optimization pass reaches roughly 13% if no profile information is available and 17% with profile information. The average code and data segment growth is controlled within 13%.