Code Density Research Articles

Darwin3: a large-scale neuromorphic chip with a novel ISA and on-chip learning.

Spiking neural networks (SNNs) are gaining increasing attention for their biological plausibility and potential for improved computational efficiency. To match the high spatial-temporal dynamics in SNNs, neuromorphic chips are highly desired to execute SNNs in hardware-based neuron and synapse circuits directly. This paper presents a large-scale neuromorphic chip named Darwin3 with a novel instruction set architecture, which comprises 10 primary instructions and a few extended instructions. It supports flexible neuron model programming and local learning rule designs. The Darwin3 chip architecture is designed in a mesh of computing nodes with an innovative routing algorithm. We used a compression mechanism to represent synaptic connections, significantly reducing memory usage. The Darwin3 chip supports up to 2.35 million neurons, making it the largest of its kind on the neuron scale. The experimental results showed that the code density was improved by up to 28.3× in Darwin3, and that the neuron core fan-in and fan-out were improved by up to 4096× and 3072× by connection compression compared to the physical memory depth. Our Darwin3 chip also provided memory saving between 6.8× and 200.8× when mapping convolutional spiking neural networks onto the chip, demonstrating state-of-the-art performance in accuracy and latency compared to other neuromorphic chips.

Underwater Single-Photon Lidar Equipped with High-Sampling-Rate Multi-Channel Data Acquisition System

Lidar has emerged as an important technology for the high-precision three-dimensional remote sensing of the ocean. While oceanic lidar has been widely deployed on various platforms, its underwater deployment is relatively limited, despite its significance in deep-sea exploration and obstacle avoidance for underwater platforms. Underwater lidar systems must meet stringent requirements for high performance, miniaturization, and high integration. Single-photon lidar, by elevating the detection sensitivity to the single-photon level, enables high-performance detection under the condition of a low-pulse-energy laser and a small-aperture telescope, making it a stronger candidate for underwater lidar applications. However, this imposes demanding requirements for the data acquisition system utilized in single-photon lidar systems. In this work, a self-developed multi-channel acquisition system (MCAS) with a high-resolution and real-time histogram statistics capability was developed. By utilizing field-programmable gate array (FPGA) technology, a method that combines coarse counters with multi-phase clock interpolation achieved an impressive resolution of 0.5 ns and enabled a time of flight duration of 1.5 μs. To address counting instability, a dual-counter structure was adopted in the coarse counter, and real-time histogram statistics were achieved in the data acquisition system through a state machine. Furthermore, the non-uniform phase shift of the clock was analyzed, and a correction algorithm based on code density statistics was proposed to mitigate the periodic modulation of the backscattered signal, with the effectiveness of the algorithm demonstrated through experimental results. The robustness and stability of the MCAS were validated through an underwater experiment. Ultimately, the development of this compact acquisition system enables the implementation of underwater single-photon lidar systems, which will play a crucial role in underwater target imaging, obstacle avoidance in underwater platforms, and deep-sea marine environment monitoring.

Tapped delay line for compact time-to-digital converter on UltraScale FPGA and its coding method

The time-to-digital converter (TDC) is the primary instrument for measuring time intervals. A common solution for FPGA-based TDCs is to construct a tapped delay line (TDL) for time interpolation to produce a sub-clock time resolution. The jitter and quantization, granularity and uniformity of the delay cells, and so on in TDL, determine the achievable TDC time resolution and linearity. To achieve higher linearity, a TDL and its encoding method for compact TDC on the UltraScale FPGA is proposed in this paper. A dual-sampling method with TDL is adopted, which improves precision and efficiency by directly encoding the state of the delay line, allowing further subdivision of the delay unit in combination with wave union. The bin width of the TDL obtained based on our method is measured here using the code density calibration method and draw the integral nonlinearity and differential nonlinearity. Based on the chain structure and encoding method proposed in this article, the TDL and encoding layout have been optimized to achieve a more compatible UltraScale FPGA and can also be further applied to multi-channel TDC.

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

Performance Evaluation and Comparison Between LDPC and Turbo Coded MC-CDMA

This work presents a comparison between the Convolutional Encoding CE, Parallel Turbo code and Low density Parity Check (LDPC) coding schemes with a MultiUser Single Output MUSO Multi-Carrier Code Division Multiple Access (MC-CDMA) system over multipath fading channels. The decoding technique used in the simulation was iterative decoding since it gives maximum efficiency at higher iterations. Modulation schemes used is Quadrature Amplitude Modulation QAM. An 8 pilot carrier wereused to compensate channel effect with Least Square Estimation method. The channel model used is Long Term Evolution (LTE) channel with Technical Specification TS 25.101v2.10 and 5 MHz bandwidth bandwidth including the channels of indoor to outdoor/ pedestrian channel and Vehicular channel. The results showed that the performance of the proposed system was better when the LDPC was used as a coding technique

High-Capacity Double-Sided Square-Mesh-Type Chipless RFID Tags

This paper presents a novel methodology for designing high-capacity frequency domain chipless RFID tags based on the backscattering principle. The tag consists of multiple square open-loop resonators loaded with a varying number of square metallic patches to form a mesh structure. Thus, in contrast to conventional designs, the overall physical size of each resonator remains fixed and does not change with respect to its operating resonant frequency. The RCS response of the proposed tag can be easily manipulated by varying the loading factor of each resonator. The tag size is further miniaturized by placing resonators on both sides of the substrate used. The tag configuration with resonators arranged in the form of a single row (4 × 1) printed on both sides of the substrate is finally chosen for maximum robustness and efficiency. The frequency shift coding (FSC) technique is used to encode more than one bit per resonator by using segments within sub-bands. The proposed tag encodes 16-bit data in a frequency band from 5.9 to 10.5 GHz and has a very high code density of 23.51 bits/cm2 and a spectral efficiency of 3.47 bits/GHz. The design methodology is novel and leads to a very efficient chipless RFID tag that can be used in a variety of high-data-capacity applications.

A Semi-Octagonal 40-Bit High Capacity Chipless RFID Tag for Future Product Identification

This paper presents a unique geometry of a chipless radio frequency identification (RFID) tag for encoding a large number of bits in a very small form factor. The tag geometry consists of semi-octagonal copper strips, sequentially laid on a single side of an ultra-thin substrate. A unique and robust encoding mechanism for the tag identification (ID) is proposed. The operating frequency spectrum of the tag ranges from 3.1 to 10.5 GHz. The tag is compact, having an overall size of 14.5 × 28 mm2. The proposed tag exhibits very high code density of 9.85 bits/cm2 and spectral efficiency of 5.4 bits/GHz. The unique geometric configuration of the proposed tag allows it to encode up to 40 bits of data as an RCS signature. This chipless RFID tag seems to be a potential candidate for a wide range of modern RFID applications.

Построение планов выполнения программ с максимальной плотностью кода на фиксированном наборе параллельных вычислителей

Построение планов выполнения программ с максимальной плотностью кода на фиксированном наборе параллельных вычислителей

Computational complexity when constructing rational plans for program execution in a given field of parallel computers

Objectives. The construction of rational plans (schedules) for parallel program execution (PPE) represents a challenging problem due to its ambiguity. The aim of this work is to create methods for developing such plans and specialized software for implementing these methods, which are based on the internal properties of algorithms, primarily on the property of internal (hidden) parallelism.Methods. The main method for developing PPE plans was the construction, analysis, and purposeful transformation of the stacked-parallel form (SPF) of information graphs of algorithms (IGA). The SPF was transformed by transferring operators from tier to tier of the SPF (this event was taken as an elementary step in determining the computational complexity of scenario execution). As a transformation tool, a method for developing transformation scenarios in the scripting programming language Lua was used. Scenarios were created by a heuristic approach using a set of Application Programming Interface (API) functions of the developed software system. These functions formed the basis for a comprehensive study of the parameters of the IGA and its SPF representation for the subsequent construction of a PPE plan applying to a given field of parallel computers.Results. Features of the internal properties of the algorithms that affect the efficiency of SPF transformations were identified during the course of computational experiments. Comparative indices of the computational complexity of obtaining PPE plans and other parameters (including code density, etc.) were obtained for various SPF transformation scenarios. An iterative approach to improving heuristic methods favors developing optimal schemes for solving the objective problem.Conclusions. The developed software system confirmed its efficiency for studying the parameters of hidden parallelism in arbitrary algorithms and rational use in data processing. The approach of using a scripting language to develop heuristic methods (scenarios) for the purposeful transformation of IGA forms showed great flexibility and transparency for the researcher. The target consumers of the developed methods for generating schedules for parallel execution of programs are, first of all, developers of translators and virtual machines, and researchers of the properties of algorithms (for identifying and exploiting the potential of their hidden parallelism). The developed software and methods have been successfully used for a number of years for increasing student competence in data processing parallelization at Russian universities.

High capacity chipless RFID tags for biomass tracking application

AbstractThe design of a low-cost, flexible, miniaturized, and a high code density chipless radio-frequency identification (RFID) tag is presented as a solution for tracking the transportation of biomass fuel pellets. The performance of the tag is presented and demonstrates the applicability of the design for different material systems, while maintaining a compact size of 5.06 cm2. The tag consists of nested concentric hexagonal elements and a central spiral resonator suitable for ID encoding. The tag presented demonstrates code density of 3.6-bits/cm2, possesses angular stability up to 60°, and high radar cross section (RCS). The tag performance was also observed for tracking 5 kg of fly-ash biomass. Additionally, as the tag mass mostly consists of FR4, PET, or Taconic TLX-0 with a minute mass of either copper, gold, or silver, the tag can be easily combusted and disposed of during biomass combustion. The novel features of this tag are the combination of hexagonal and spiral shape slots for maximum space utilization thereby achieving high RCS signatures along with high code density. All these properties of the proposed chipless RFID tag provide a pioneering pathway for a real-time biomass tracking application.

A 32-Bit Single Quadrant Angle-Controlled Chipless Tag for Radio Frequency Identification Applications.

A 32-bit chipless RFID tag operating in the 4.5–10.9 GHz band is presented in this paper. The tag has a unique multiple-arc-type shape consisting of closely packed 0.2 mm wide arcs of different radii and lengths. The specific tag geometry provides multiple resonances in frequency domain of an RCS plot. A frequency domain coding technique has also been proposed to encode the tag’s RCS signature into a 32-bit digital identification code. The tag has an overall dimension of 17.9 × 17.9 mm2, resulting in a high code density of 9.98 bits/cm2 and spectral efficiency of 5 bits/GHz. The proposed tag is built on a low loss substrate bearing a very small footprint, thereby making it extremely suitable for large-scale product identification purposes in future chipless RFID tag systems.

Multi-Channel FPGA Time-to-Digital Converter With 10 ps Bin and 40 ps FWHM

We present a novel architecture for multi-channel time-to-digital converters (TDCs) to be implemented into low-cost field-programmable gate arrays (FPGAs), achieving 10-ps least significant bit (LSB), 164- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> full-scale range, and good linearity both in terms of differential nonlinearity (DNL) and integral nonlinearity (INL). The conceived architecture is based on the carry chain delay line model and wave union A method: the positions of both rising and falling edges that propagate in multiple parallel carry chains are recorded each time there is an HIT input. This technique effectively subdivides the ultrawide bins improving the measurement precision and, combined with the sliding-scale technique and continuous code density calibration, improves the TDC linearity. Employing the proposed architecture, we have implemented in a Xilinx Artix-7 FPGA a TDC with 20 timestamp units and validated the device in a time-correlated single photon counting (TCSPC) setup, when connected to an array chip with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times 5$ </tex-math></inline-formula> single-photon avalanche diodes (SPADs).

A low-profile FSS-based high capacity chipless RFID tag for sensing and encoding applications

AbstractThis paper presents a polarization-independent 11-bit chipless RFID tag based on frequency-selective surface which has been designed for encoding and relative humidity (RH) sensing applications. The 10 exterior U-shaped resonators are used for item encoding whereas Kapton has been incorporated with the interior resonator for RH sensing. This radio-frequency identification (RFID) tag operates in S- and C-frequency bands. The proposed design offers enhanced fractional bandwidth up to 88% with the density of 4.46 bits/cm2. Both single- and dual-layer tags have been investigated. The simulated results are in good agreement with measured results and a comparison with existing literature is presented to show the performance. Simple geometry, high code density, large frequency signature bandwidth, high magnitude bit, high radar cross-section, and angular stability for more than 75° are the unique outcomes of the proposed design. In addition, RH sensing has been achieved by integrating the Kapton on the same RFID tag.

Neural Network Instruction Set Extension and Code Mapping Mechanism

PDF HTML XML Export Cite reminder Neural Network Instruction Set Extension and Code Mapping Mechanism DOI: 10.21655/ijsi.1673-7288.00251 Author: Affiliation: Clc Number: Fund Project: Article | Figures | Metrics | Reference | Related | Cited by | Materials | Comments Abstract:In recent years, Convolutional Neural Network (CNN) has received widespread attention in the field of machine learning due to its high-accuracy performance in character recognition and image classification. Nevertheless, the compute-intensive and memory-intensive characteristics of CNN have posed huge challenges to the general-purpose processor, which needs to support various workloads. Therefore, a large number of CNN-specific hardware accelerators have emerged to improve efficiency. Though significantly efficient, previous accelerators are not flexible enough. In this study, classical CNN models are analyzed and a domain-specific instruction set of 10 matrix instructions, called RV-CNN, is design based on the promising RISC-V architecture. By abstracting CNN computation into instructions, the proposed design can provide sufficient flexibility for CNN and possesses a higher code density than the general ISA. On this basis, a code-to-instruction mapping mechanism is proposed. By using the RV-CNN to build different CNN models on the Xilinx ZC702, this paper found that compared to x86 processors, RV-CNN has an average of 141 times energy efficiency and 8.91 times the code density; compared to GPU, it has an average of 1.25 times energy efficiency and 1.95 times the code density. In addition, compared to previous CNN accelerators, the design supports typical CNN models while at high energy efficiency. Reference Related Cited by

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 upmu m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5times higher performance and 2.4times higher computational energy efficiency at a 1.6times larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.

Using source code density to improve the accuracy of automatic commit classification into maintenance activities

Source code is changed for a reason, e.g., to adapt, correct, or adapt it. This reason can provide valuable insight into the development process but is rarely explicitly documented when the change is committed to a source code repository. Automatic commit classification uses features extracted from commits to estimate this reason.We introduce source code density, a measure of the net size of a commit, and show how it improves the accuracy of automatic commit classification compared to previous size-based classifications. We also investigate how preceding generations of commits affect the class of a commit, and whether taking the code density of previous commits into account can improve the accuracy further.We achieve up to 89% accuracy and a Kappa of 0.82 for the cross-project commit classification where the model is trained on one project and applied to other projects. Models trained on single projects yield accuracies of up to 93% with a Kappa approaching 0.90. The accuracy of the automatic commit classification has a direct impact on software (process) quality analyses that exploit the classification, so our improvements to the accuracy will also improve the confidence in such analyses.

A high precision TDC design based on FPGA+ARM

In this paper, a high precision time digital converter(TDC) is designed based on FPGA and ARM, It includes coarse module, delay chain module, look-up-table module, ringosc moduleand spi module in the FPGA chip. The ARM chip is used for reading the timestamp and printing through the serial port. The key technology of this design is using the CARRY4 block of Xilinx Aritex-7 series to construct a delay chain for finecount. The system clock is used as the coarse count. The timestamp is obtained by the combination of fine time and coarse time.In addition, the precison of TDC is improved by code density test. The experiment result shows that precision of TDC is 43.2ps.

A Novel Kite-Shaped Chipless RFID Tag for Low-Profile Applications

In this paper a novel, compact 10-bit chipless radio frequency identification (RFID) tag with stable readable characteristics is proposed. The tag is composed of several concentric novel kite-shaped loop resonators. The desired data sequence is obtained by the insertion or removal of nested elements, offering a 1:1 data bit to resonance correspondence. Each data sequence is encoded in the spectral domain of the tag. The proposed tag shows operability at different polarizations and incident angles of the impinging electromagnetic waves. Operating within the ultra-wideband (UWB), the tag is realized on the Roger RT/duroid® 5880 substrate having physical dimensions of 13.55 × 13.55 mm2. The measurement results of the design reveal a high code density and spectral efficiency of 5.44 bits/cm2 and 2 bits/GHz, respectively. The compact and robust passive chipless RFID tag having scalable data storage potential can be deployed in numerous low-profile applications such as those of wearable and healthcare.

Implementation of python source code comparison results with Java using bubble sort method

In the implementation of Python and Java source code comparison results are more focused on the scale of the ratio of the number of lines of code, file capacity, and access speed. As for the background of this writing because there are so many programming languages that can be used with the same results but overall we do not know which programming language is more optimal and efficient in terms of the number of lines of code better known in the programming language is LOC (Line of Code) capacity of file access speed. In this study, the authors focus only on Java programming language and python course as a first step to know the ratio of the number of lines of code, file capacity, and access density. To determine the comparison there is a method used is bubble short. The results of the implementation of the comparison of these programming languages for Python programming language to produce the number of LOC (line of code) or the number of lines of code as much as 10, the capacity of the file extension.py by 506 bytes and txt extension of 397 bytes and access speed approximately for less more 4 seconds. While Java produces the number of LOC (line of code) or the number of lines of code as much as 11, the capacity of the file extension. Java of 86.2 Kbytes and extension txt of 477 bytes and access speed for 7 seconds. So do not close the possibility to make other applications python programming language will be more optimal and efficient.