Coarse-grained Parallel Algorithm Research Articles

Coarse-Grained Parallel Algorithms for Multi-DimensionalWavelet Transforms

This paper presents parallel algorithms for computing multi-dimensional wavelet transforms on both shared memory and distributed memory machines. Traditional data partitioning methods for n-dimensional Discrete Wavelet Transforms (DWTs) call for data redistribution once a one dimensional wavelet transform is computed along each dimension. To avoid the data communication inherent in this redistribution, two new partitioning methods called CRBP (Communication Reduced Block Partitioning) and CRLP (Communication Reduced Layer Partitioning) are proposed. The efficiency of the algorithms is compared through several examples implemented on a cluster of SGI workstations. Two kinds of parallel approaches are used to compute multi-dimensional wavelet transforms on shared memory machines: homogeneous parallelism, and heterogeneous parallelism. Homogeneous parallelism uses traditional data partitioning while heterogeneous parallelism uses the CRBP approach. The effectiveness of these approaches is demonstrated through several examples implemented on an SGI Power Challenge. The paper discusses the effectiveness of each of the approaches on the two kinds of architectures.

A distributed arc-consistency algorithm

Consistency techniques are an efficient way of tackling constraint satisfaction problems (CSP). In particular, various arc-consistency algorithms have been designed such as the time optimal AC-4 sequential algorithm of Mohr and Henderson (1986). In this paper, we present a new distributed arc-consistency algorithm, called DisAC-4. DisAC-4 is based on AC-4, and is a coarse-grained parallel algorithm designed for distributed memory computers using message passing communication. Termination and correctness of the algorithm are proven. Theoretical complexities and experimental results are given. Both show linear speedup with respect to the number of processors. The strong point of DisAC-4 is its suitability to be implemented on very common hardware infrastructures like networks of workstations and/or PCs as well as on intensive computing parallel mainframes.

Optimal design of laminated composite structures using coarse-grain parallel genetic algorithms

A new coarse-grain parallel architecture for genetic algorithms, called island injection genetic algorithms, is implemented for the optimal design of laminated composite structures. This approach represents the design at various levels of refinement in subpopulations on separate computational nodes, then seeks good designs at each level of resolution and injects these good solutions into a population (node) with higher resolution to “fine-tune” the design. Numerical results are presented for the optimal design of a laminated composite beam to maximize its capacity to absorb mechanical energy without fracture. It is shown that super linear speedup can be achieved by using the injection algorithm.

Sorting with linear speedup on a pipelined hypercube

The authors formally define a distributed-memory parallel architecture called the pipelined hypercube. A coarse-grained parallel sorting algorithm that can be mapped efficiently on such an architecture is also presented. The pipelined hypercube has a more powerful communication mechanism than the traditional binary code architecture, in that it permits communication of blocks of data between processing elements (PEs) to be performed in a pipelined manner. Certain data communication problems which would probably be serialized on the binary code architecture, can be performed optimally on the pipelined hypercube. The sorting algorithm can be mapped efficiently onto a pipelined hypercube of P PEs. It sorts N data items, initially distributed among the PEs, in time O((N log N/P)+log/sup 2/ P), thereby achieving linear speedup when P is O(N/log N). >