Coarse-grained Architecture Research Articles

Evaluating Coarse-Grained FPGAs having Hard Blocks Placed in Columns

This work uses a coarse-grained FPGA architecture exploration environment to compare a column-based FPGA architecture with a non-column based architecture. Different groups of netlists are collected and a single floor-planning is optimized for all the netlists in a group. It has been found that the coarse-grained architectures that do not limit their hard-blocks to columns give much better placement costs and routing channel usage than the architectures that limit their hard-blocks to columns. Though a column based architecture can give a more compact layout as compared to a noncolumn based architecture; but the latter gives higher gains in the channel width requirements and can result in overall area gain.

Coarse-Grained Reconfigurable Computing with the Versat Architecture

Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.

Efficient and Flexible Dynamic Reconfiguration for Multi Context Architectures

Dynamic reconfiguration is possible on both fine-grain and coarse-grain architectures. One of the used methodology used consists in the use of multi-context architectures. Unfortunately, the multiple contexts bring power and area overhead. This paper introduces the Dynamic Unifier and reConfigurable blocK (DUCK) concept, a new structure to perform efficiently dynamic reconfiguration on both custom designed fine-grain and coarse grain architectures. The DUCK allows to separate the configuration path and the configuration registers which facilitates simultaneous configuration and computing steps. The reconfiguration process is presented in detail, and synthesis results are given for different structures. Our solution is finally validated with the implementation of a WCDMA (Wideband Code Division Multiple Access) receiver on a multi-context embedded FPGA and on the dynamically reconfigurable processor DART. This implementation demonstrates the interest and the efficiency of the use of dynamic reconfiguration and the proposed flexible structure.

Reconfigurable FPGA Architectures: A Survey and Applications

Reconfigurable computing is a potential paradigm which has been effectively performing mostly in the developments of devices likely Field Programmable Gate Arrays (FPGAs). This paper illustrates the reconfigurable architecture of FPGA and its types. Most widely used high-speed computation fabrics utilized in reconfigurable computing are FPGAs. This paper demonstrates the architectures used in reconfigurable computing and shows the various advantages of using reconfigurable computing design over conventional Application-Specific Integrated Circuits for achieving high level of performance for a desired application. The survey deals with the architecture of FPGAs and their types in detail. This paper also explains the highlights and challenges of fine-grained and coarse-grained architectures. FPGAs have supported partial reconfiguration over the few years. This survey also includes the partial reconfiguration techniques and the various applications of reconfigurability.

Multipopulation Genetic Algorithm Based on GPU for Solving TSP Problem

A GPU-based Multigroup Genetic Algorithm was proposed, which parallelized the traditional genetic algorithm with a coarse-grained architecture island model. The original population is divided into several subpopulations to simulate different living environments, thus increasing species richness. For each subpopulation, different mutation rates were adopted, and the crossover results were optimized by combining the crossover method based on distance. The adaptive mutation strategy based on the number of generations was adopted to prevent the algorithm from falling into the local optimal solution. An elite strategy was adopted for outstanding individuals to retain their superior genes. The algorithm was implemented with CUDA/C, combined with the powerful parallel computing capabilities of GPUs, which greatly improved the computing efficiency. It provided a new solution to the TSP problem.

SIFO: Secure Computational Infrastructure Using FPGA Overlays

Secure Function Evaluation (SFE) has received recent attention due to the massive collection and mining of personal data, but remains impractical due to its large computational cost. Garbled Circuits (GC) is a protocol for implementing SFE which can evaluate any function that can be expressed as a Boolean circuit and obtain the result while keeping each party’s input private. Recent advances have led to a surge of garbled circuit implementations in software for a variety of different tasks. However, these implementations are inefficient, and therefore GC is not widely used, especially for large problems. This research investigates, implements, and evaluates secure computation generation using a heterogeneous computing platform featuring FPGAs. We have designed and implemented SIFO: secure computational infrastructure using FPGA overlays. Unlike traditional FPGA design, a coarse-grained overlay architecture is adopted which supports mapping SFE problems that are too large to map to a single FPGA. Host tools provided include SFE problem generator, parser, and automatic host code generation. Our design allows repurposing an FPGA to evaluate different SFE tasks without the need for reprogramming and fully explores the parallelism for any GC problem. Our system demonstrates an order of magnitude speedup compared with an existing software platform.

Design Space Exploration of 1-D FFT Processor

A design space exploration methodology of 1-D FFT processor is proposed to find the best hardware architecture in a quantitative way during early design. The methodology includes architecture candidate collection, coarse-grained architecture selection, and circuit level design optimizations. We show how to select a better architecture from candidates including different architectures (SDF, SDC, MDF, MDC and memory-based) with different degree of parallelism at different radices. The sub-level designs, including designs of rotator and data scaling module, are introduced for further optimizations. As a proof of concept, an FFT processor for 4G, WLAN and future 5G is designed supporting 16-4096 and 12-2400 point FFTs. Memory-based architecture with 16-datapath mixed-radix butterfly unit is selected to satisfy the demands for 1GS/s (4096) throughput. The synthesis result based on 65nm technology shows that the silicon cost and power consumption are 1.46mm2 and 68.64mW respectively. The proposed processor has better normalized throughput per area unit and normalized FFTs per energy unit than the state of the art available designs.

Design of Coarse Grained Architecture with Gated Clock Technique for Low Power Applications

Design of Coarse Grained Architecture with Gated Clock Technique for Low Power Applications

Plasticine

Reconfigurable architectures have gained popularity in recent years as they allow the design of energy-efficient accelerators. Fine-grain fabrics (e.g. FPGAs) have traditionally suffered from performance and power inefficiencies due to bit-level reconfigurable abstractions. Both fine-grain and coarse-grain architectures (e.g. CGRAs) traditionally require low level programming and suffer from long compilation times. We address both challenges with Plasticine, a new spatially reconfigurable architecture designed to efficiently execute applications composed of parallel patterns. Parallel patterns have emerged from recent research on parallel programming as powerful, high-level abstractions that can elegantly capture data locality, memory access patterns, and parallelism across a wide range of dense and sparse applications. We motivate Plasticine by first observing key application characteristics captured by parallel patterns that are amenable to hardware acceleration, such as hierarchical parallelism, data locality, memory access patterns, and control flow. Based on these observations, we architect Plasticine as a collection of Pattern Compute Units and Pattern Memory Units. Pattern Compute Units are multi-stage pipelines of reconfigurable SIMD functional units that can efficiently execute nested patterns. Data locality is exploited in Pattern Memory Units using banked scratchpad memories and configurable address decoders. Multiple on-chip address generators and scatter-gather engines make efficient use of DRAM bandwidth by supporting a large number of outstanding memory requests, memory coalescing, and burst mode for dense accesses. Plasticine has an area footprint of 113 mm2 in a 28nm process, and consumes a maximum power of 49 W at a 1 GHz clock. Using a cycle-accurate simulator, we demonstrate that Plasticine provides an improvement of up to 76.9x in performance-per-Watt over a conventional FPGA over a wide range of dense and sparse applications.

Coarse-grained Dynamically Reconfigurable Processor for Vision Pre-Processing

The operations in vision pre-processing, especially two-dimensional convolution, are computation-intensive and demand high flexibility. Reconfigurable hardware has been typically used to achieve a good trade-off between performance and flexibility. A coarse-grained dynamically reconfigurable processor is presented for vision pre-processing. The processor architecture is a combination of a hardware reconfiguration controller, a color space converter, a reconfigurable convolution array, a convolution post-processing module, and a sampling and storing module. The dynamic reconfiguration approach and coarse-grained architecture can improve the performance and flexibility of the processor. The reconfigurable convolution array, which is the main component of the processor, can simultaneously perform convolutions with different masks, with the maximum mask size up to 16 × 16. The hardware reconfiguration controller can shorten the reconfiguration time and reduce the application difficulty. The processor is implemented on an FPGA. Experimental results show that the frame rate of the processor is more than 150 fps, far exceeding the real-time requirement for the vision system. Synthesis results show that the processor can deliver 87.1 GOPS and 3.95 GOPS/mm2 at 140 MHz system clock in SMIC 0.18μm CMOS process. The simulation and experimental results demonstrate that the processor is applicable to real-time vision pre-processing.

Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices

This paper proposes a procedure for avoiding delay faults in field with slack assessment during standby time. The proposed procedure performs path delay testing and checks if the slack is larger than a threshold value using selectable delay embedded in basic elements (BE). If the slack is smaller than the threshold, a pair of BEs to be replaced, which maximizes the path slack, is identified. Experimental results with two application circuits mapped on a coarse-grained architecture show that for aging-induced delay degradation a small threshold slack, which is less than 1ps in a test case, is enough to ensure the delay fault prediction.

A BIOMATHEMATICAL MODEL OF LYMPHOPOIESIS FOLLOWING SEVERE RADIATION ACCIDENTS—POTENTIAL USE FOR DOSE ASSESSMENT

A biomathematical model of lymphopoiesis is described and used to analyze the lymphocyte changes observed in the blood of exposed victims in radiation accidents. The coarse-grained architecture of cellular replication and production and implicit cellular regulation mechanisms used in this model make it straightforward to incorporate various radiation conditions. Model simulations with reported absorbed doses as inputs are shown to qualitatively and quantitatively describe a wide range of accidental data in vastly different scenarios. In addition, the absolute lymphocyte counts and the depletion rate constants calculated by this model show good correlation with two widely recognized empirical methods for early dose assessment. This demonstrates the potential to use the biophysical model as an alternative method for the assessment of radiation injury in the case of large-scale radiation disaster. The physiological assumptions underlying the model are also discussed, which may provide a putative mechanism for some biodosimetric tools that use the peripheral blood cell counts as markers of radiation impairment.

An augmented reality system with a coarse-grained reconfigurable device

Image recognition and motion tracking are widely utilized in the field of Augmented Reality (AR). Although their computational cost is huge, they enable to extend the practicality and the range of applications if all computation is processed within real time. Toward this goal, in this paper, we propose a handheld AR system optimized for direct hardware computation. It includes a subspace method for image recognition and a KLT tracking algorithm for motion tracking. The AR system is composed of one two-million-pixel-CCD-image sensor, one head-mounted display, one reconfigurable device called DAPDNA-2, and so on. DAPDNA-2 is a coarse-grained and dynamic-reconfigurable device which is produced by Tokyo Keiki Inc. The merit of DAPDNA-2 is its short-reconfiguration time and it is utilised to full for not only high performance but also the reduction of power consumption. The experimental result through a real Japanese-English translation system shows image recognition and motion tracking are computed within real-time; the computation time is less than 0.741 milliseconds per a VGA-resolution (640 x 480 pixels) frame. Thus, we are able to find a highly efficient computation using a coarse-grained architecture compared with general-purpose processors and embedded processors.

Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis

Compiling high-level user applications to execute on FPGAbased reconfigurable computers often involve synthesizing dataflow graphs beyond the capacity of the available hardware resources. A framework that provides rapid and energyefficient compilation of such dataflow graphs on FPGAs using an array of pre-placed configurable processing elements is proposed. The mapping schedule of the compute operations on the CPEs and the direct network among the CPEs are co-synthesized on a per-application basis to provide the targeted power-performance tradeoff. Compared to the use of a fixed generic topology, the use of an application-specific topology derived by a genetic algorithm can achieve up to 28% improvement in energy-delay product. As the CPEs are pre-placed, compiling for a new application involve only the generation of a new operation schedule, which is stored in on-chip memory, and the new routes among the CPEs. With optimization in operation scheduling and mapping and application-specific interconnect network, the proposed framework achieved up to 199X better energy-delay product compared to a traditional FPGA high-level synthesis tool xPilot. The use of such framework is anticipated to serve as part of a high-level application compiler for hybrid CPU-FPGA computation.

CHARACTERIZATION OF THE RADIATION-DAMAGED PRECURSOR CELLS IN BONE MARROW BASED ON MODELING OF THE PERIPHERAL BLOOD GRANULOCYTES RESPONSE

Bone marrow failure is the major cause of radiation lethality in mammals. Since bone marrow is distributed heterogeneously within trabecular spongiosa encased in a cortex of cortical bone, it is very difficult to measure the extent of the radiation damage directly. However, indirect consequences of damage to marrow, such as reductions in peripheral blood cell counts, are easily measured. In this paper, the authors investgate a mathematical model of the granulopoiesis system that provides quantitative relationships between reductions in peripheral blood cells and the bone marrow precursor cells following radiation exposure. A coarse-grained architecture of cellular replication and production as well as a mechanism for implicit regulation used in this model are discussed. The model is based on previous investigations of rodents. The authors test how well the model matches, in the principal dynamic regime of hematopoiesis, experimental data on large animals as well as empirical data on humans following radiation exposure. Due to its ability to infer, albeit indirectly, radiation damage to bone marrow, this model will provide a useful computational tool in radiation accident management, military operations involving nuclear warfare, radiation therapy, and space radiation risk assessment.

Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture

Since the power consumption of FPGA is larger than that of ASIC under the condition to perform the same function using the same scaling, the application of FPGA is limited especially in portable electronic devices. In this paper, we propose a novel low-power FPGA architecture based on coarse-grained power gating to reduce power consumption. The new placement algorithm and routing resource graph for sleep regions is also presented. After enhancing the CAD framework, a detailed discussion is given under different region size supported by the new FPGA architecture. As a result, our proposed FPGA architecture combined with the new placement and routing algorithm can reduce 19.4% in the total power consumption compared with the traditional FPGA. By using our proposed method, FPGA is promising to be widely applied to portable devices.

A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core

In the present study, we investigate the use of reconfigurable logic devices (RLDs) as intellectual properties (IPs) for system on a chip (SoC). Using RLDs, SoCs can achieve both high performance and high flexibility. However, conventional RLDs have problems related to performance, area, and power consumption. In order to resolve these problems, we investigated the features of RLD architecture. RLDs are classified into fine-grained and coarse-grained devices based on their architecture. Generally, the granularity of an RLD is limited to either type, which means that a device can only achieve high performance in applications that are suited to its architecture. Therefore, we propose a variable-grain logic cell (VGLC) architecture that can overcome the trade-off between fine-grained and coarse-grained architectures, which are required for the implementation of random and arithmetic logics, respectively. The VGLC is based on a 4-bit adder including configuration bits, which can perform arithmetic and random logic operations unlike the LUT. In the present paper, a local interconnection architecture for the VGLC is proposed. Several types of local interconnections composed of different crossbars are compared, and the trade-off between hardware resources and flexibility is discussed. Using local interconnection, the routing area is reduced by a maximum of 49%.

Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures

This paper proposes a reliability evaluation environment for coarse-grained reconfigurable architectures. This environment is designed so that it can be easily extended to different target architectures and applications by automating the generation of the simulation inputs such as HDL codes for fault injection and configuration information. This automation enables us to explore a huge design space in order to efficiently analyze area/reliability trade-offs and find the best solution. This paper also shows demonstrative examples of the design space exploration of coarse-grained reconfigurable architectures using the proposed environment. Through the demonstrations, we discuss relationship between coarse-grained architectures and reliability, which has not yet been addressed in existing literatures and show the feasibility of the proposed environment.

Architecture Exploration for a Reconfigurable Architecture Template

Coarse-grained architectures (CGRAs) can be tailored and optimized for different application domains. The vast design space of coarse-grained reconfigurable architectures complicates the design of optimized processors. The goal is to design a domain-specific processor that provides just enough-flexibility for that domain while minimizing the energy consumption for a given level of performance. However, a flexible architecture template and a retargetable simulator and compiler enable systematic architecture exploration that can lead to more efficient domain-specific architecture design. This article presents such an environment and an architecture exploration for a novel CGRA template.

Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compilation tools are essential to their success. In this paper, we present a modulo scheduling algorithm to exploit loop-level parallelism for coarse-grained reconfigurable architectures. This algorithm is a key part of our dynamically reconfigurable embedded systems compiler (DRESC). It is capable of solving placement, scheduling and routing of operations simultaneously in a modulo-constrained 3D space and uses an abstract architecture representation to model a wide class of coarse-grained architectures. The experimental results show high performance and efficient resource utilization on tested kernels.