Co-packaged Optics Research Articles

A 4×112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics

A 4×112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics

Progress in Research on Co-Packaged Optics

In the 5G era, the demand for high-bandwidth computing, transmission, and storage has led to the development of optoelectronic interconnect technology. This technology has evolved from traditional board-edge optical modules to smaller and more integrated solutions. Co-packaged optics (CPO) has evolved as a solution to meet the growing demand for data. Compared to typical optoelectronic connectivity technology, CPO presents distinct benefits in terms of bandwidth, size, weight, and power consumption. This study presents an overview of CPO, highlighting its fundamental principles, advantages, and distinctive features. Additionally, it examines the current research progress of two distinct approaches utilizing Vertical-Cavity Surface-Emitting Laser (VCSEL) and silicon photonics integration technology. Additionally, it provides a concise overview of the many application situations of CPO. Expanding on this, the analysis focuses on the CPO using 2D, 2.5D, and 3D packaging techniques. Lastly, taking into account the present technological environment, the scientific obstacles encountered by CPO are analyzed, and its future progress is predicted.

A 4×112 Gb/s Ultra-Compact Polarization-Insensitive Silicon Photonics WDM Receiver With CMOS TIA for Co-Packaged Optics and Optical I/O

A 4×112 Gb/s Ultra-Compact Polarization-Insensitive Silicon Photonics WDM Receiver With CMOS TIA for Co-Packaged Optics and Optical I/O

Co-Packaged Optics - Heterogeneous Integration of Photonic IC and Electronic IC

Abstract The trends in co-packaged optics will be investigated in this study. Emphasis is placed on the heterogeneous integration of photonic IC (PIC) and electronic IC (EIC). In particular, 2D and 3D heterogeneous integration of ASIC Switch, PIC and EIC w/o bridges, and heterogeneous integration of ASIC Switch, PIC and EIC on glass substrate will be discussed. Some recommendations will be provided.

Integration of Multi-Lithography Technologies for the Fabrication of Flexible Optical Link

The advancement in demand for high bandwidth energy-efficient communication in the data centre and edge cloud servers needs a viable optical interconnection solution to cope with the demands. Therefore, the presented study describes the concept of flexible multi-mode waveguides (MMWGs) as an optical link for co-packaged optics. It evaluates three lithography technologies; UV-lithography, 2 photon polymerization direct laser writing process (2PP-DLW), and nano-imprint lithography (NIL) for the fabrication of flexible MM-WGs. The UV-lithography and 2PP-DLW process were evaluated for the fabrication of MM-WGs and micro-mirrors, respectively, for the master pattern of the NIL stamp. The NIL evaluates the imprinting of the MM-WGs with micro-mirrors at either end on the flexible and transparent PEN substrates with a low-loss OrmoClad lower cladding layer. There are five different crosssections from 10x10 μm2 to 50x50 μm2 of MM-WGs with micromirrors were imprinted. Additionally, it presents the importance of integrating multi-lithography technologies to fabricate flexible optical links where a 2PP-DLW process shows the best results for printing μm-scale optical components. On the other side, UV-lithography with SU-8 gives the foremost definition of the master for the polymeric MM-WGs. Furthermore, NIL offers the industrial mass-production option alongside prototyping.

Exploring the benefits of using co-packaged optics in data center and AI supercomputer networks: a simulation-based analysis [Invited

We investigate the advantages of using co-packaged optics in next-generation data center and AI supercomputer networks. The increased escape bandwidth offered by co-packaged optics provides multiple possibilities for building 50T switches and beyond, expanding the opportunities in both the data center and supercomputing domains. This provides network architects with the opportunity to expand their design space and develop simplified networks with enhanced network locality properties. Co-packaging at the switch and server points enables networks with double capacity while reducing the switch count by 64% compared to state-of-the-art systems. We evaluate these concepts through discrete-event simulations using all-to-all and all-reduce traffic patterns that simulate collective communications commonly found in network-bound applications. Initially, we investigate the all-to-all overhead involved in distributing the virtual machines of the applications across multiple leaf switches and compare it to the scenario in which all VMs are placed under a single switch. Subsequently, we evaluate the performance of an AI supercomputing cluster by simulating both patterns for different message sizes, while also varying the number of participating nodes. The results suggest that networks with improved locality properties become increasingly important as the network stack operates at higher speeds; for a stack latency of 1.25 µs, placing the applications under multiple switches can result in up to 68% higher completion times than placing them under a single switch. For AI supercomputers, significant improvements are observed in the mean server throughput, reaching more than 90% for configurations involving 256 nodes and message sizes of at least 128 KiB.

Thermo-Mechanical and Compression Analyses for Large-Scale Co-packaged Optics (CPO) Assembly

Thermo-Mechanical and Compression Analyses for Large-Scale Co-packaged Optics (CPO) Assembly

1.6 Tbps FOWLP-Based Silicon Photonic Engine for Co-Packaged Optics

1.6 Tbps FOWLP-Based Silicon Photonic Engine for Co-Packaged Optics

Co-Packaged Optics Opportunities in Radio-Access Networks

Co-Packaged Optics Opportunities in Radio-Access Networks

Thermal Characteristics of Mirror-Based Optical Redistribution for Co-Packaged Optics

Thermal Characteristics of Mirror-Based Optical Redistribution for Co-Packaged Optics

Ultrafast laser processing of glass waveguide substrates for multi-fiber connectivity in co-packaged optics

High bandwidth demanding applications such as high-performance computing and hyperscale datacenters are drivers for co-packaged optics, which aims to bring optical signals as close as possible to the electrical computing chips by integrating the electro-optic transceivers and ASICs on the same package substrate. These next-generation switches require advanced fiber-to-chip connectivity and novel packaging concepts to enable sufficient power and cost savings. As such, low-loss, high bandwidth, and high fiber-counts are required at the photonic chip interface. In this work, these challenges are addressed by enabling the multi-fiber push-on (MPO) interface at the edge of integrated glass waveguide substrates and thus leverages the existing fiber connector eco-system. An ultrafast laser process is used to singulate glass wafers into individual photonic chips leaving optical-quality end-facets with <1 μm flatness over the 6.5 mm wide connector region thereby directly enabling low-loss fiber-to-chip edge-coupling. To overcome the high-costs and complex photonic packaging associated with active alignment of the fiber connectors to the glass waveguide interfaces, ultrafast laser-ablated features are accurately positioned on the glass substrate to enable self-alignment of the MPO connector guide-pins resulting in a passive alignment approach. Subsequent mating and de-mating of the MPO connector to the glass waveguide interface yields on average a 0.19 dB increase in the coupling loss compared to using active alignment.

Demonstration of Silicon-Photonics Hybrid Glass-Epoxy Substrate for Co-Packaged Optics

Demonstration of Silicon-Photonics Hybrid Glass-Epoxy Substrate for Co-Packaged Optics

Effective switchless inter-FPGA memory networks

FPGA network bandwidth increases to 400 Gbps or higher by high-density optical integration, e.g., Co-Packaged Optics (CPO) and onboard Si-photonics transceivers. This study presents its lightweight switchless network architecture by exploiting an indirect path, consisting of up to k one-hop paths for a diameter-k network topology. It integrates interconnection network and memory channels into a lightweight memory-to-memory inter-FPGA network. It has a uni-directional network topology for connecting the largest number of FPGAs. A newly introduced indirect flow control enables lossless uni-directional networks. We present multi-path point-to-point communications, multi-port message-combine collective communications, and efficient WDM (Wavelength Division Multiplexing) cabling method for the uni-directional networks. We implement and evaluate the uni-directional switchless network on an FPGA cluster consisting of six custom Stratix10 MX2100 FPGA cards connected with a 16-wavelength Arrayed Waveguide Grating (AWG) router. Simulation results show that the multi-port message-combine collective communication achieves 7× faster than conventional communication with 272 FPGAs. Effective WDM cabling using 16 wavelengths decreases the number of cables by 88% compared with parallel optical cabling for 272 FPGAs.

Glass Substrate for Co-Packaged Optics

Co-packaged optics leads to significant power reduction by placing the electronic and photonic chiplets in a single package. An integrated electro-optical substrate made of glass with optical waveguides, through vias and electrical redistribution layers inside a single-sided cavity enables fine-line electrical routing and low-cost assembly. Existing glass and thin film technologies were evaluated and combined into a single process stream including photonic assembly. Photonic chips with silicon nitride waveguides were optically coupled to integrated low-loss (<0.1 dB/cm) glass waveguides with minimum loss of 0.65 dB achieved by fiducial alignment and pick-and-place assembly.

Ultra-Compact Optical Transceiver Technologies for Co-Packaged Optics

Ultra-Compact Optical Transceiver Technologies for Co-Packaged Optics

Co-packaged optics (CPO): status, challenges, and solutions

Due to the rise of 5G, IoT, AI, and high-performance computing applications, datacenter traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three-fourths of the datacenter traffic resides within datacenters. The conventional pluggable optics increases at a much slower rate than that of datacenter traffic. The gap between application requirements and the capability of conventional pluggable optics keeps increasing, a trend that is unsustainable. Co-packaged optics (CPO) is a disruptive approach to increasing the interconnecting bandwidth density and energy efficiency by dramatically shortening the electrical link length through advanced packaging and co-optimization of electronics and photonics. CPO is widely regarded as a promising solution for future datacenter interconnections, and silicon platform is the most promising platform for large-scale integration. Leading international companies (e.g., Intel, Broadcom and IBM) have heavily investigated in CPO technology, an inter-disciplinary research field that involves photonic devices, integrated circuits design, packaging, photonic device modeling, electronic-photonic co-simulation, applications, and standardization. This review aims to provide the readers a comprehensive overview of the state-of-the-art progress of CPO in silicon platform, identify the key challenges, and point out the potential solutions, hoping to encourage collaboration between different research fields to accelerate the development of CPO technology.Graphical

Beyond CPO: A Motivation and Approach for Bringing Optics Onto the Silicon Interposer

Co-packaged optics (CPO) technology is well positioned to break through the bottlenecks that impede efficient bandwidth scaling in key near-term commercial integrated circuits. We begin by providing some historical context for this important sea change in the optical communications industry. Then, motivated by GPU-based accelerated computing requirements, we investigate the next pain points that are poised to constrain bandwidth and efficiency in future CPO-based systems. We identify 2.5D integrated optics (i.e., bringing optics onto the interposer) as a promising solution that can enable continued scaling for these systems due to the dense wiring available which facilitates more efficient slow-and-wide electrical interfaces. We explore the benefits, challenges, and requirements associated with such tight coupling of the processors and optical engines by considering high-level photonic link design, technology, and packaging. We demonstrate the viability of a control loop which can adequately regulate temperature within the aggressive thermal environment. Then, we introduce a custom simulation framework that allows quantified comparisons of detailed design decisions; the simulations validate the feasibility of the general approach while also providing key guidance to designers on best directions to pursue for efficient optimization.

High density vertical optical interconnects for passive assembly.

The co-packaging of optics and electronics provides a potential path forward to achieving beyond 50 Tbps top of rack switch packages. In a co-packaged design, the scaling of bandwidth, cost, and energy is governed by the number of optical transceivers (TxRx) per package as opposed to transistor shrink. Due to the large footprint of optical components relative to their electronic counterparts, the vertical stacking of optical TxRx chips in a co-packaged optics design will become a necessity. As a result, development of efficient, dense, and wide alignment tolerance chip-to-chip optical couplers will be an enabling technology for continued TxRx scaling. In this paper, we propose a novel scheme to vertically couple into standard 220 nm silicon on insulator waveguides from 220 nm silicon nitride on glass waveguides using overlapping, inverse double tapers. Simulation results using Lumerical's 3D Finite Difference Time Domain solver are presented, demonstrating insertion losses below -0.13 dB for an inter-chip spacing of 1 µm; 1 dB vertical and lateral alignment tolerances of approximately 2.6 µm and ± 2.8 µm, respectively; a greater than 300 nm 1 dB bandwidth; and 1 dB twist and tilt tolerances of approximately ± 2.3 degrees and 0.4 degrees, respectively. These results demonstrate the potential of our coupler for use in co-packaged designs requiring high performance, high density, CMOS compatible out of plane optical connections.

Detachable interface toward a low-loss reflow-compatible fiber coupling for co-packaged optics (CPO).

High-density reflow-compatible fiber I/O is one of the challenges for co-packaged optics (CPO). This paper developed a detachable coupling interface based on expanded beam edge coupling, which can be applied for optical coupling between lasers, PICs, and fibers, seamlessly supporting many channels with high efficiency. It comprises a removable fiber connector and a permanent chip/device connector, in which microlens/lens arrays are used for waveguide mode expansion and MT-like connectors are used for position registration. An effective alignment scheme based on beam detection was developed and implemented in an assembly station for building the removable fiber connectors, while the permanent chip/device connector was assembled by active alignment to a pre-made fiber connector mated with a registration connector. Promising results were obtained from the proof-of-concept demonstrations of the coupling from SiP PIC and III/V lasers to fibers using the off-the-shelf lenses and modified MT registration connectors. In both cases, less than 1 dB coupling loss was achieved with an expanded beam size of 160 µm in diameter. Even with a relatively large lens offset of ∼35 µm, the detachable fiber array connectors showed good interchangeability. Such a coupling interface is expected to be solder-reflow compatible by replacing the plastic registration connectors with ceramic ones, making it a promising candidate for the solution to CPO fiber I/O.

Glass Platform for Co-Packaged Optics

Placing the electrical and photonic chiplets in a single package leads to significant power reduction. Chiplets are connected by fine-line electrical routing over a length of a few millimeters and optical interconnects in the package connect photonic chips with optical fibers for off-package communication. A packaging substrate made of glass with optical waveguides, through glass vias and electrical redistribution layers inside a single-sided cavity enables lower-cost assembly. A single-sided 50 µm deep cavity was etched in glass, and electrical copper lines with 5 µm in height and width were deposited on the floor of the cavity. Ion-exchange (IOX) waveguides with propagation loss of <0.1 dB/cm were fabricated below the glass surface. For flip-chip assembly of photonic chips and optical coupling with the IOX waveguides at the top surface of the glass, all electrical interconnects were located inside the cavity. Photonic chips with silicon nitride waveguides were optically coupled to glass waveguides with a minimum loss of 0.5 dB, achieved by fiducial-aligned flip-chip photonic assembly. A low-profile fiber connector with height of 4.4 mm connects the integrated ion-exchanged waveguides with the optical fibers. Average connector loss of 0.83 dB was demonstrated with physical contact between fibers and IOX glass waveguides.