CMOS Transconductor Research Articles

CMOS VM/CM Tow–Thomas-Equivalent Biquad Filters and a Linear VCO Using Recently Proposed CMOS Transconductors

The main objective of this paper is to present novel applications of two recently proposed CMOS transconductors in realizing voltage mode/current mode Tow–Thomas (TT)-equivalent biquads and a linear voltage-controlled oscillator (VCO), all exhibiting a number of advantages over the previously known circuits to realize the same functions. The workability of all the propositions has been demonstrated by SPICE simulation results using TSMC [Formula: see text] CMOS technology parameters.

Fully active frequency compensation analysis on multi-stages CMOS amplifier

An enhanced three-stage CMOS transconductance amplifier attached to a novel frequency compensation network is proposed. Two differential stages are attached with Miller capacitors and the Miller effect is boosted accordingly. In this way, four negative loops intensify the Miller effect virtually. The structure is designed at the transistor level using 0.18 μm CMOS library and the SPICE simulator while a symbolical transfer function is extracted and analyzed to obtain circuit dynamics. Leveraging both concept and method, the proposed amplifier shows unconditional stability with acceptable accuracy regarding the symbolic description and simulation results. Ample sensitivity analysis is also provided to show the reliability of the amplifier. By simulation responses, the presented circuit expresses competitive merits against previous works. Simulation results show 120 dB as DC gain, 18 MHz as, GBW, and 54º as phase margin while the simulated amplifier consumes only 345μW.

CMOS Trans Conductance based Instrumentation Amplifier for Various Biomedical Signal Analysis

Feed forward design techniques for the Trans-conductance operational amplifier removes the barriers of operating frequencies. It is now possible to design amplifiers with large the Trans-conductance that operates at Giga hertz frequency range. There are several Trans-conductance amplifiers used to design a medical and Industrial application that helps in processing various bio medical signals such as Electrocardiographs, Electroencephalographs, Electromyograms and several others. The proposed paper shows the implementation of an instrumentation amplifier using CMOS based the Trans-conductance operational amplifiers also the processing of biomedical ECG, EEG and EMG signals. The CMOS process technology helps to integrate complex circuits on minimal surface area. The Trans-conductance instrumentation operational amplifiers has features includes noise reduction, low DC offset, High output impedance and Common Mode rejection Ratio values. The circuit implementation and simulations has been done on Electronic Design and Automation tool with 0.13μm CMOS process technology.

0.5 V CMOS Inverter-Based Transconductance Amplifier with Quiescent Current Control

A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary transistors between the supply rails. The amplifier provides class-AB operation with quiescent current control obtained through an auxiliary loop that utilizes the MOSFETs body terminals. Simulation results, referring to a commercial 28 nm bulk technology, show that the quiescent current of the amplifier can be controlled quite effectively, even adopting a supply voltage as low as 0.5 V. The designed solution consumes around 500 nA of quiescent current in typical conditions and provides a DC gain of around 51 dB, with a unity gain frequency of 1 MHz and phase margin of 70 degrees, for a parallel load of 1 pF and 1.5 MΩ. Settling time at 1% is 6.6 μs, and white noise is 125 nV/Hz.

A new active resistor and its application to a CMOS transconductor

In this paper a new active resistor is proposed which is suitable for tunable linear voltage to current converters. The proposed resistor is composed of the main and auxiliary triode-mode transistors in which the resistance of auxiliary transistor adds to that of main transistor at a specific tune voltage. By this way the triode operation of both transistors is ensured throughout the tuning range. The proposed resistor is used in a tunable linear transconductor. The proposed transconductor which is implemented in 0.13 μm CMOS technology works with 1.2 V supply voltage and its power consumption changes between 682 and 980 μW. Simulation results show 20 dB improvement in THD of transconductor thanks to using proposed resistor rather than conventional one for input voltage amplitude of 1Vpp at 1 MHz. The transconductance can be tuned from 68 to 177.4 μA/V and the THD remains less than −55 dB for input voltage amplitudes up to 1.2Vpp and for the entire tuning range.

CMOS transconductor with improved linearity using the bulk of self‐cascode transistors

A novel transconductor based on the source degeneration technique is introduced. The proposed solution includes self-cascode transistors as input devices, additionally employing their bulk terminal to increase the linearity. Input transconductance characteristics are improved as compared with conventional topologies without considerably increasing power consumption and die area. The circuit was designed and fabricated in a standard 0.18 μm CMOS technology to operate with a 1.8 V single supply voltage. Experimental results showed a linearity improvement of 20 dB for an input signal of 0.2 V at 100 kHz.

Design of Linear CMOS Transconductance Elements for Alpha-Power Law Based Mosfets and an Automatic Compensation Technique for Temperature

A model on alpha-power law MOSFETs based source-coupled differential pair (SCDP) is discussed and a simple design procedure for realizing a linear CMOS SCDP transconductance element is proposed. The proposed or modified SCDP circuit using this procedure is an alternative to that of conventional SCDP and the circuit discussed has superior linearity for a wide range ±(0-300mv) of input differential voltage at a supply voltage of 1.2v. The modified SCDP also includes the circuitry needed to suppress the variation in the quiescent current with respect to input common-mode voltage noise. The SPICE results are used to verify theoretical predictions. The results show close agreement between the predicted model behavior and the simulated performance. The simulated result on Total Harmonic Distortion (THD) shows that the modified SCDP circuit is better than the conventional SCDP by about four times at input differential voltage amplitude of ±100mv. An example circuit, a second order continuous time gm-C band-pass filter is constructed using the fully differential modified SCDP and the fully differential conventional SCDP circuit and the result shows that the modified transconductor circuit is better in linearity (THD) than the conventional SCDP by about two times at the input differential voltage amplitude of ±100mv. An automatic digital compensation scheme for temperature is also presented and the temperature coefficient of output current is reduced by about eight times to 250ppm/deg. C after compensation for the maximum change in temperature of 150deg.C and at the input differential voltage of 100mv.

Highly linear wide‐swing continuous tuning of CMOS transconductors

SUMMARYA technique to improve the input and output range of CMOS transconductors with resistive current division for continuous tuning is presented. Using it, a tunable transconductor is proposed which features high linearity over a wide input range and simplicity. Measurement results of the transconductor, fabricated in a 0.5 µm CMOS process, show an IM3 of −66 dB for a ±1.65 V supply and two input tones centered at 1 MHz of 1 Vpp each, and only 0.7 mW of power consumption. This represents an improvement of 13 dB versus the same transconductor using conventional current division. Copyright © 2013 John Wiley & Sons, Ltd.

Design of micropower class AB transconductors: A systematic approach

A systematic design approach to achieve micropower class AB CMOS transconductors is presented. It includes techniques to get rail-to-rail operation and continuous transconductance tuning, based on floating and Quasi-Floating Gate transistors. Application of the proposed design approach leads to a new family of high-performance power-efficient class AB CMOS transconductors. To illustrate the feasibility of this approach, 12 transconductors derived from this common framework have been designed and fabricated in a 0.5μm CMOS technology. Measurement results show THD values for 2V inputs of −56dB for a static power of 300μW and silicon area <0.07mm2.

A 1.5V CMOS Transconductor using adaptive biasing and its application

A low-voltage CMOS transconductor is designed in 0.35µm standard CMOS technology. The proposed circuit uses adaptive biasing linearization method to achieve better linearity in low voltage applications. Simulation results using HSPICE show a total harmonic distortion of -71 dB at 1.25 MHz for a 400 mV peak to peak input voltage. The total power consumption is only 45 µW with 1.5 V power supply. The circuit can be used in the implementation of membership functions or fuzzifiers in analogue and mixed-signal neuro-fuzzy systems. Keywords: Adaptive biasing, High linear, Low-voltage, Low-power, Transconductance, Fuzzifier.

A simple CMOS-based inductor simulator and frequency performance improvement techniques

In this paper, a new CMOS grounded positive tunable inductor simulator based on using two simple CMOS transconductors and an inverting amplifier is presented. The introduced inductor simulator uses a grounded capacitor; accordingly, it is suitable for integrated circuit (IC) fabrication. In addition a CMOS circuit for realizing negative tunable resistor which can be used for parasitic cancellation in inductor simulators and consequently enhancing their frequency performances is developed. A novel method for providing high-frequency performance improvement of simulated inductors is also introduced. Simulation and experimental results are given to demonstrate the performance of the developed inductor simulator and validity of the proposed frequency performance improvement method.

A 3–5 GHz Current-Reuse $g_{m}$-Boosted CG LNA for Ultrawideband in 130 nm CMOS

This paper presents a low-power CMOS transconductance “ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> ” boosted common gate (CG) ultrawideband (UWB) low noise amplifier (LNA) architecture, operating in the 3-5 GHz range, employing current-reuse technique. This proposed UWB CG LNA utilizes a common source (CS) amplifier as the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> -boosting stage which shares the bias current with the CG amplifying stage. A detailed mathematical analysis of the LNA is carried out and the different design tradeoffs are analyzed. The LNA circuit was designed and fabricated using the 130-nm IBM CMOS process and it achieved input return loss (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) and output return loss (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">22</sub> ) variations of respectively - 8.4 to - 40 dB and - 14 to - 15 dB within the pass-band. The LNA exhibits almost flat forward power gain (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) of 13 dB and a reverse isolation (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sub> ) variation of -55 dB to -40 dB, along with a noise figure (NF) ranging between 3.5 and 4.5 dB. The complete circuit (with output buffer) draws only 3.4 mW from a 1 V supply voltage.

A low-voltage low-power CMOS fully differential linear transconductor with mobility reduction compensation

A highly linear fully differential CMOS transconductor architecture based on flipped voltage follower (FVF) is proposed. The linearity of the proposed architecture is improved by mobility reduction compensation technique. The simulated total harmonic distortion (THD) of the proposed transconductor with 0.4Vpp differential input is improved from −42dB to −55dB while operating from 1.0V supply. As an example of the applications of the proposed transconductor, a 4th-order 5MHz Butterworth Gm-C filter is presented. The filter has been designed and simulated in UMC 130nm CMOS process. It achieves THD of −53dB for 0.4Vpp differential input. It consumes 345μw from 1.0V single supply. Theoretical and simulated results are in good agreement.

A highly linear CMOS transconductance amplifier in 180 nm process technology

The present article describes the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range. The proposed configuration combines the techniques of signal attenuation and source degeneration in order to reduce the odd order harmonic distortion significantly. The proposed circuit is compared with several circuit topologies based on MOS differential pairs with respect to their achievable linearity, input referred noise and power consumption. The linear transconductor is designed and simulated in 180 nm CMOS process technology with 1.8 V power supply. Simulation results show third order harmonic distortion (HD 3) of ?70 dB for 600 mVpp input signal. For 1% transconductance variation the linear range is about 1.2 Vpp. The input referred noise of the transconductor is $$70\,\hbox{nV}/\sqrt{\text {Hz}}$$ at 10 MHz. The quiescent power consumption is only 450 μW.

An active device based wide tuning range CMOS transconductor

A CMOS transconductor for wide tuning range filter application is presented. The linear transconductor is designed based on the flipped-voltage follower (FVF) circuit and can work in the weak, mode...

Using Floating Gate and Quasi-Floating Gate Techniques for Rail-to-Rail Tunable CMOS Transconductor Design

Floating-gate and quasi-floating gate MOS transistors can be efficiently employed to design CMOS transconductors. These transistors allow achievement of relevant features in a compact and simple way, such as rail-to-rail input range, continuous transconductance tuning, and class AB operation. This paper illustrates how these techniques can be applied by employing them in the design of two transconductors, which have been fabricated in a 0.5 μm CMOS process. Measurement results confirm the advantages of the proposed approach.

Enhanced source-degenerated CMOS differential transconductor

A simple technique to improve the output resistance and the linearity of a source-degenerated differential CMOS transconductor is presented, useful even under low supply voltage. It combines the utilization of a super-transistor as a unity-gain buffer and the use of the weak inversion region to optimize a regulated cascode source. Using a standard 0.13μm CMOS technology with 1.5V supply voltage, simulation results show the transconductor attains more than 1GΩ as differential output resistance and a third-order harmonic distortion factor less than −110dB at 1kHz for a 0.35Vpp differential input signal. Other performances are 126μW power consumption and 65MHz bandwidth.

CMOS triode transconductor based on quasi-floating-gate transistors

A novel CMOS transconductor based on transistors operating in the triode region and quasi-floating gate (QFG) techniques is proposed. The V-I conversion is performed by two triode transistors acting as a current divider and QFG transistors are employed to enforce a constant drain-source voltage, improving the linearity notably. The circuit has been fabricated and measured using a 0.5 µm CMOS technology in order to validate the QFG design.

A -68.5 dB IM3 Low-Voltage CMOS Transconductor with Wide Tuning Range

SUMMARY A CMOS transconductor for multi-mode application is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier, which operates in the weak inversion region, provides a wide transconductance tuning range without degrading the linearity. The transconductor was designed and fabricated in the TSMC 0.18-μm CMOS process. The results show the transconductance tuning ratio of 23 and the IM3 performance of −68.5 dB.

A Fault Signature Characterization Based Analog Circuit Testing Scheme and the Extension of IEEE 1149.4 Standard

An analog circuit testing scheme is presented. The testing technique is a sinusoidal fault signature characterization, involving the measurement of DC offset, amplitude, frequency and phase shift, and the realization of two crossing level voltages. The testing system is an extension of the IEEE 1149.4 standard through the modification of an analog boundary module, affording functionalities for both on-chip testing capability, and accessibility to internal components for off-chip testing. A demonstrating circuit-under-test, a 4th-order Gm-C low-pass filter, and the proposed analog testing scheme are implemented in a physical level using 0.18-µm CMOS technology, and simulated using Hspice. Both catastrophic and parametric faults are potentially detectable at the minimum parameter variation of 0.5%. The fault coverage associated with CMOS transconductance operational amplifiers and capacitors are at 94.16% and 100%, respectively. This work offers the enhancement of standardizing test approach, which reduces the complexity of testing circuit and provides non-intrusive analog circuit testing.