Abstract
A low-voltage CMOS transconductor is designed in 0.35µm standard CMOS technology. The proposed circuit uses adaptive biasing linearization method to achieve better linearity in low voltage applications. Simulation results using HSPICE show a total harmonic distortion of -71 dB at 1.25 MHz for a 400 mV peak to peak input voltage. The total power consumption is only 45 µW with 1.5 V power supply. The circuit can be used in the implementation of membership functions or fuzzifiers in analogue and mixed-signal neuro-fuzzy systems. Keywords: Adaptive biasing, High linear, Low-voltage, Low-power, Transconductance, Fuzzifier.
Highlights
Linear CMOS transconductors are versatile analog (Sánchez-Sinencio et al, 1989; Valburg & van de Plassche, 1992; Sasaki et al, 1992; Thomsen & Brooke, 1993)
Often in these applications the input transconductor determines the overall linearity of the system
Several linearization techniques have been proposed in literature to enhance the linearity of MOS transconductors (Krummenacher & Joehl, 1988; Kuo & Leuciuc, 2001; Worapishet & Nephaphan, 2003; Kachare et al, 2005a)
Summary
Several linearization techniques have been proposed in literature to enhance the linearity of MOS transconductors (Krummenacher & Joehl, 1988; Kuo & Leuciuc, 2001; Worapishet & Nephaphan, 2003; Kachare et al, 2005a). The reported linearization techniques include: cross-coupling of multiple differential pairs, adaptive biasing, source degeneration (using resistor or MOS transistor), shift level biasing, series connection of multiple differential pairs and pseudodifferential stages (using transistor in the triode region or in saturation) All these techniques enhance the linearity, they are not well suited for low-voltage operation. Low voltage linear transconductor design we will firstly review adaptive biasing linearization technique which is previously reported (Nedungadi & Viswanathan, 1984). In this technique an adaptive biasing current source is used to cancel the
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