CMOS Technology Research Articles

An Efficient Design of 2-BIT Arithmetic Logical Unit in Quantum Dot Cellular Automata

For the past two decades, CMOS technology has reigned supreme in the world of Very Large Scale Integration (VLSI). But Quantum Dot Cellular Automata (QCA) is stepping into the spotlight, offering a fresh solution to the growing challenges of CMOS. This paper delves into the potential of QCA circuits by presenting a 2-bit Arithmetic Logic Unit (ALU) crafted with this groundbreaking technology, while also benchmarking it against conventional CMOS designs. The proposed QCA-based ALU delivers a trifecta of benefits: streamlined circuit design, exceptional space efficiency, and reduced quantum cost—all while keeping performance sharp in terms of latency and area usage. This 2-bit ALU encompasses a suite of operations: addition, subtraction, multiplication, division, bitwise AND, OR, XOR, and XNOR. QCA technology addresses some of CMOS's major pain points, like slow switching speeds, and doesn't require additional power sources, making it both efficient and environmentally friendly. This is not just an incremental improvement; it's a bold leap into the future of circuit design

Low power nanoscale S-FED based single ended sense amplifier applied in integrate and fire neuron circuit

Current advancements in neuromorphic computing systems are focused on decreasing power consumption and enriching computational functions. Correspondingly, state-of-the-art system-on-chip developers are encouraged to design nanoscale devices with minimum power dissipation and high-speed operation. This paper deals with designing a sense amplifier based on side-contacted field-effect diodes to reduce the power-delay product (PDP) and the noise susceptibility, as critical factors in neuron circuits. Our findings reveal that both static and dynamic power consumption of the S-FED-based sense amplifier, equal to 1.86 μW and 1.92 fW/GHz, are × 243.03 and × 332.83 lower than those of the conventional CMOS counterpart, respectively. While the sense-amplifier circuit based on CMOS technology undergoes an output voltage deviation of 170.97 mV, the proposed S-FED-based one enjoys a minor output deviation of 27.31 mV. Meanwhile, the superior HIGH-level and LOW-level noise margins of the S-FED-based sense amplifier to the CMOS counterparts (∆NMH = 70 mV and ∆NML = 120 mV), respectively, can ensure the system-level operation stability of the former one. Subsequent to the attainment of an area-efficient, low-power, and high-speed S-FED-based sense amplifier (PDP = 187.75 × 10–18 W s) as a fundamental building block, devising an innovative integrate-and-fire neuron circuit based on S-FED paves the way to realize a new generation of neuromorphic architectures. To shed light on this context, an S-FED-based integrate-and-fire neuron circuit is designed and analyzed utilizing a sense amplifier and feedback loop to enhance spiking voltage and subsequent noise immunity in addition to an about fourfold increase in firing frequency compared to CMOS-based ones.

Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and Reliability

Rapid progress in the CMOS technology for the past 25 years has increased the vulnerability of processors towards faults. Subsequently, focus of computer architects shifted towards designing fault-tolerance methods for processor architectures. Concurrently, chip designers encountered high order challenges for designing fault tolerant processor architectures. For processor cores, redundancy-based fault tolerance methods for fault detection at core level, micro-architectural level ,thread level , and software level are discussed. Similar applicable redundancy-based fault tolerance methods for cache memory, and hardware accelerators are presented in the article. Recent trends in fault tolerant quantum computing and quantum error correction are also discussed. The classification of state-of-the-art techniques is presented in the survey would help the researchers to organize their work on established lines.

A wideband inductorless LNA exploiting three-stage feedback and thermal noise canceling

In inductorless wideband low-noise amplifier (LNA) design, input-matching is traded off with noise figure (NF). The common-source noise-canceling (CSNC) structure and the gyrator alleviate this trade-off, but the corresponding study is insufficient. This work combines the CSNC and gyrator and introduces a three-stage feedback loop to achieve high feedback gain while minimizing the added input capacitance. Hence, the trade-off between NF and input impedance matching is significantly released. Consequently, the lowest NF among inductorless LNAs was achieved, while an operation bandwidth of more than 3 GHz was obtained. Post-layout simulation results in 40 nm CMOS technology show that the circuit achieves an NF of 1.35 dB–1.7 dB while maintaining a wide operation bandwidth of 100 MHz to 3.46 GHz. As far as the author knows, this is the lowest NF inductorless LNAs have achieved. Furthermore, S21 of 10.9 dB and IIP3 (input third-order intercept point) of −5.6 dB m are obtained, and the circuit consumes 14.9 mW at a 1.2 V voltage supply. Being self-biased, the circuit core consumes only 0.0032 mm2 die area.

A 16-Gb/s 3-tap adaptive DFE in 12-nm FinFET CMOS technology

This paper introduces a 3-tap half-rate adaptive decision feedback equalizer (DFE) and a 2-D eye-opening monitor (EOM). A newly developed regenerating sampler (RG-sampler) with smaller setup time and ck2q time is integrated into the proposed DFE, enhancing its performance. To ensure greater robustness, the sign-sign least-mean-squares (SSLMS) algorithm with a pattern filter is employed to adapt DFE tap coefficients. The proposed 2-D EOM accurately captures the shape of the eye diagram using adjustment steps of 1.95ps and 7 mV in the horizontal and vertical directions, respectively. Additionally, by reusing analog components within the adaptive DFE and 2-D EOM modules, significant reductions in silicon area and power consumption are achieved. Implemented in 12-nm FinFET CMOS technology, the transceiver integrated with adaptive DFE and 2-D EOM operates at a data rate of 16 Gb/s over a channel with 30 dB loss at 8 GHz frequency. The proposed adaptive DFE and 2-D EOM occupy a total area of 0.00808 mm2. Measurement results demonstrate that following DFE adaptation, the eye height is 77 mV, and the eye width is 29.25ps at 16 Gb/s.

HIGHLY EFFICIENT INVERTER BLOCKS IN QCA TECHNOLOGY

QCA technology presented as a new paradigm to replace CMOS technology in the nanoscale. QCA technology represents binary information by cell polarization, not as a voltage level. The basic blocks in QCA technology are the majority gate and inverter. Efficient building blocks are important to get whole efficient circuits. This article aims to present novel configurations for the inverter block that offer advantages in terms of temperature tolerance, cell count, and area efficiency. Moreover, a Repeater gate with high efficiency is proposed to demonstrate their versatility. The proposed inverter has efficient improvements by 2%, 4.4%, 11%, and 17.5% over the best-reported inverter block at 10 K, 100 K, 150 K, and 200 K, respectively. The circuits presented in this study were designed and validated using QCADesigner software v 2.0.3, and the energy consumption of the proposed designs was assessed using QCAPro tools.

Enhancing Carrier Mobility in Monolayer MoS2 Transistors with Process-Induced Strain.

Two-dimensional electronic materials are a promising candidate for beyond-silicon electronics due to their favorable size scaling of electronic performance. However, a major challenge is the heterogeneous integration of 2D materials with CMOS processes while maintaining their excellent properties. In particular, there is a knowledge gap in how thin film deposition and processes interact with 2D materials to alter their strain and doping, both of which have a drastic impact on device properties. In this study, we demonstrate how to utilize process-induced strain, a common technique extensively applied in the semiconductor industry, to enhance the carrier mobility in 2D material transistors. We systematically varied the tensile strain in monolayer MoS2 transistors by iteratively depositing thin layers of high-stress MgOx stressor. At each thickness, we combined Raman spectroscopy and transport measurements to unravel and correlate the changes in strain and doping within each transistor with their performance. The transistors displayed uniform strain distributions across their channels for tensile strains of up to 0.48 ± 0.05%, at 150 nm of stressor thickness. At higher thicknesses, mechanical instability occurred, leading to nonuniform strains. The transport characteristics systematically varied with strain, with enhancement in electron mobility at a rate of 130 ± 40% per % strain and enhancement of the channel saturation current density of 52 ± 20%. This work showcases how established CMOS technologies can be leveraged to tailor the transport in 2D transistors, accelerating the integration of 2D electronics into a future computing infrastructure.

High-speed cascode cross-coupled CMOS dynamic comparator with auxiliary inverter pair

A dynamic comparator is the core element in high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. The majority of the dynamic comparators can only operate at high speeds when the input difference voltage is large enough. Due to the limited pre-amplifier gain, the comparators’ performance deteriorates at lower input difference voltages, which is not suitable for high-speed, high-resolution ADCs. A double-tail dynamic comparator with a pair of auxiliary inverters is proposed to alleviate this problem. With the proposed comparator, the pre-amplifier’s differential gain is increased, and the latch regeneration time is reduced by the auxiliary inverter pair resulting in faster comparison operations. The proposed comparator is designed, simulated, and compared with the latest topologies in 65 nm CMOS technology. The performance metrics such as delay, kickback noise, energy consumption per bit, rms noise, and power delay product are evaluated and compared with the state-of-the-art architectures. The proposed technique can be applied to any dynamic comparator that has differential signals at the output of the pre-amplifier stage. Simulations show that the auxiliary inverter pair improves the comparator’s speed by more than 10%.

Test result of the new ASD2 chips for Phase-II upgrade of the ATLAS MDT chambers at HL-LHC

For the Phase-II upgrade of the ATLAS Muon Spectrometer to High-Luminosity LHC, new front-end readout electronics for the Monitored Drift Tube chambers is required, as the old one no longer meets the demands. The first stage in the Monitored Drift Tubes readout chain is the Amplifier-Shaper-Discriminator chip. For the upgrade, the new ASD2 ASIC chip in IBM 130 nm CMOS technology has been developed. For the ATLAS experiment, 80000 ASD2 chips are produced, which have to be tested before integration in order to obtain the required 50000 well-performing chips in the end. Using a prototype tester board and pre-production ASD2 chips, the overall performance and the influence on programmable parameters is investigated. Based on these results, 1775 production chips are tested to define final optimized cut values for the automated production testing of all chips in the company.

An Efficient Design of a Three-Layer Magnitude Comparator for Nano-Scale IoT Applications Based on QCA Technology

The difficulty of further downscaling CMOS technology arises from the restriction of feature size reduction. Quantum-dot cellular automata (QCA) emerges as a paradigm-shifting successor to CMOS, heralding a new era of effective digital design at the nanoscale. It stands as an enticing frontier in nanoscale computing, with limited exploration into the realms of smaller QCA cells, elevated processing speeds, and more compact area requirements across diverse circuits. Within the intricate landscape of decoding circuits and process controllers, the binary comparator assumes a role of paramount significance. On the other hand, the quickly developing Internet of Things (IoT) market aims to produce high-speed, low-power gadgets. A comparator is a crucial component in the analog-to-digital conversion process used by IoT devices. In order to meet the power and latency requirements of IoT devices, a high-speed, low-power comparator is greatly required. Consequently, the strategic design of comparators within the QCA framework has ascended to a position of heightened importance in cutting-edge research. This study undertakes the formidable task of conceiving QCA-centric designs for MV32, the majority gate, and the inverter gate, thereby contributing to the development of a sophisticated multi-layered comparator architecture for IoT devices. In the realization of a three-layer comparator implemented in QCA, we attain an impressive feat—a minimal clock zone demanding only a singular clock pulse coupled with exceptional compaction (measuring at a mere 0.03 μm2). Experimental revelations corroborate the substantial advancement of the proposed design over traditional methodologies, particularly in terms of circuit area, cell count, and clock efficiency.

Hardware software co-design for leveraging STDP in a memristive neuroprocessor

Abstract In neuromorphic computing, different learning mechanisms are being widely adopted to improve the performance of a specific application. Among these techniques, Spike-Timing-Dependent Plasticity (STDP) stands out as one of the most favored. STDP is simply managed by the temporal information of an event, which is biologically inspired. However, most of the prior works on STDP are focused on circuit implementation or software simulation for performance evaluation. Previous works also lack a comparative analysis of the performances of different STDP implementations. This study aims to provide a comprehensive assessment of STDP, centering on the performance across various applications such as classification (static and temporal datasets), control, and reservoir computing. Different applications necessitate distinct STDP configurations to achieve optimal performance with the neuroprocessor. Additionally, this work introduces an Application-Specific Integrated Circuit (ASIC) design of STDP circuitry. The design is based on current-controlled memristive synapse principles and utilizes 65nm CMOS technology from IBM. The detailed presentation includes circuitry specifics, layout, and performance parameters such as energy consumption and design area.

Neuro-inspired hardware solutions for high-performance computing: A TiO2-based nano-synaptic device approach with backpropagation

Computer-based machine learning algorithms that produce impressive performance results are computationally demanding and thus subject to high energy consumption during training and testing. Therefore, compact neuro-inspired devices are required to achieve efficiency in hardware resource consumption for the smooth implementation of neural network applications that require low energy and area. In this paper, learning characteristics and performances of the nanoscale titanium dioxide (TiO2) based synaptic device have been analyzed by implementing it in the hardware-based neural network for digit classification. Our model is experimentally validated by using 32-nm CMOS technology and the results demonstrate that the model provides high computational ability with better accuracy and efficiency in resource consumption with low energy and less area. The proposed model exhibits 20% energy gain and 16.82% accuracy improvement and 18% less total latency compared to the state-of-the-art Ag:Si synaptic device-based neural network. Furthermore, when compared to the software-based (i.e., computer-based) implementation of neural networks, our TiO2-based model not only achieved an impressive accuracy rate of 90.01% on the MNIST dataset but also did so with reduced energy consumption. Consequently, our model, characterized by a low hardware implementation cost, emerges as a promising neuro-inspired hardware solution for various neural network applications. The proposed model has further demonstrated outstanding performance in experiments involving both the MNIST and Fisher’s Iris datasets. On the latter dataset, the model exhibited notable precision (94.5%), recall (91.5%), and an impressive F1-score (92.9%), accompanied by a commendable accuracy rate of 93.04%.

ASIC Design and Implementation of Automated Coffee and Tea Brewing System with FPGA Validation

Abstract: This paper presents a pioneering approach to enhance the efficiency of automated coffee and tea brewing systems through the integration of an ASIC-GDSII and FPGA validation. Leveraging the power of 45nm CMOS Technology, the design achieves substantial reductions in area, power consumption, and delay. The Verilog HDL code undergoes meticulous verification using Cadence tools like Genus and Innovus, ensuring optimal design performance. Innovus validates timing constraints, ensuring adherence to acceptable delay parameters. The resulting compact design not only minimizes power consumption but also effectively addresses leakage issues. These comprehensive optimizations meet stringent performance, area, and power requirements, elevating the operational efficiency of automated brewing systems. Furthermore, the control algorithm is synthesized and implemented using Xilinx's ISE Design Suite, followed by validation on SPARTAN 6 FPGA, providing invaluable insights for future synthesis and implementation endeavors.

Chip-Based Electronic System for Quantum Key Distribution

Quantum Key Distribution (QKD) has garnered significant attention due to its unconditional security based on the fundamental principles of quantum mechanics. While QKD has been demonstrated by various groups and commercial QKD products are available, the development of a fully chip-based QKD system, aimed at reducing costs, size, and power consumption, remains a significant technological challenge. Most researchers focus on the optical aspects, leaving the integration of the electronic components largely unexplored. In this paper, we present the design of a fully integrated electrical control chip for QKD applications. The chip, fabricated using 28 nm CMOS technology, comprises five main modules: an ARM processor for digital signal processing, delay cells for timing synchronization, ADC for sampling analog signals from monitors, OPAMP for signal amplification, and DAC for generating the required voltage for phase or intensity modulators. According to the simulations, the minimum delay is 11ps, the open-loop gain of the operational amplifier is 86.2 dB, the sampling rate of the ADC reaches 50 MHz, and the DAC achieves a high rate of 100 MHz. To the best of our knowledge, this marks the first design and evaluation of a fully integrated driver chip for QKD, holding the potential to significantly enhance QKD system performance. Thus, we believe our work could inspire future investigations toward the development of more efficient and reliable QKD systems.

Weight‐Reconfigurable Neuromorphic Computing Systems for Analog Signal Integration

AbstractOwing to the necessity of high computation amounts has emerged, interest in a neuromorphic computing system has significantly increased as a compelling alternative to conventional CMOS technology. This paper presents a neuromorphic hardware algorithm to finely reconfigure multi‐input signal processing, which can be implemented as an advanced processor for diverse external information, and the hydrogen explosion risk assessment system is demonstrated as a proof of concept. Hydrogen concentration and temperature are used as sensory inputs for the signal integration and the precise values of them are determined by offsetting the effect of temperature on the electrical signal from the hydrogen sensor through a sensor circuit. Each signal is then updated by the weight control circuit and converted into a postsynaptic current to represent the hydrogen explosion risk using a multi‐input artificial synapse. This simplicity of the circuitry renders the fabrication of all components and circuits compatible with simple inkjet printing methods, enabling cost‐effective and high‐throughput manufacturing. Additionally, the real‐time demonstration of the neuromorphic computing system is successfully conducted, offering insights into the practical application of neuromorphic computing.

Self-cascode and self-biased Dickson charge pump for fast locking wide lock range PLL with reduced phase noise

The charge pump is a fundamental component in phase-locked loop (PLL) circuits, essential for generating a control voltage that adjusts the frequency and phase of the voltage-controlled oscillator (VCO) to match the input reference signal. The self-cascode and self-biased Dickson charge pump architecture presented in this work addresses several key challenges encountered in conventional PLL designs. By integrating self-cascode techniques, the charge pump exhibits enhanced charging and discharging capabilities, enabling faster locking times essential for wide lock range PLLs. This comprehensive approach offers a compact and integrated solution that simultaneously enhances locking speed, widens the lock range, reduces phase noise, and simplifies design complexity, making it highly suitable for demanding applications in communication systems, radar, and wireless technologies. The novel CP is implemented in 90-nm CMOS technology with a 1.0-V supply voltage. It is integrated with a phase-locked loop (PLL) that has a lock time of 1.0 us, a negligible reference spur, and an average power consumption of 34.7 mW. The PLL is having a wide lock range of 0.98 GHz to 2.98 GHz with a center frequency of 1.54 GHz where the phase noise is calculated to be −100.9 dBc/Hz at 1 MHz offset frequency. This makes the PLL compatible with both GSM having 1.8 GHz and Wi-Fi having 2.8 GHz frequency bands. The proposed PLL is also capable of operating at a wide range of temperatures (−27 °C, 0 °C, 27 °C, 84 °C) and at various corners (NN, FS, SF, SS, FF) making it reliable in adverse circumstances.

Ultra-Low Power 9T FinFET Based SRAM Cell for IoT Applications

The rapid proliferation of Internet of Things (IoT) devices has escalated the demand for energy-efficient memory solutions. The development of SRAM (Static Random-Access Memory) has gathered significant attention, particularly for low-power applications and portable devices. This research introduces a novel approach to ensure robust performance and operational integrity, all while adhering to stringent power constraints amidst process and temperature fluctuations. This quest for alternative nano-devices has been ignited by the scaling and channel control challenges intrinsic to CMOS technology. Among the array of alternatives, including FinFETs, TFETs, and CNTFETs, FinFETs have emerged as strong contenders. FinFET SRAMs contribute to the ongoing drive for electronic devices to become more compact and energy-efficient. They offer a distinct advantage as a promising CMOS substitute, attributed to their high performance, stability, with low power consumption characteristics at the nanoscale. The study proposes an ultra-low power 9T FinFET based SRAM cell meticulously designed for IoT applications. Leveraging the unique attributes of FinFET based 9T cell, the proposed SRAM cell is tailored to achieving minimal power consumption while maintaining inherent stability. The study assesses the performance of the proposed SRAM cells for power dissipation, stability, speed, and energy efficiency, and compares them with existing SRAM structures. The results are obtained through the Monte Carlo simulation technique, which evaluates circuit performance under specified conditions. The study achieves remarkable efficiency gains with 9T SRAM cells compared to other configurations. Additionally, the reduced read and write access times facilitate expedited data retrieval and storage operations.  

Design and validation of a piezoelectric diaphragm micropump for drug delivery

There is a common eye ailment called Dry Eye Disease (DED) that causes symptoms of discomfort, visual disturbance, and tear film instability, which cause damage to the ocular surface. For treatment of this illness, the application of artificial tear fluid is usually prescribed. This work presents the design process of a piezoelectric micropump to become part of an automatic pumping system for delivering artificial tear fluid to people suffering from DED. Low polarizing voltage, portability, and achieving a variable output flow rate in the range of 1 µl/min, which is the necessary range needed by a person suffering from DED, are the focus of this design. Standard microfabrication techniques widely used in the CMOS industry and for MEMS development will be used for manufacturing the proposed micropump. For this reason, the materials and manufacturing processes involved must be CMOS-compliant. For the piezoelectric actuator, zinc oxide (ZnO) was selected due to its compatibility with CMOS technology and because it is readily available in thin film form through a sputtering process. Other materials involved in the device are silicon and aluminum. The design was validated through finite element analysis software, COMSOL Multiphysics®. The maximum flow rate obtained by a single micropump device was 2.51µl/min operating at 20V peak with a frequency of 900Hz. Also, the flow rate is controllable through variations in frequency, thus making it suitable for the application previously described.

A 400 V Buck Converter integrated with Gate-Drivers and low-voltage Controller in a 25–600 V mixed-mode SiC CMOS technology

A 400 V Buck Converter integrated with Gate-Drivers and low-voltage Controller in a 25–600 V mixed-mode SiC CMOS technology

Through-polymer, via technology-enabled, flexible, lightweight, and integrated devices for implantable neural probes

In implantable electrophysiological recording systems, the headstage typically comprises neural probes that interface with brain tissue and integrated circuit chips for signal processing. While advancements in MEMS and CMOS technology have significantly improved these components, their interconnection still relies on conventional printed circuit boards and sophisticated adapters. This conventional approach adds considerable weight and volume to the package, especially for high channel count systems. To address this issue, we developed a through-polymer via (TPV) method inspired by the through-silicon via (TSV) technique in advanced three-dimensional packaging. This innovation enables the vertical integration of flexible probes, amplifier chips, and PCBs, realizing a flexible, lightweight, and integrated device (FLID). The total weight of the FLIDis only 25% that of its conventional counterparts relying on adapters, which significantly increased the activity levels of animals wearing the FLIDs to nearly match the levels of control animals without implants. Furthermore, by incorporating a platinum-iridium alloy as the top layer material for electrical contact, the FLID realizes exceptional electrical performance, enabling in vivo measurements of both local field potentials and individual neuron action potentials. These findings showcase the potential of FLIDs in scaling up implantable neural recording systems and mark a significant advancement in the field of neurotechnology.