CMOS Technology Node Research Articles

Selecting alternative metals for advanced interconnects

Interconnect resistance and reliability have emerged as critical factors limiting the performance of advanced CMOS circuits. With the slowdown of transistor scaling, interconnect scaling has become the primary driver of continued circuit miniaturization. The associated scaling challenges for interconnects are expected to further intensify in future CMOS technology nodes. As interconnect dimensions approach the 10 nm scale, the limitations of conventional Cu dual-damascene metallization are becoming increasingly difficult to overcome, spurring over a decade of focused research into alternative metallization schemes. The selection of alternative metals is a highly complex process, requiring consideration of multiple criteria, including resistivity at reduced dimensions, reliability, thermal performance, process technology readiness, and sustainability. This Tutorial introduces the fundamental criteria for benchmarking and selecting alternative metals and reviews the current state of the art in this field. It covers materials nearing adoption in high-volume manufacturing, materials currently under active research, and potential future directions for fundamental study. While early alternatives to Cu metallization have recently been introduced in commercial CMOS devices, the search for the optimal interconnect metal remains ongoing.

A wideband high-PSR OCL LDO using a gain-relaxed OTA featuring dynamic complex zeros frequency compensation

This article proposes an Output-Capacitor-Less (OCL) Low-Dropout (LDO) regulator with an assisted positive feedback loop technique, which mimics a negative resistance, along with a single common-gate stage. Conventional techniques utilize multistage high-gain OTA to achieve a high DC loop gain. However, such an OTA suffers from high power consumption and sophisticated frequency compensation mechanisms. Instead, the use of a single-stage relatively low-gain OTA helps to extend the bandwidth. Then, the overall DC loop gain is maximized by the proposal of a novel negative resistance circuit. To further improve the PSR, a bulk-driven ripple canceling path that is insensitive to process corners is proposed making the LDO suitable for high-PSR applications. Stability is another challenge in the design of OCL LDOs due to its associated complex poles. We propose a new frequency compensation technique by introducing two complex zeros to eliminate these complex poles. Hence, the overall stability is improved. Since these complex poles location vary from light to heavy loads, the proposed zeros dynamically change accordingly. Besides, this suggested mechanism has been analyzed using the generalized time-and-transfer constants (TTCs) circuit analysis technique. Under heavy load conditions, the suggested LDO has attained phase and gain margins of 62.8° and 29 dB, respectively. Moreover, Monte Carlo simulations along with process and temperature variations have been investigated to prove the reliability of such a frequency compensation technique. The proposed LDO has been implemented in 65 nm CMOS technology node with a short pass transistor length of 100nm. The simulation results reveals that the LDO draws 299.4μA of quiescent current under light load conditions and 296.8μA under heavy load conditions (including the bandgap voltage reference). The suggested LDO functions at 1.2V supply voltage, delivers 0.93V output voltage and can handle a load current up to 10mA with load regulation of 17μV/mA, line regulation of 2.22mV/V, and PSR of −48.7dB at low frequencies. The PSR at 1MHz is at least −32.5dB which is superior to the reported recent LDOs.

Defect-Free SiGe/Si Multistacks for Next-Generation CFET Architectures

The advancement of CMOS technology nodes demands increasingly complex device architectures. In this frame, the epitaxial deposition of complicated SiGe/Si multistacks presents a significant technology challenge required to enable such cutting-edge devices. This work presents the characterization of defect-free multistacks featuring SiGe layers with two possible Ge concentrations and incorporating either two or six stacked Si nanosheets. Our comprehensive analysis reveals good matching with the nominal structures and demonstrates remarkable repeatability of the Si channels. Furthermore, the multistacks exhibit ideal surface morphology, crucial for subsequent processing steps. Notably, the study also highlights optimal wafer-to-wafer repeatability, a key factor in ensuring consistent performance across large-scale production.

Embedded FPGA developments in 130 nm and 28 nm CMOS for machine learning in particle detector readout

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called “FABulous” was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Further development of the eFPGA technology and its application to collider detector readout is discussed.

Ditching the Queue: Optimizing Coprocessor Utilization with Out-of-Order CPUs on Compact Systems on Chip

The growing demand for high-performance and energy-efficient processing in edge-oriented Systems-on-Chip is driving the adoption of dedicated integrated circuits that accelerate computationally intensive workloads. To minimize area and performance overhead, low-power, general-purpose CPUs are often tightly coupled with domain-specific coprocessors implementing custom instructions, thereby delivering higher throughput and reduced memory traffic. However, commonly used in-order CPUs are not optimized for instruction-level parallelism, leading to stalls in the instruction stream while waiting for long-latency coprocessor operations and under-utilization of the coprocessor while executing other instructions. This work investigates the benefits of replacing simple in-order cores with a more complex out-of-order architecture to dynamically schedule instructions for the main core and coprocessor, optimizing resource utilization and reducing execution time. To ensure generality, an in-depth analysis was carried out by offloading instructions to a custom dummy coprocessor capable of emulating iterative and pipelined operations with arbitrary latency. Various workloads simulating real-world applications were executed on two variants of an open-source microcontroller equipped with a recent out-of-order core and the state-of-the-art CV32E40X in-order core, respectively. Results from Register Transfer Level simulations show that the former configuration executes up to 60% more instructions per cycle, with a modest 12% system area overhead on a 65 nm CMOS technology node.

From silicon shield to carbon lock‐in? The environmental footprint of electronic components manufacturing in Taiwan (2015–2020)

AbstractTaiwan plans to rapidly increase its industrial production capacity of electronic components while concurrently setting policies for its ecological transition. Given that the island is responsible for the manufacturing of a significant part of worldwide electronics components (including the most advanced CMOS technology nodes), the sustainability of the Taiwanese electronics industry is of critical interest. In this paper, we survey the environmental footprint of 16 Taiwanese electronic components manufacturers (ECMs) using corporate sustainability responsibility reports. Based on data from 2015 to 2020, we find out that the sample of ECMs in this study increased its greenhouse gas emissions by 7.5% per year, its final energy and electricity consumption by 8.8% and 8.9%, and its water usage by 6.1%. We show that the volume of manufactured electronic components and the environmental footprint compiled in this study are strongly correlated, which suggests that relative efficiency gains are not sufficient to curb the overall environmental footprint of ECMs on the island. Given the critical nature of the electronics industry for Taiwan's geopolitics and economics, the observed increase of energy consumption, and the slow renewable energy roll‐out, Taiwan could face a carbon lock‐in situation which will most likely prevent the achievement of carbon reduction goals and sustainability policies on the island.

Nanoscale single-electron box with a floating lead for quantum sensing: Modeling and device characterization

We present an in-depth analysis of a single-electron box (SEB) biased through a floating node technique that is common in charge-coupled devices. The device is analyzed and characterized in the context of single-electron charge sensing techniques for integrated silicon quantum dots (QD). The unique aspect of our SEB design is the incorporation of a metallic floating node, strategically employed for sensing and precise injection of electrons into an electrostatically formed QD. To analyze the SEB, we propose an extended multi-orbital Anderson impurity model (MOAIM), adapted to our nanoscale SEB system, that is used to predict theoretically the behavior of the SEB in the context of a charge sensing application. The validation of the model and the sensing technique has been carried out on a QD fabricated in a fully depleted silicon on insulator process (FD-SOI) on a 22-nm CMOS technology node. We demonstrate the MOAIM's efficacy in predicting the observed electronic behavior and elucidating the complex electron dynamics and correlations in the SEB. The results of our study reinforce the versatility and precision of the model in the realm of nanoelectronics and highlight the practical utility of the metallic floating node as a mechanism for charge injection and detection in integrated QDs. Finally, we identify the limitations of our model in capturing higher order effects observed in our measurements and propose future outlooks to reconcile some of these discrepancies.

Qualitative data augmentation for performance prediction in VLSI circuits

Various studies have shown the advantages of using Machine Learning (ML) techniques for analog and digital IC design automation and optimization. Data scarcity is still an issue for electronic designs, while training highly accurate ML models. This work proposes generating and evaluating artificial data using generative adversarial networks (GANs) for circuit data to aid and improve the accuracy of ML models trained with a small training data set. The training data is obtained by various simulations in the Cadence Virtuoso, HSPICE, and Microcap design environment with TSMC 180 nm and 22 nm CMOS technology nodes. The artificial data is generated and tested for an appropriate set of analog circuits and digital cells. The experimental results show that the proposed artificial data generation significantly improves ML models and reduces the percentage error by more than 50% of the original percentage error, which were previously trained with insufficient data. Furthermore, this research aims to contribute to the extensive application of AI/ML in the field of VLSI design and technology by relieving the training data availability-related challenges.

Efficient ASIC Architecture for Low Latency Classic McEliece Decoding

Post-quantum cryptography addresses the increasing threat that quantum computing poses to modern communication systems. Among the available “quantum-resistant” systems, the Classic McEliece key encapsulation mechanism (KEM) is positioned as a conservative choice with strong security guarantees. Building upon the code-based Niederreiter cryptosystem, this KEM enables high performance encapsulation and decapsulation and is thus ideally suited for applications such as the acceleration of server workloads. However, until now, no ASIC architecture is available for low latency computation of Classic McEliece operations. Therefore, the present work targets the design, implementation and optimization of a tailored ASIC architecture for low latency Classic McEliece decoding. An efficient ASIC design is proposed, which was implemented and manufactured in a 22 nm FDSOI CMOS technology node. We also introduce a novel inversionless architecture for the computation of error-locator polynomials as well as a systolic array for combined syndrome computation and polynomial evaluation. With these approaches, the associated optimized architecture improves the latency of computing error-locator polynomials by 47% and the overall decoding latency by 27% compared to a state-of-the-art reference, while requiring only 25% of the area.

FinFET Technology: Modeling and RF Characterization for 5nm Node Technology: A Review

The study offers new methods for understanding and simulating the radiofrequency, analog, and thermal characteristics of the FinFET at the 5nm CMOS technology node. The results of the thermal assessment show that changes in temperature have an effect on the threshold voltage and sub-threshold slope (SS). The maximum oscillation frequency and cut-off frequency of an n-FinFET RF device with a single gate contact are revealed by the RF investigation. Additionally, the study provides information about the device-level temperature sensitivity of the analog and RF Figures of Merit (FoMs) for the 5nm technology. The industry-standard BSIM-CMG model is adjusted to include the effects of self-heating (SH) and parasites in order to improve model accuracy. The updated BSIM-CMG model increases accuracy by taking self-heating and parasite effects into account. Effective heat pathways for lowering junction temperature are found by employing vias on silicon and stacks of conductive materials made of metal. It should be remembered, though, that using these heat pathways could raise parasitic capacitance and negatively impact the circuit's functionality. Keywords: RF Characterization, Thermal Impact, Self-Heating, Figure of Merit, FinFET, Analog Characteristics.

MDCIM: MRAM-Based Digital Computing-in-Memory Macro for Floating-Point Computation with High Energy Efficiency and Low Area Overhead

Computing-in-Memory (CIM) is a novel computing architecture that enormously improves energy efficiency and reduces computing latency by avoiding frequent data movement between the computation and memory units. Currently, digital CIM is regarded as more suitable for high-precision operations represented in floating-point arithmetic, as it is not limited by the bit width of ADC/DAC in analog CIM. However, the development of DCIM still faces two problems: On the one hand, mainstream SRAM-based DCIM memory cells introduce large area overheads, which contain at least six transistors per cell. On the other hand, existing DCIM solutions can only support the computing precision up to FP32, failing to meet the demands of high-accuracy application scenarios. To overcome these problems, this work designs a novel SOT-MRAM-based digital CIM macro (MDCIM) with higher area/energy efficiency and achieves double-precision floating-point (FP64) computation with a modified fused multiply–accumulate (FMA) module. The proposed design is synthesized with a 55 nm CMOS technology node, achieving 0.62 mW power consumption, 26.9 GOPS/W, and 0.332 GOPS/mm2 energy efficiency at 150 MHz with 1.08 V supply. Circuit level simulation results show that the MDCIM can achieve higher area utilization compared to previous SRAM-based CIM designs.

Adaptive STDP-based on-chip spike pattern detection.

A spiking neural network (SNN) is a bottom-up tool used to describe information processing in brain microcircuits. It is becoming a crucial neuromorphic computational model. Spike-timing-dependent plasticity (STDP) is an unsupervised brain-like learning rule implemented in many SNNs and neuromorphic chips. However, a significant performance gap exists between ideal model simulation and neuromorphic implementation. The performance of STDP learning in neuromorphic chips deteriorates because the resolution of synaptic efficacy in such chips is generally restricted to 6 bits or less, whereas simulations employ the entire 64-bit floating-point precision available on digital computers. Previously, we introduced a bio-inspired learning rule named adaptive STDP and demonstrated via numerical simulation that adaptive STDP (using only 4-bit fixed-point synaptic efficacy) performs similarly to STDP learning (using 64-bit floating-point precision) in a noisy spike pattern detection model. Herein, we present the experimental results demonstrating the performance of adaptive STDP learning. To the best of our knowledge, this is the first study that demonstrates unsupervised noisy spatiotemporal spike pattern detection to perform well and maintain the simulation performance on a mixed-signal CMOS neuromorphic chip with low-resolution synaptic efficacy. The chip was designed in Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm CMOS technology node and comprises a soma circuit and 256 synapse circuits along with their learning circuitry.

CMOS Scaling Challenges for High Performance and Low Power applications facing Reliability Criteria towards the Decananometer range

The huge improvements in integrated circuits manufacturing has faced great challenges between process optimization, performance requirements and the trade-off between low power operation and reliability for long term use. Both the variability at time zero and the time variability due to external constraints and aging phenomena make mandatory the validation of the CMOS technology nodes from device to circuits and products under operation. While High-K Metal-Gate (HKMG) offered good compromises down to 28nm gate-length, the move to Fully Depleted Silicon on Insulator (FDSOI) allows to further scale the dimension down to 14nm effective gate-length with ultra-thin equivalent gate-oxide thickness (EOT) of 1.35 nm. This has been obtained guarantying a small subthreshold slope for switching, small drain-induced barrier lowering (DIBL) for limited short-channel effect (SCE) and excellent current drivability thanks to a proper gate-stack with HfO2/SiON optimization and adapted rapid thermal processing and annealing. We give new insights to determine first the performance with temperature, the process variability impact at time zero and the robustness of CMOS nodes submitted to interface traps, oxide charge and recoverable traps. Their role is analysed using accelerated DC and AC experiments in devices to SRAM cell and array, focusing on the balance between hot-carrier and bias temperature damage. This allows to guaranty the technology robustness, speed performance and limited power consumption for product qualification.

Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell

This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and VDD collapse. The impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and VDD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. The impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. The deviation of HSNM for 15°C to 55°C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. The proposed SRAM cell is designed at a 22 nm CMOS technology node and verified in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer.

Formula omitted] Parallel paths for non-linearity mitigation in ring oscillator based analog-to-digital conversion

A new technique to mitigate the non-linearity of the ring oscillator is introduced and described for open loop ring oscillator based analog-to-digital conversion. The idea is based on limiting the input signal amplitude to make the ring oscillator work in a more linear range, thus improving the SNDRpeak. The dynamic range is preserved by means of several parallel digitization channels injected in phase. Passive interpolation between the channels is exploited to ensure a uniform distribution of the output phases. The idea is validated through system and schematic simulations using a 65 nm CMOS technology node, towards high bandwidth applications such as new communication protocols or Internet-of-Things environments. A SNDR of 63 dB is achieved with four digitization parallel channels with an input signal swing of differential 600 mVpp in a bandwidth of 50 MHz. PVT variations and mismatch effects are checked and no degradation in the final resolution is observed. Therefore, the proposal shows a high robustness without requiring any type of calibration. Additionally it is proven that the architecture consumes less than half of the power consumed by the conventional approach, leading to a higher power efficiency.

A Tunable Gain and Bandwidth Low-Noise Amplifier with 1.44 NEF for EMG and EOG Biopotential Signal

This paper presents a low-noise inverter-based current-mode instrumentation amplifier with tunable gain and bandwidth for electromyogram (EMG) and electrooculogram (EOG) biopotential signals, targeting low input noise while maintaining low power consumption. The gain tuning method is based on pseudo-resistors, whereas the bandwidth is tunable due to a varactor system that is controlled by the same control voltage that tunes the gain. The circuit was designed and manufactured using the 110 nm UMC CMOS technology node, occupying an area of 0.624 mm2. The circuit presents a functioning mode for each biopotential signal with different characteristics, for the EMG a gain of 34.7 dB and a bandwidth of 1412 Hz was measured, with an input referred noise of 1.407 μV which matches a noise efficiency factor of 1.44. The EOG mode achieves a 39.5 dB gain and a 22.4 Hz bandwidth while presenting an input-referred noise of 0.829 μV corresponding to a noise efficiency factor of 6.37. For both modes, the supply voltage is 1.2 V and the circuit consumes 1 μA.

Electronically Tunable Circuit Realization of Multimemelement Function Simulator and Its Application to Chaos Generation

The paper presents a very compact dual memelement function simulator using only one active building block (ABB) namely modified Voltage Differencing Current Conveyor (mVDCC), two MOSFETs, and two grounded passive elements. The proposed emulator can realize the function of memristor, meminductor, and memcapacitor-dual, which can be achieved via the proper selection of only one grounded passive element as R, L, and C. The proposed multimemelement emulator (MME) is fully electronically tunable and exhibits nonvolatile storage property. Also, the emulator can exhibit memristor response up to MHz range of frequency. The PSPICE-generated simulation results verify the working of the given floating MME for the realization of all three elements using 0.18 [Formula: see text]m CMOS technology node. The presented CMOS layout shows that the proposed emulator implementation occupies an area of [Formula: see text]. Along with the CMOS-based structure, the presented MME is verified through commercial ICs-based implementation. The given application example of the chaotic circuit also proves the working of the presented MME.

MPEG/H256 video encoder with 6T/8T hybrid memory architecture for high quality output at lower supply

The use of Multimedia video content is increased rapidly in the past decade, and most multimedia video content is used by mobile phone users. Multimedia video processing consumes significant power during video compression, and thus low power multimedia video compression is essential for battery operated devices. Moving Picture Experts Group (MPEG) Video encoding is giving a higher compression rate and low bandwidth requirement. Conventional MPEG Video encoding architecture uses the conventional 6T memory cells to store video frames for further compression processing. The failure probability of 6T cells is significantly large (0.0988 at 600 mV supply voltage), leading to a decrease in the output quality of the encoded video. From the hybrid memory matrix formulation, it is calculated that storing higher-order MSB bits in highly stable memory cells will provide high-quality video encoding processing as compared to the conventional technique because the human eye is more susceptible to higher-order luminance bits. Hence, in this research work instant of using conventional 6T memory cells during video encoding processing, a unique Hybrid 6T/8T memory architecture is proposed, where the 8-bit Luminance pixels are stored favourably in consonance with their effect on the output quality. The higher order luminance bits (MSB’s) require high stability and thus these bits are stored in the 8T bit cells and the remaining bits (LSB’s) are stored in the conventional 6T bit cells for high-quality video encoding processing. This research article also proposes a separate memory peripheral circuitry for hybrid memory architecture for video encoding techniques. In addition, this article proposes a unique architecture for parallel video processing with the use of a hybrid pixel memory array. The failure probability of 6T and 8T at the worst failure corner (FS corner for read and SF corner for write) is simulated for 30000 Monte-Carlo simulations points at 45 nm CMOS technology node using CADENCE EDA tool. For the simulation work here, a standard Common Intermediate Format/Quarter Common Intermediate Format (CIF/QCIF) Coastguard video sample is used and for output quality here average PSNR method is used and simulation work is performed using the MATLAB tool.The worst PSNR for conventional 6T memory array and Hybrid memory array at 600 mV supply voltage shows improvement in worst minimum PSNR as 6.43 dB is calculated. 30% less power consumption to conventional memory architecture.

Radiation-tolerant all-digital clock generators for HEP applications

The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. Both LC oscillator and ring oscillator-based all-digital PLL/CDR blocks for front-end ASICs were studied, designed, manufactured and characterized. Their design, the hardening considerations, as well as the performance obtained with these circuits are presented in this article.

Reduction of variation and leakage in wide fan-in OR Logic domino gate

In this paper, a novel domino gate is proposed to decrease the process variability and leakage current with enhanced noise margin for wide fan-in OR logic. The process variation is decreased by reducing the transconductance of the keeper transistor, whereas the subthreshold leakage current is decreased by redesigning the evaluation network. In addition, a keeper-controlled network is developed to control the switching activity of keeper which eventually reduces the power dissipation. Further, extensive analysis of reliability is accomplished against the process, voltage, and temperature. Further, 64-word*32bit Read ported register file is designed to show the supremacy of proposed domino gate over the conventional domino. All proposed circuits are designed, simulated and verified using SPECTRE simulator in CADENCE VIRTUOSO at 45 nm CMOS technology node. The results reveal that power and delay variability are reduced by 55% and 57%, whereas noise margin is improved by 74% with respect to reported conventional domino. Hence, the analysis suggests that proposed domino circuit can be useful to implement deep submicron low power VLSI circuits.