CMOS Technology Research Articles

Test measurements of an ASIC for X-ray material discrimination by using on-chip time domain integration and a CdTe sensor

Using time-domain integration (TDI) and a two-dimensional sensor is beneficial for X-ray imaging of moving objects. Applying on-chip instead off-chip TDI decreases the required data throughput between an ASIC and the backend several times [1]. This, in turn, allows us to significantly simplify the ASIC itself as well as the backend.We present the results of test measurements of an ASIC dedicated for X-ray material discrimination by using on-chip TDI and a CdTe sensor.The main part of the ASIC is an 192 × 64 pixel matrix. The pixel size is 100 μm × 100 μm, so the chip size is approximately 6.7 mm × 2 cm. The chip is manufactured in a 130 nm CMOS technology with 8 metal layers. A single pixel analog front-end consists of a charge-sensitive amplifier, a shaper, and three discriminators followed by counters. The test was conducted with a 0.75 mm thick CdTe sensor.First, we show the results of the discriminator offset correction followed by the evaluation of the pixel analog front-end gain and noise conducted with single energy radiation. Next, the results of moving objects imaging are obtained by using an industrial X-ray machine for food inspection (continuous energy spectrum). This is carried out to present an example of the image and evaluate the image signal to noise ratio for different energy discriminator thresholds, sensor bias voltages, detector module temperatures and object speeds.

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology

Multi-phase time-zooming high-precision ultrasonic water flow meter

In this study, we have developed a high-precision ultrasonic water flow meter with a 0.18 μm standard CMOS technology. Three methods are proposed to improve the performance: implementation of an active bandpass filter, threshold voltage optimization, and integration of a multi-phase time-zooming technique. The active bandpass filter effectively reduces noise in the received signal, thereby contributing to the overall accuracy of propagation measurements. Based on a threshold voltage generator, our proposed system identifies the optimum threshold voltage, ensuring robust noise durability. Furthermore, we have extended the conventional time-zooming technique by incorporating multiple phases of internal clocks. This innovative multiphase time-zooming technique offers a theoretical improvement in time resolution. The results demonstrate a remarkable suppression of flow rate measurement variations, achieving an impressive reduction to 1/10 of the original values. This affirms the effectiveness of the developed ultrasonic water flow meter in ensuring precise and reliable flow rate measurements.

Voltage-based magnetization switching and reading in magnetoelectric spin-orbit nanodevices

As CMOS technologies face challenges in dimensional and voltage scaling, the demand for novel logic devices has never been greater, with spin-based devices offering scaling potential, at the cost of significantly high switching energies. Alternatively, magnetoelectric materials are predicted to enable low-power magnetization control, a solution with limited device-level results. Here, we demonstrate voltage-based magnetization switching and reading in nanodevices at room temperature, enabled by exchange coupling between multiferroic BiFeO3 and ferromagnetic CoFe, for writing, and spin-to-charge current conversion between CoFe and Pt, for reading. We show that, upon the electrical switching of the BiFeO3, the magnetization of the CoFe can be reversed, giving rise to different voltage outputs. Through additional microscopy techniques, magnetization reversal is linked with the polarization state and antiferromagnetic cycloid propagation direction in the BiFeO3. This study constitutes the building block for magnetoelectric spin-orbit logic, opening a new avenue for low-power beyond-CMOS technologies.

The data acquisition system for the PANDA Micro-Vertex Detector

The PANDA (antiProton ANnihilation at DArmstadt) experiment will study the strong interaction in annihilation reactions between an antiproton beam and a stationary cluster jet target. The PANDA detector will be composed of several sub-detectors designed for tracking, particle identification and calorimetry. The Micro-Vertex Detector (MVD) is the innermost part of the tracking system surrounding the interaction region, which is designed for precise vertex and tracking detection. It consists of silicon pixel and double-sided microstrip detectors. For the readout of the microstrip sensors an ASIC called ToASt (Torino Asic for Strip readout) is being developed in 0.11 μm CMOS technology at INFN Turin. The ASIC takes advantage of both Time-over-Threshold and Time-of-Arrival methods to accurately measure the event's energy and timestamp. To sustain the acquisition of the microstrip sensors a MDC (Module Data Concentrator) ASIC is under development at KIT. Up to eight ToASt front-ends' data streams are multiplexed, read out and processed by one MDC. The data of several MDCs are collected and processed by the off-detector readout card MMB (MVD Multiplexer Board), also under development at KIT. The processed data is then transferred via 100 GbE optical links to the computing nodes. The ToASt chips have been integrated with the FPGA implementation of the MDC to form the first fully functional detector module. Beam tests have been performed at the COSY facility in Jülich. This paper focuses on the design of MDC ASIC and MMB board, the integration with the ToASt and presents preliminary beam test results.

Interstacked Transformer Quad-Core VCOs

This paper presents for the first time a quad-core oscillator based on a very compact interstacked transformer that tightly couples the four cores without oscillation mode ambiguity thanks to its strong magnetic coupling factor. As a proof of concept, a 19.125 GHz oscillator for a narrowband 77 GHz radar system was designed in 28 nm fully depleted silicon-on-insulator CMOS technology with a general purpose back-end-of-line. The soundness of the proposed quad-core oscillator topology is demonstrated by comparison with state-of-the-art quad-core solutions, highlighting a significant advantage in terms of area occupation and power consumption. The proposed topology can be profitably exploited in several RF/mm-wave applications, such as radar and wireless communication systems.

Fabrication of the low-k films with tunable k value as spacers in advanced CMOS technology

In advanced CMOS technology, a suitable spacer scheme is crucial to alleviate the effects of increasing parasitic resistance and capacitance on device performance as the critical dimensions shrinking. Low dielectric constant (low-k) films, possessing a tunable k value ranging from 3.5 to 6.5, were fabricated using plasma-enhanced atomic layer deposition in a single chamber. The fabrication process involved the deposition of the SiN film via SiH2I2 with N2 plasma, as well as the deposition of the SiOX, SiOCN, and SiON films using diisopropylamino silane with O2, Ar/O2, and N2/O2 plasmas, respectively. The introduction of groups containing carbon (C) tended to loosen the film structure, due to its weak bond strength with Si, thus made distinctions in structural and electrical stability. We developed such a process which can adjust the C-group concentration and O, N content to tune the film k value. The SiOx, SiOCN, SiON, and SiN films had high breakdown strength of 9.04, 7.23, 9.41, and over 11 MV cm−1, and meanwhile low leakage current density of 2.42 × 10−9, 4.78 × 10−8, 1.29 × 10−9, and 9.26 × 10−10 A cm−2, respectively. The films exhibited remarkable thermal stability, enhanced breakdown strength, and suppressed leakage with annealing treatment, which could be attributed to the desorption of —CHX groups. Moreover, the low-k materials demonstrated excellent step coverage both in the inner-spacer cavity and on sidewalls, exploring the potential application as spacers in advanced CMOS structure.

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Pass Transistor Logic based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Pass Transistor Logic based Full adder circuits. The entire work is simulated in 180nm CMOS technology.

An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications

To generate high frequency signals for frequency modulated continuous wave (FMCW) application, components such as doubler, tripler or multiplier are usually utilized to process further signals from the low frequency voltage controlled oscillator (VCO). In this paper, a phase-locked loop (PLL) is intended to be the primary part used to generate frequency modulated continuous wave (FMCW) signals from 80 to 84.8 GHz by utilizing a fundamental frequency VCO. To divide those high frequency output signal and large output bandwidth, the auto-tracking Miller divider topology is proposed. This new topology can achieve 9 GHz locking range. In order to generate FMCW signals with a straight-line triangular chirp, the cascaded PLL is used. The integrated jitter from 1 kHz to 1 GHz is 887 fs for the cascaded PLL, while the single stage PLL used 1.264 ps. Moreover, when architecture with doubler or multiplier is used, the fundamental tone has an effect towards the next systems, while the cascaded PLL does not. It can be highlighted that this work achieves the best RMS-FMerror/BWchirp and RMS-FMerror/(BWchirp × fc × Tc) with value of 0.013% and 0.77e−12, respectively. The designed PLL for FMCW signal generator is implemented in 28 nm CMOS technology. By using a supply voltage of 1.2 V, the chip consumes power of 102 mW. Including all the chip pads, the implemented circuit occupies a silicon area of 1440 µm × 820 µm.

Fully Integrated 24-GHz 1TX-2RX Transceiver for Compact FMCW Radar Applications.

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is -80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm2 die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets.

[formula omitted] methodology applied to ring oscillators

This work presents a ring oscillator design flow that calculates the transistor’s dimensions and bias currents that meet the oscillation frequency and phase noise requirements using only pre-calculated tables and MATLAB scripts. The methodology combines look-up tables, the gm/ID methodology, and the square root of the delay K. Results indicate a significant correlation between calculation and simulations with a variation percentage of the frequency oscillation from 2.3% up to 29% for oscillators designed in a TSMC 180 nm CMOS technology.

A 0.6 V voltage reference circuit with 57 ppm/°C temperature coefficient, 73 KΩ output impedance and 0.080%/V line sensitivity for energy efficient applications

In this paper, a voltage reference circuit generating 0.6 V developed in the Semiconductor Laboratory (SCL) 0.18 μm standard CMOS technology has been presented. It is based on the principle of Beta multiplier circuit. Operating under a supply voltage of 1.8V, the proposed reference accomplishes a line sensitivity as low as 0.080%/V across a voltage range of 1.8 V to 3.5 V. In addition to a low line sensitivity, it achieves a low temperature coefficient of 57 ppm/ °C over the temperature range of −40 °C to +85 °C. The circuit furnishes a power supply rejection ratio (PSRR) of −75.72 dB. The improved load regulation feature allows the circuit to drive loads as low as 73 KΩ with minimum variation. A reliable nature of the circuit has been observed on examining the response for different process corners and variations.

Design and optimization of a 16-bit spike detector based on 90nm CMOS technology

To deeply understanding of brain function, the rapid and accurate extracting relevant signals during brain operation has become increasingly important. As our understanding of brain function advances, the ability to extract relevant signals quickly and accurately becomes increasingly crucial. Therefore, a 16-bit spike detector has been designed to detect neural signals. Since a 4-bit absolute value detector is a critical module of the 16-bit spike detector, this paper presents a design for a 4-bit value comparator using a chain adder and a comparator. Two methods, changing the supply voltage and changing the gate size, were utilized to reduce power consumption, and it was found that changing the supply voltage method was more effective. Additionally, the circuits layout was designed for simulation to enhance the authenticity and reliability of the results. Currently, brain-computer interface technology remains a widely discussed topic in the field of neuroscience, and the speed and accuracy of neural signal processing continue to be critical issues that need to be addressed.

An evenly-spaced-phase all-digital DLL using dual-loop SAR control

This study introduces an all-digital delay-locked loop (ADDLL), which generates 20 evenly-spaced-phase clock signals. A successive-approximation register (SAR)-based dual-loop control is used to realize the locking process of the ADDLL. A modified SAR unit combined with a tri-state digital phase detector (TSDPD) is adopted to achieve a closed-loop operation of the ADDLL. A delay matrix, which can significantly reduce the jitter accumulation, is used to generate evenly spaced phases without using a long-cascaded delay line. Additional harmonic-lock detector circuits are added to the two control loops to avoid the harmonic lock issue. The ADDLL is designed and fabricated using a 0.18μm mixed-signal CMOS technology with an active area of 0.109 μm2. The lock range of the ADDLL is 30–230 MHz and the power consumption of the ADDLL is 8.9 mW at 100 MHz. The measured rms jitter is 23.3 ps at 100 MHz, and the results show a good linearity of the multiphase outputs at a 100 MHz input clock where the maximum DNL and INL are 0.08 and -0.22 LSB, respectively. The proposed ADDDLL is highly suitable for low-frequency, low-power, and high-time-resolution applications.

Voltage-Mode Multifunction and Universal Biquads with Two CFOAs

In this paper, a new voltage-mode (VM) multifunction filter including only two grounded capacitors, three resistors, and two current feedback operational amplifiers is introduced. This filter with one high input impedance and two low output impedances can simultaneously provide band-pass filter (BPF) and low-pass filter (LPF) responses with an adjustable gain. A universal VM filter topology with three inputs and one output generating high-pass filter (HPF), BPF, LPF, notch filter, and all-pass filter (APF) responses is obtained from the multifunction one. It has the same number of active and passive elements as the multifunction and a low output impedance. Sensitivities of both introduced filters are low enough. However, the APF of the introduced universal filter has a passive element-matching problem. As an example, parasitic impedance effects are considered for the LPF of the universal filter, while non-ideal gain analyses are given for the HPF. To see how the introduced universal filter works, countless simulations are performed through the SPICE (Simulation Program with Integrated Circuit Emphasis) program in which 0.13 [Formula: see text]m IBM CMOS technology parameters are utilized. DC supply voltages are selected as ± 0.9 V. Also, several experiments using commercially available AD844s with ± 10 V supply voltages are carried out to see the performance.

Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications

Digital signal processing (DSP) has been widely adopted in sensor systems, communication systems, digital image processing, artificial intelligence, and Internet of Things applications. However, these applications require circuits for complex arithmetic computation. The logarithmic number system is a method to reduce the implementation area and transmission delay for arithmetic computation in DSP. In this study, we propose antilogarithmic converters with efficient error–area–delay products (eADPs) based on the fractional-bit compensation scheme. We propose three mathematical approximations—case 1, case 2, and case 3—to approximate the accurate antilogarithmic curve with different DSP requirements. The maximum percentage errors of conversion for case 1, case 2, and case 3 are 1.9089%, 1.7330%, and 1.2063%, respectively. Case 1, case 2, and case 3 can achieve eADP savings of 15.66%, 80.80%, and 84.61% compared with other methods reported in the literature. The proposed eADP-efficient antilogarithmic converters can achieve lower eADP and digitalized circuit implementation. The hardware implementation utilizes Verilog Hardware Description Language and the digital circuits are created via very-large-scale integration by the Taiwan Semiconductor Manufacturing Company with 0.18 µm CMOS technology. This proposed antilogarithmic converter can be efficiently applied in DSP.

Body Biasing Techniques for Dynamic Comparators: A Systematic Survey

Forward body biasing (FBB) has often been exploited in the literature for improving the performance of both analog and digital building blocks. Recent works have explored the application of FBB variants to mixed-signal electronics and in particular to dynamic comparators, where these techniques can help to relax the trade-off between speed and power consumption at medium and low supply voltages. However, the literature lacks a structured analysis of the solutions that have been developed and of the trade-offs that affect them. This work attempts to fill the gap by providing a survey of the application of FBB techniques to dynamic comparators. The analysis focuses on the two most popular dynamic comparator topologies, the Strong Arm latch and Elzakker’s comparator. Several FBB variants are examined from a theoretical point of view. Moreover, the benefits and the limitations of the different approaches are assessed in terms of the main figures of merit through a systematic campaign of simulations in a 55 nm CMOS technology.

Atomic Layer Deposition of Epitaxial Ferroelectric Hf0.5Zr0.5O2 Thin Films

AbstractThe groundbreaking discovery of unconventional ferroelectricity in HfO2 opens exciting prospects for next‐generation memory devices. However, the practical implementation, particularly its epitaxial stabilization and a clearer understanding of its intrinsic ferroelectricity has been a significant challenge. The study arouses the potential importance of atomic layer deposition (ALD) for mass production in modern industries, demonstrating its proficiency in achieving epitaxial growth of ferroelectric Hf0.5Zr0.5O2 (HZO) thin films on Yttria‐stabilized zirconia (YSZ) substrates. Moreover, with distinct ferroelectric switching currents, the work reveals the ferroelectric characteristics of epitaxial HZO thin films deposited through ALD on YSZ‐buffered Si substrates, which aligns well with CMOS technology. Overall, the results pave the way for a scalable synthesis system for ferroelectric HfO2‐based materials, hinting at a bright future for low‐temperature epitaxial nanoelectronics.

A new nano-design of configurable logic module based on coplanar reversible adder and modified Fredkin gates using quantum technology

Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications.

A 107.6 dB-DR Three-Step Incremental ADC for Motion-Tolerate Biopotential Signals Recording.

This article describes a power-efficient, high dynamic range (DR) incremental ADC (IADC) for wearable biopotential signals recording, where DC and low-frequency disturbances such as electrode offset, 50/60 Hz interference and motion artifact must be tolerated. To achieve a wide DR, the IADC performs a three-step conversion by combining zoom-SAR and extended counting (EC) on top of a second-order incremental delta-sigma modulator (ΔΣM). The hybrid architecture notably reduces the oversampling ratio (OSR) with respect to conventional incremental ΔΣMs, while using the EC further improves the Signal-to-Noise-and-Distortion Ratio (SNDR) by 7.4 to 25.6 dB. Fabricated in a 0.18-μm CMOS technology, the IADC achieves 107.6-dB DR, 104.9-dB peak SNR, and 99.3-dB peak SNDR at 2 kS/s while dissipating 130 μW from 1.8-V (analog) / 1.2-V (digital) supply. This translates to a highly competitive FoMDR of 176.5 dB. The high-DR IADC reduces the gain of the preceding instrumentation amplifier (IA) such that significant DC and low-frequency disturbances can be tolerated. The advantages of high DR have been demonstrated by wearable Electrocardiography (ECG) and Electroencephalography (EEG) recordings under motion artifact.