We have been developing a Josephson-CMOS hybrid memory with subnanosecond access time in order to overcome the memory bottleneck in single-flux-quantum digital systems. In this study, we aimed for reducing the power consumption of the 64-kb CMOS static RAM. We took three approaches, miniaturization of memory cells, improvement of data drivers, and employment of a binary-tree decoder. By using these techniques, we decreased the power consumption of 64-kb CMOS static RAMs by 54% in the write operation and by 8% in the read operation. Moreover, we aimed for demonstrating the fully functional operation of the 64-kb Josephson-CMOS hybrid memory composed of the low-power CMOS static RAM, Josephson interface circuits, and Josephson current sensors by using the Rohm 0.18 μm process and the AIST standard process 2. We confirmed the correct memory operation for arbitrary address accesses at low speed. The total access time was evaluated to be 1718 ps and the power consumption was estimated to be 27.62 mW in the write operation and 21.25 mW in the read operation in circuit simulations. Based on these estimations, we discuss the access time and the power consumption of hybrid memories using future CMOS processes.