Abstract
Special test structures fabricated with three different CMOS processes were used to investigate the effect of elevated temperature on single-particle latchup. The latchup threshold was strongly affected by contact geometry, and its temperature dependence is consistent with a model based on triggering of the vertical parasitic transistor. Threshold LET values decreased by about a factor of 2.5 at 125 degrees C relative to room temperature values for all three processes. Saturation cross sections exceeded the isolation well area for the two bulk processes because of diffused charge. Laser studies showed that latchup could be triggered by strikes outside the isolation well, consistent with the diffused charge mechanism. These same mechanisms were consistent with measurements of the latchup cross section of a static CMOS RAM.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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