Defect‐ and fault‐tolerant static ram module designs based on parity checking and automatic testing

Abstract

AbstractAdvanced redundancy configurations are presented for static RAM modules. These extend the word duplication and selection by horizontal parity checking (WDSH) and error correction by horizontal and vertical parity checking (ECHV) configurations to enhance yields of wafer‐scale integrated circuits. They use automatic spare block replacements for bit‐lines and word‐lines, word selection by access error checking, pair unit replacement, and two‐level hierarchical redundancy.A simulation using a 1.5‐μm, 128 k‐bit CMOS static RAM module suggests that defect‐ and fault‐tolerance capability is improved nine or 17 times over the basic redundancy configurations. These values are four or six times that achieved by conventional triple‐modular redundancy (TMR).