CMOS RF Receiver Research Articles

A 0.5-8GHz Reconfigurable CMOS RF Receiver Front-end for CR and DPA Applications

A 0.5-8GHz Reconfigurable CMOS RF Receiver Front-end for CR and DPA Applications

A Compact, Reconfigurable CMOS RF Receiver for NavIC/GPS/Galileo/BeiDou

This article presents a fully integrated low-intermediate frequency (IF) receiver, Dhruva, for global navigation satellite system (GNSS). The compact receiver uniquely features a fully programmable IP with no external components and no change in the on- chip hardware for various GNSS signals (civilian and precise positioning). The receiver bandwidth is programmable from 2 to 24 MHz for signals around <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L1$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L2$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L5$ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S$ </tex-math></inline-formula> frequency bands from Navigation with Indian Constellation (NavIC), global positioning system (GPS), Galileo, and BeiDou. A single-to-differential wideband input-matched noise-canceling low-noise amplifier (LNA) is proposed to avoid the external balun and matching components. An on- chip fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loop (PLL) with a single voltage-controlled oscillator (VCO) generates the required local oscillator (LO) frequencies. A dc offset correction circuit is proposed in the variable gain amplifier (VGA) to avoid signal saturation. Fabricated in 65-nm CMOS technology, the receiver draws a current of 38.35 mA from a 1.2-V supply while providing a maximum gain of 101.72 dB with a programmable gain of 53.53 dB and a minimum noise figure (NF) of 3.8 dB. The receiver occupies an active die area of 1.96 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including the I/O padring with ESD protection.

Design and analysis of CMOS RF receiver front-end of LNA for wireless applications

This article deals the design and analysis of CMOS RF receiver front-end with the optimization of single-stage and two-stage low noise amplifier (LNA) for wireless applications. The low noise, high gain and better linearity for 3–10 GHz ultra wideband (UWB) wireless applications realized in 45 nm CMOS technology. The novelty of a single-ended and cascaded CMOS LNA designs for multi-standard purposeful for reconfigurable applications. The proposed LNA espouse entire circuit simulations investigation of the results in the center frequency of 3.4GHz. The admirable power gain (S21) is 32.5 dB with high reverse isolation (S12) of<−43.2dB; the preferable noise figure (NF) obtained as 0.9 dB. The perfect matching of input-output impedance for stability has measured to significantly input-output reflection coefficients S11=−11.6dB,S22=−10.0dB respectively while consuming only 11.8 mW from a 1 V supply.

Bandwidth‐switchable cellular CMOS RF receiver front‐end for intra‐band carrier aggregation

AbstractA bandwidth‐switchable cellular complementary metal‐oxide‐semiconductor radio frequency receiver front‐end design employing a current‐reusing technique is presented in a 65‐nm RF CMOS technology. The proposed single‐ended receiver front‐end can fully support both narrowband and wideband multiple‐channel RF signals for up to three intraband carrier aggregations with high performance and low direct current consumption. To achieve different bandwidth‐handling capability, a narrowband‐ and a wideband‐switchable low noise amplifier is provided to realize appropriate matching conditions and transconductance, while maintaining high performance in multiple component carrier (CC) modes. The design operates at frequency bands of 700‐2700 MHz with 1.2 V. The design achieves conversion gains of more than 40 and 46 dB and noise figures (NFs) of less than 4.9 and 3.5 dB in wideband and narrowband modes, respectively. NF degradation in multiple CC modes is less than 0.5 dB for both bandwidth conditions.

A CMOS Receiver Front-end with Fractional-N PLL Synthesizer for MedRadio Applications

A CMOS RF receiver front-end with an integrated fractional-N PLL synthesizer and 25% duty-cycle LO generator is presented for MedRadio applications. The receiver front-end comprises a cascode low-noise amplifier, single-to-differential gmstage, quadrature passive mixer, and trans-impedance amplifiers. The PLL synthesizer generates 1.45-1.95 GHz signal, which is then divided by four to generate 25% duty-cycle non-overlapping I/Q LO signals for improved gain and noise performances of the quadrature passive mixer. Implemented in 65 nm CMOS, the fully integrated receiver operates from a 1-V supply, while dissipating 3.2 and 3.5 mW for the RF front-end and PLL synthesizer, respectively. It achieves the voltage gain of +42.2 dB, the noise figure of 3.3 dB, and the input-referred third-order intercept point (IIP3) of -24 dBm. The low-power consumption, high front-end gain, and full integration with the PLL and LO generator make this receiver well suited for low-power small-form-factor MedRadio applications.

Design techniques for mitigation of intermodulation distortion components in CMOS RF receiver front-end circuits with subthreshold operation

This paper provides an overview of target applications and design aspects for emerging radio frequency front-end circuits with subthreshold biasing to reduce power consumption. Design methods are described to linearize a subthreshold pseudo-differential common-source cascode low-noise amplifier (LNA) and a subthreshold active mixer. The linearization techniques can improve the third-order intermodulation intercept point (IIP3) through the use of passive components, which implies that they do not require auxiliary amplifiers to suppress third-order distortion components, and therefore do not incur any extra power consumption. A 1.95 GHz receiver front-end chip with a narrowband LNA and down-conversion mixer was designed and fabricated in 110 nm CMOS technology. Measurement results show that the linearized low-power front-end has a 20.6 dB voltage gain, a 9.5 dB double sideband noise figure, and a − 10.8 dBm IIP3 with a power consumption of 0.9 mW.

A 370 $\mu{\rm W}$ CMOS MedRadio Receiver Front-End With Inverter-Based Complementary Switching Mixer

A low-power CMOS RF receiver front-end is proposed for medical device radiocommunications service (MedRadio) applications. The proposed MedRadio receiver front-end design incorporates an AC-coupled current reuse inverter in order to reduce power consumption and increase transconductance gm. The proposed RF front-end comprises a current-reuse low noise amplifier with ac coupling inverter topology and an inverter-based single-balanced mixer with complementary switching. The proposed RF front-end is implemented in a 0.18 μm CMOS process and draws 370 μA from a 1 V supply voltage. It shows a gain of more than 29 dB, NF of less than 5.2 dB, and IIP3 of more than -19.5 dBm for all MedRadio bands.

A broadband CMOS RF receiver for digital broadcasting systems

Nowadays digital radio systems are replacing analog radio systems. In this paper, a CMOS RF receiver with frequency synthesizer and analog baseband is introduced, which was fabricated with a 0.18-µm CMOS process for DRM/DAB wideband applications. In the system, a fully differential low noise amplifier with a noise cancelling technology is adopted It has achieved a gain of 11.69 dB. A harmonic rejection mixer was implemented to realize the rejections of 3rd- and 5th-order harmonics. As the local oscillator, a wide-band frequency synthesizer provides a phase noise of ?125 dBc/Hz at 1-MHz offset. The designed RF receiver has achieved a conversion gain of 90 dB. The IIP3 of the receiver is in the range of ?25 to ?12 dBm, and the noise figure of 5.44---14.72 dB. The core circuits draw a current of 78.35 mA from a 1.8-V power supply and the chip occupies 6.46-mm2 die area.

A 0.13-㎛ Zero-IF CMOS RF Receiver for LTE-Advanced Systems

This paper presents a zero-IF CMOS RF receiver, which supports three channel bandwidths of 5/10/40MHz for LTE-Advanced systems. The receiver operates at IMT-band of 2,500 to 2,690MHz. The simulated noise figure of the overall receiver is 1.6 dB at 7MHz (7.5 dB at 7.5 kHz). The receiver is composed of two parts: an RF front-end and a baseband circuit. In the RF front-end, a RF input signal is amplified by a low noise amplifier and <TEX>$G_m$</TEX> with configurable gain steps (41/35/29/23 dB) with optimized noise and linearity performances for a wide dynamic range. The proposed baseband circuit provides a -1 dB cutoff frequency of up to 40MHz using a proposed wideband OP-amp, which has a phase margin of <TEX>$77^{\circ}$</TEX> and an unit-gain bandwidth of 2.04 GHz. The proposed zero-IF CMOS RF receiver has been implemented in <TEX>$0.13-{\mu}m$</TEX> CMOS technology and consumes 116 (for high gain mode)/106 (for low gain mode) mA from a 1.2 V supply voltage. The measurement of a fabricated chip for a 10-MHz 3G LTE input signal with 16-QAM shows more than 8.3 dB of minimum signal-to-noise ratio, while receiving the input channel power from -88 to -12 dBm.

A low‐power 5‐GHz CMOS RF receiver for WLAN applications

AbstractA low‐power 5‐GHz IEEE 802.11a CMOS RF receiver for wireless local area network is designed.For low‐power dissipation, a dual conversion current‐driven passive mixer is used in an RF front‐end. An optimum allocation of alternated low‐pass filters and amplifiers in a baseband analog chain is also performed. The receiver is fabricated in 0.13 μm 1‐poly 6‐metal CMOS technology. The fully integrated receiver achieves 90.5 dB maximum gain, 7.1 dB noise figure, and −20 dBm input‐referred third‐order intercept point. The chip area is 3.25 mm2 and it consumes a power of 40.8 mW from a supply voltage of 1.2 V. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:842–847, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26700

A low-power multi-band CMOS RF receiver front-end for ubiquitous sensor network applications

This paper presents the design and experimental results of a low-power multi-band RF receiver including a multi-band low-noise amplifier (LNA) and a down-conversion mixer based on the IEEE 802.15.4 standard for sensor node applications. A multi-band LNA with two inputs is tuned to two resonant frequencies by controlling the voltage on a switched MOS. The implemented RF receiver front-end achieves a maximum voltage conversion gain of 38 and 30 dB, NF of 6.2 and 9.2 dB at the 868/915 MHz and the 2.45 GHz bands, respectively. The RF receiver front-end dissipates total 3.0 mA (including I/Q mixers) under supply voltage of 1.8 V at both operation bands.

A Direct-Conversion CMOS RF Receiver Reconfigurable From 2 to 6 GHz

A CMOS direct-conversion receiver with only one signal path is reconfigurable from 2 to 6 GHz in the RF band and from 3.6 to 54 MHz in the channel bandwidth. By employing a voltage feedback in a common-gate low-noise amplifier (LNA), the input matching of the LNA can be reconfigured for each RF band by simply changing the resonant frequency of the load network. The frequency characteristics of the active-RC channel selection filter with an R-2R ladder is automatically tuned by a one-shot tuning circuit. Implemented in 0.18- μm RF CMOS technology, the whole receive path shows 4.6-5.6-dB noise figure while consuming 65-75 mA from a 1.8-V supply depending on the mode of operation.

A highly linear receiver front-end employing modified derivative superposition method with tuned inductors for 5.25 GHz

We design a highly linear CMOS RF receiver front-end operating in the 5GHz band using the modified derivative superposition (DS) method with one- or two-tuned inductors in the low noise amplifier (LNA) and mixer. This method can be used to adjust the magnitude and phase of the third-order currents at output, and thus ensure that they cancel each other out. We characterize the two front-ends by the third-order input intercept point (IIP3), voltage conversion gain, and a noise figure based on the TSMC 0.18μm RF CMOS process. Our simulation results suggest that the front-end with one-tuned inductor in the mixer supports linearization with the DS method, which only sacrifices 1.9dB of IIP3 while the other performance parameters are improved. Furthermore, the front-end with two-tuned inductors requires a precise optimum design point, because it has to adjust two inductances simultaneously for optimization. If the inductances have deviated from the optimum design point, the front-end with two-tuned inductors has worse IIP3 characteristic than the front-end with one-tuned inductor. With two-tuned inductors, the front-end has an IIP3 of 5.3dBm with a noise figure (NF) of 4.7dB and a voltage conversion gain of 23.1dB. The front-end with one-tuned inductor has an IIP3 of 3.4dBm with an NF of 4.4dB and a voltage conversion gain of 24.5dB. There is a power consumption of 9.2mA from a 1.5V supply.

A 2.4/5.7‐GHz dual‐band low‐power CMOS RF receiver with embedded band‐select switches

AbstractThis article presents a 2.4‐/5.7‐GHz dual‐band low‐power direct‐conversion CMOS RF receiver for the 802.11a/b/g WLAN applications. The RF receiver includes a low noise amplifier (LNA) with dual input stages and dual switches for each of 2.4/5.7‐GHz applications. This design can substitute the use of two LNAs in conventional structure and eliminate the use of the costly external band‐select switches. It also alleviates the difficulty of single matching for multiple frequency bands. The RF receiver also includes a Gilbert‐cell‐based broadband mixer which is designed to be both low power consumption and relatively high conversion gain. Fabricated in 0.18‐μm CMOS technology, the RF receiver exhibits a conversion gain of 25.8/20.6 dB, DSB noise figure of 4.4/5.6 dB, and input IP3 of −18/−12.5 dBm at 2.4/5.7 GHz frequency band, respectively. The measured EVM for IEEE 802.11a/b/g is 1.2/1.6/1.1% at data rate of 11/54/54 Mbps. The power consumption under 1.8 V supply is 10.6 mW for the 2.4 GHz mode, and 17.2 mW for the 5.7 mode. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 593–597, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24120

비동기식 CMOS IR-UWB 수신기의 설계 및 제작

본 논문에서는 IR-UWB 통신에 적합한 저 전력, 저복잡도의 CMOS RF 수신기를 제작하였다. 제안된 IR-UWB 수신기는 비교적 구조가 간단한 non-coherent demodulation 방식으로 설계, 제작되었다. 설계된 IR-UWB 수신기는 LNA, envelop detector, VGA, comparator로 구성되어 있으며, envelop detector, VGA, comparator는 <TEX>$0.18{\mu}m$</TEX> CMOS 공정 기술을 이용하여 단일 칩으로 설계, 제작하였다. 측정 결과 data rate이 1 Mbps일 때 sensitivity가 -70 dBm이며, 이때 BER은 <TEX>$10^{-3}$</TEX>의 값을 가진다. 외부의 LNA를 제외한 단일 칩 CMOS IR-UWB 수신기의 전류 소모는 전압이 1.8 V일 때 5 mA이다. In this paper presents a CMOS RF receiver for IR-UWB wireless communications is presented. The impulse radio based UWB receiver adopts the non-coherent demodulation that simplifies the receiver architecture and reduces power consumption. The IR-UWB receiver consists of LNA, envelop detector, VGA, and comparator and the receiver including envelope detector, VGA, and comparator is fabricated on a single chip using <TEX>$0.18{\mu}m$</TEX> CMOS technology. The measured sensitivity of IR-UWB receiver is down to -70 dBm and the BER <TEX>$10^{-3}$</TEX>, respectively at data rate 1 Mbps. The current consumption of IR-UWB receiver except external LNA is 5 mA at 1.8 V.

Erratum: An integrated 8‐MW 2.4‐GHZ CMOS RF receiver for low‐power WPAN

AbstractOriginally published Microwave Opt Technol Lett 50: 2345–2348, 2008. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 3280, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23901

Design of a 2.4-GHz Fully Differential Zero-IF CMOS Receiver Employing a Novel Hybrid Balun for Wireless Sensor Network

A novel compact model for a five-port transformer balun is proposed for the efficient circuit design of hybrid balun. Compared to the conventional model, the proposed model provides much faster computation time and more reasonable values for the extracted parameters. The hybrid balun, realized in 0.18 ㎛ CMOS, achieves 2.8 ㏈ higher gain and 1.9 ㏈ lower noise figure than its passive counterpart only at a current consumption of 0.67 ㎃ from 1.2 V supply. By employing the hybrid balun, a differential zero-IF receiver is designed in 0.18 ㎛ CMOS for IEEE 802.15.4 ZigBee applications. It is composed of a differential cascode LNA, passive mixers, and active RC filters. Comparative investigations on the three receiver designs, each employing the hybrid balun, a simple transformer balun, and an ideal balun, clearly demonstrate the advantages of the hybrid balun in fully differential CMOS RF receivers. The simulated results of the receiver with the hybrid balun show 33 ㏈ of conversion gain, 4.2 ㏈ of noise figure with 20 ㎑ of 1/f noise corner frequency, and -17.5 ㏈m of IIP3 at a current consumption of 5 ㎃ from 1.8 V supply.

An integrated 8‐mW 2.4‐GHz CMOS RF receiver for low‐power WPAN

AbstractA fully integrated 2.4‐GHz CMOS receiver IC for the low‐power wireless personal area network (WPAN) is reported. In the proposed receiver, low power operation is achieved by using low voltage linear RF front‐end circuit based on current mirror amplifier based mixer and the interleaved analog baseband filter‐amplifier chain. The fully integrated receiver was fabricated in 0.18 μm CMOS technology and IIP3 of −29 dBm and noise figure of 9.6 dB at high gain mode were obtained at 8.4 mW power consumption from a 1.2 V supply. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2345–2348, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23652

A Module for BiST of CMOS RF Receivers

A module to perform a built-in self-test in CMOS RF receivers is presented. The module is associated with a test strategy consisting of measuring the main performance parameters of the single building blocks individually. Circuitry overhead, however, is kept low by using some blocks as part of the test set-up and reusing them. The test overhead has also been reduced by replacing direct determination of performance parameters with their estimation. The test methodology has been applied to a mixer in the first down conversion stage of a GSM receiver, estimating its conversion gain, 1dB compression and third-order interception points. Using the output of the IF amplifier as the only testing point, the rms errors in the estimation of the above mentioned parameters are 1.5, 3.0 and 2.7%, respectively.

CMOS RF receiver system design: a systematic approach

A unified system-level design methodology for highly integrated CMOS radio frequency receiver design is introduced. This complete system-level design methodology is targeted to minimize the total power consumption of the receiver. System-level design techniques which can be used to derive the overall receiver radio specifications and study noise and linearity performance of receivers are presented. Then, a few circuit examples of building blocks in receiver signal chain are analyzed to show a linear relationship between power and dynamic range of the blocks. The result is then used to derive the optimal system specification distribution among receiver signal chain building blocks yielding the minimum total receiver power consumption for a given system performance. The theory and an actual CMOS Bluetooth receiver design are compared showing very good agreement.