CMOS RF Front-end Research Articles

A Low-Power High Gain and High Linearity CMOS RF Front-End Design Involving a Charge Injection Mixer for V2X Technology

In this paper, an RF front-end (RFFE) circuit consisting of a low noise amplifier (LNA) and a down-conversion mixer for vehicle-to-everything (V2X) applications in a 65-nm CMOS process is presented. V2X standard has a carrier frequency of 5.9[Formula: see text]GHz with 10 and 20[Formula: see text]MHz bandwidth options. The LNA topology of the RFFE is based on an inductively degenerated cascode common source differential approach. The mixer design uses a double-balanced topology with a charge injection method to enhance the linearity and noise figure performance. The RFFE design shows a single sideband integrated noise figure of 4.47[Formula: see text]dB with a total conversion gain of 28[Formula: see text]dB. The IIP3 is obtained as [Formula: see text]17[Formula: see text]dBm with charge injection in the mixer which is an improvement of 5[Formula: see text]dB as compared to no charge injection. The design consumes a total current of 10.24[Formula: see text]mA from a 1.2-V supply. This work is the first CMOS RFFE design implemented for V2X applications.

A Multimode 5–6 GHz FD/HD/FDD Quadrature Balanced CMOS Front End With Transmit–Receive Cross-Modulation Distortion Correction

We introduce a multimode and wideband quadrature balanced CMOS RF front end (RFFE) supporting full-duplex (FD), half-duplex (HD), and frequency-division duplex (FDD) operation at the 5-6 GHz band. The proposed RFFE is enhanced by nonlinear digital algorithms that maintain optimal performance at high transmit (Tx) power levels. A theoretical model of the transmit-receive (TR) cross-modulation (CM) distortion mechanism stemming from instantaneous variations in the power amplifiers (PAs) output impedance is laid out and verified in simulation and measurement. A 2-D digital postdistortion (2-D DPoD) algorithm that utilizes the known baseband Tx signal and the downconverted distorted Rx signal is proposed to linearize the CM-distorted Rx signal, in conjunction with wideband digital RF and baseband cancellation of the Tx self-interference at the receiver input and 1-D digital predistortion to linearize the Tx signal. The system was characterized in simultaneous TR operation using 802.11ac VHT Wi-Fi signals at 10 dBm average Tx power. In the FD mode using 20 MHz signals, TR isolation of 66 dB was achieved, and the 2-D DPoD corrected Rx error vector magnitude (EVM) by 11 dB to a value of -33 dB. In the FDD mode with 800 MHz frequency separation, 14 dB improvement was demonstrated in Rx EVM with 2-D DPoD to the levels of -35 and -31 dB for 20 and 160 MHz signals, respectively. Similar EVM values were measured in the HD Rx mode at -40 dBm average Rx power, along with Rx insertion loss lower than 1 dB without using a TR switch.

Analysis and Design of a Broadband Output Stage With Current-Reuse and a Low Insertion-Loss Bypass Mode for CMOS RF Front-End LNAs

This article presents a comprehensive analysis of a novel broadband output stage for external RF front-end low-noise amplifiers (eLNAs). Both variants of the output stage are manufactured using a 130nm bulk CMOS technology. They utilize a common-drain output stage with current-reuse topology, switchable resistive feedback, and source-degeneration. Also, a novel inductor-less low insertion-loss bypass mode is implemented for enhanced bypass functionality. The LNAs are implemented with 4 gain modes achieving excellent RF performance in all possible mobile communication scenarios. Furthermore, an auxiliary linearization circuitry (NMOS IMD sinker) is implemented for variant β to improve linearity performance in low gain mode. Besides, the LNAs support all frequency bands between 1.4GHz and 2.7GHz by only changing the external matching component, allowing easy adaption to different frequency bands. Two offered solutions are realized with a die size of only 0.16mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.11mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. The power consumption is 6.0mW in high gain, 3.6mW in low gain and active-bypass and 0.12mW in bypass mode using a supply voltage of 1.2V. Moreover, a 5.15GHz LNA with high-Q on-chip matching and the broadband output stage is realized and manufactured using a 60nm RF SOI technology. A NF performance of only 1.15dB is achieved consuming only 6.0mW power.

A Broadband CMOS RF Front End for Direct Sampling Satellite Receivers

This paper presents a comparative analysis between two new architectures for RF programmable-gain amplifiers (RFPGAs): voltage-mode RFPGA-V and current-mode RFPGA-I. RFPGA-V utilizes multiple-switch-multiple-amplifier configuration and gain interpolation method to achieve a fine gain step of 0.25-dB over 42-dB gain range for the band of 250 MHz to 2.3 GHz. Meanwhile, RFPGA-I uses a current steering approach to achieve a fine gain step of 0.25-dB over 42-dB gain range for an even wider band of 250 MHz to 3.4 GHz. Since the active feedback topology is used, no off-chip inductor is needed in either RFPGA, especially for the low-frequency band. In addition, both RFPGA-V and RFPGA-I are able to handle maximum 4.4 V peak-to-peak input signal without compromising their high operating bandwidth. Two broadband RF front ends for direct sampling receivers, which include either RFPGA-V or RFPGA-I followed by the same gain buffer and RF filter, have been demonstrated. For the RF front end with RFPGA-V, the measured gain, noise figure, third-order input-referred intercept point (IIP3), and second-order input-referred intercept point (IIP2) in the differential mode are 29.5 dB, 5.2 dB, −10.9 dBm, and 31.4 dBm, respectively. With RFPGA-I, they are 30.5 dB, 3 dB, −10.5 dBm, and 21.1 dBm, respectively. Both RF front ends consume approximated 50 mW and occupy the similar area of 0.32 mm2 in 28-nm CMOS technology.

Design of Low Voltage Integrated CMOS RF front-end based LNA and Mixer for GPS Application

In this research article RF front-end is proposed which is important block of receiver system in wireless communication constituting Low Noise Amplifier (LNA) and Mixer block. It should necessarily have high Gain, good isolation, minimum noise figure, high stability and high linearity for optimum performance. This work is an attempt to develop the same. In proposed front-end, the LNA contains single differential topology including matching network. The Mixer is a switching block having Gilbert Down conversion topology. The CMOS RF front end is designed through Cadence spectre RF simulation in standard UMC 90 nm CMOS process at 1.575 GHz frequency which seeks its application in GPS receiver system. The parameters like Gain, input matching, output matching, reverse isolation and stability, noise figure, 1dB compression point, IIP3 and power consumption are examined for 1.5V input along with comparison of existing works.

Implementation of a wireless ECG acquisition SoC for IEEE 802.15.4 (ZigBee) applications.

This paper presents a wireless biosignal acquisition system-on-a-chip (WBSA-SoC) specialized for electrocardiogram (ECG) monitoring. The proposed system consists of three subsystems, namely, 1) the ECG acquisition node, 2) the protocol for standard IEEE 802.15.4 ZigBee system, and 3) the RF transmitter circuits. The ZigBee protocol is adopted for wireless communication to achieve high integration, applicability, and portability. A fully integrated CMOS RF front end containing a quadrature voltage-controlled oscillator and a 2.4-GHz low-IF (i.e., zero-IF) transmitter is employed to transmit ECG signals through wireless communication. The low-power WBSA-SoC is implemented by the TSMC 0.18-μm standard CMOS process. An ARM-based displayer with FPGA demodulation and an RF receiver with analog-to-digital mixed-mode circuits are constructed as verification platform to demonstrate the wireless ECG acquisition system. Measurement results on the human body show that the proposed SoC can effectively acquire ECG signals.

A CMOS RF front-end with linearized current-to-current converter and gate switching mixer

A CMOS RF front-end with a linearized current-to-current converter and a gate switching mixer for multiband and multistandard mobile TV tuners is proposed. A linearized current-to-current converter and a gate switching passive mixer merged with the linearized current-to-current converter are proposed to improve the linearity of the RF front-end. It is fabricated in a 0.13-μm CMOS process and draws 13, 15, and 15 mA from a 1.2 V power supply at VHF, UHF, and L-band operation, respectively. It shows a gain of more than 32 dB, NF of less than 2.5 dB, IIP2 of more than 35 dBm, and IIP3 of more than −10.5 dBm across all bands. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:247–250, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27309

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, −7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply.

Low-Power Analog Integrated Circuits for Wireless ECG Acquisition Systems

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

A Broadband CMOS RF Front-End for Universal Tuners Supporting Multi-Standard Terrestrial and Cable Broadcasts

A wideband CMOS highly linear and low noise RF front-end including inductor-less wideband LNA, integrated passive tunable filter, harmonic rejection mixer (HRM), and loop-through amplifier (LTA) is proposed for universal tuners. The proposed inductor-less wideband LNA shows a gain range greater than 55 dB with fine gain step less than 0.5 dB while achieving higher linearity and lower noise figure (NF), as compared with the traditional resistive/active feedback LNA through a source follower (SF). The integrated tunable filter covers the entire VHF bands without dividing the frequency range by multiple filters. By adopting tunable filter and HRM simultaneously, the overall harmonic rejection ratio (HRR) of over 65 dBc is obtained. The active feedback LTA utilizing a complementary characteristic of NMOS and PMOS is proposed for supporting multiple tuner applications. The proposed RF front-end achieves a maximum voltage gain of 42 dB, a minimum NF of 4.7 dB, and CTB and CSO of under -60 dBc. The power consumption including the LTA is 144 mW at a 1.8 V supply and the chip area is 1.43 mm2 .

A Subthreshold CMOS RF Front-End Design for Low-Power Band-III T-DMB/DAB Receivers

This letter presents a CMOS RF front-end operating in a subthreshold region for low-power Band-III mobile TV applications. The performance and feasibility of the RF front-end are verified by integrating with a low-IF RF tuner fabricated in a 0.13-μm CMOS technology. The RF front-end achieves the measured noise figure of 4.4 dB and a wide gain control range of 68.7 dB with a maximum gain of 54.7 dB. The power consumption of the RF front-end is 13.8 mW from a 1.2 V supply.

Experimental 5-GHz RF Frontends for Ultra-Low-Voltage and Ultra-Low-Power Operations

This paper presents experimental CMOS RF frontends suitable for ultra-low-power and ultra-low-voltage operations. In order to achieve the desirable gain and linearity of the receiver chain at a reduced supply voltage, the current-reused bias technique and the multiple-gated transistors are employed. As for the transmitter frontend, a low-voltage double-balanced mixer is utilized to maximize the conversion gain. In addition, a differential-to-single-ended circuit is also included to increase the saturated output power. Using a standard 0.18-μm CMOS process, the proposed circuits are realized for 5-GHz RF applications with a supply voltage of 0.6 V. The fabricated receiver frontend demonstrates a conversion gain of 14.5 dB and an IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of -16 dBm with a power consumption of 2.1 mW, while the conversion gain and the output 1-dB compression of the transmitter frontend are 12.9 dB and -4.1 dBm, respectively, provided a dc power of 6 mW.

A low noise CMOS RF front-end for UWB 6–9 GHz applications

An integrated fully differential ultra-wideband CMOS RF front-end for 6–9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 μm RF CMOS process and achieves a maximum voltage gain of 23–26 dB and a minimum voltage gain of 16–19 dB, an averaged total noise figure of 3.3–4.6 dB while operating in the high gain mode and an in-band IIP3 of −12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

A CMOS Wideband RF Front-End With Mismatch Calibrated Harmonic Rejection Mixer for Terrestrial Digital TV Tuner Applications

A wideband direct-conversion RF front-end for Advanced Television Systems Committee terrestrial digital TV (DTV) tuner applications is realized in a 0.18-μm CMOS technology. In order to effectively solve the critical local oscillator (LO) harmonic mixing problem in an ultra-wideband frequency environment of 48-860 MHz, the combination of a mismatch calibrated harmonic rejection mixer (HRM) and a simple preceding integrated third-order passive RF tracking filter with an external inductor is utilized to obtain 60-80 dB of harmonic rejection for all odd-order harmonic mixing within the DTV spectrum. In addition, an efficient novel calibration algorithm for the HRM is proposed in order to simplify the compensation process. The RF front-end also includes a broadband noise-canceling low-noise amplifier, an attenuator to cover the wide dynamic range, an LO multiphase generator, and peripheral circuits such as an I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> C serial interface for digital control. The implemented CMOS RF front-end achieves a total gain of 40 dB, output third-order intercept point of 30 dBm, and noise figure of 5.5 dB while consuming a low power of 140 mW from a 1.8-V supply voltage.

Capacitive RF MEMS Switches Fabricated in Standard 0.35-$\mu{\hbox{m}}$ CMOS Technology

The objective of this paper is to investigate the integration of capacitive type RF microelectromechanical systems (MEMS) switches in a standard CMOS technology. A maskless monolithic integration process dedicated to electrostatically actuated capacitive type RF MEMS switches is developed and optimized. The fabricated switches consist of composite metal-dielectric warped membranes. The warped-plate structure is used to increase the capacitance ratio of the switch. The switches are fabricated using the interconnect metal and dielectric layers available in a standard 0.35-μm CMOS process. Measurement results for the first switch show an insertion loss less than 0.98 dB, a return loss below 13 dB up to 20 GHz in the up-state, and a down-state isolation of 12.4-17.9 dB from 10 to 20 GHz. The capacitance ratio is enhanced up to 91:1 using the warped-plate structure. A second cascaded switch consisting of two shunt capacitive switches and a slow-wave high-impedance transmission line section is designed and fabricated for high-isolation applications. The measured insertion loss for this switch is less than 1.41 dB up to 20 GHz, the return loss is below 19 dB, and the isolation is 19-40 dB across the frequency band from 10 to 20 GHz. The proposed RF MEMS switches can be used in millimeter-wave CMOS RF front-ends where multiband functionality and reconfigurability is required.

Design of Ultra-Low-Voltage RF Frontends With Complementary Current-Reused Architectures

In this paper, ultra-low-voltage circuit techniques are presented for CMOS RF frontends. By employing a complementary current-reused architecture, the RF building blocks including a low-noise amplifier (LNA) and a single-balanced down-conversion mixer can operate at a reduced supply voltage with microwatt power consumption while maintaining reasonable circuit performance at multigigahertz frequencies. Based on the MOSFET model in moderate and weak inversion, theoretical analysis and design considerations of the proposed circuit techniques are described in detail. Using a standard 0.18-mum CMOS process, prototype frontend circuits are implemented at the 5-GHz frequency band for demonstration. From the measurement results, the fully integrated LNA exhibits a gain of 9.2 dB and a noise figure of 4.5 dB at 5 GHz, while the mixer has a conversion gain of 3.2 dB and an IIP3 of -8 dBm. Operated at a supply voltage of 0.6 V, the power consumptions of the LNA and the mixer are 900 and 792 muW, respectively.

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), ?18 dBm input 1 dB compression point (ICP) and ?7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard.

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and ...

A CMOS RF front-end for a multistandard WLAN receiver

This letter describes the design and performance of a dual band tri-mode receiver front-end compliant with the IEEE 802.11a, b, and g standards. The receiver front-end was built in a 0.18-μm CMOS process and achieves a noise figure of 4.7 dB/5.1 dB for the 2.4-GHz/5-GHz bands, respectively. The receiver front-end provides a dual gain mode of 5 dB/30 dB with an IIP3 of -1dBm for the low gain mode. The front-end draws 25 mA/27 mA from a 1.8-V supply for the 2.4-GHz/5-GHz bands, respectively.