CMOS Process Research Articles

A 1.65‐nW 11.14‐ppm/°C self‐biased subthreshold CMOS voltage reference with temperature compensation circuit

SummaryThis paper presents a subthreshold CMOS voltage reference (VR) that utilizes self‐biased circuits. This voltage reference includes temperature compensation circuits to expand its operating temperature range and reduce its temperature coefficient. The proposed CMOS voltage reference is designed using a standard 0.18‐μm CMOS process and has a small area of only 0.005 mm2. Post‐layout simulation results demonstrate that the power consumption of the circuit at room temperature (25°C) is only 1.65 nW at a power supply voltage of 1 V. In this case, the voltage reference output is 316.56 mV, with an average temperature coefficient (TC) of 11.14 ppm/°C in a wide temperature range from −40°C to 140°C. Furthermore, the line sensitivity (LS) of the circuit is 0.024%/V, and the power supply rejection ratio (PSRR) of the circuit is −86.5 dB at 10 Hz. In summary, the subthreshold CMOS voltage reference structure proposed in this paper demonstrates excellent performance characteristics, such as low power consumption, a small area, and high‐temperature stability. These features make it a promising candidate for voltage reference for low‐power applications with significant changes in environmental temperature.

1 V Tunable High-Quality Universal Filter Using Multiple-Input Operational Transconductance Amplifiers

This paper presents a new multiple-input single-output voltage-mode universal filter employing four multiple-input operational transconductance amplifiers (MI-OTAs) and three grounded capacitors suitable for low-voltage low-frequency applications. The quality factor (Q) of the filter functions can be tuned by both the capacitance ratio and the transconductance ratio. The multiple inputs of the OTA are realized using the bulk-driven multiple-input MOS transistor technique. The MI-OTA-based filter can also offer many filtering functions without additional circuitry requirements, such as an inverting amplifier to generate an inverted input signal. The proposed filter can simultaneously realize low-pass, high-pass, band-pass, band-stop, and all-pass responses, covering both non-inverting and inverting transfer functions in a single topology. The natural frequency and the quality factors of all the filtering functions can be controlled independently. The natural frequency can also be electronically controlled by tuning the transconductances of the OTAs. The proposed filter uses a 1 V supply voltage, consumes 120 μW of power for a 5 μA setting current, offers 40 dB of dynamic range and has a third intermodulation distortion of −43.6 dB. The performances of the proposed circuit were simulated using a 0.18 μm TSMC CMOS process in the Cadence Virtuoso System Design Platform to confirm the performance of the topology.

4670‐PPI OLEDoS pixel circuit design for wide data voltage range in a 5 V 0.13 μm CMOS process

AbstractOLEDoS displays hold great promise for AR/VR applications, but the ultra‐high pixel density required for microdisplays, exceeding several thousand PPI, presents significant challenges for pixel circuit design. Above all, the maximum OLED current of each OLEDoS sub‐pixel is extremely low, on the order of several nanoamperes or less, resulting in a data voltage range narrower than a few hundred millivolts. Consequently, for example, when expressing 10‐bit grayscale, designing data driver circuits to divide the data voltage range into 1024 levels becomes exceedingly challenging. Furthermore, circuit techniques that compensate for variations in transistor characteristics are nearly inapplicable due to the ultra‐small pixel area. This paper proposes a pixel circuit design method to expand the data voltage range for a 4670‐PPI OLEDoS display while considering current uniformity. The effectiveness of the proposed pixel circuit was verified through measurements on 40 × 120 pixel arrays fabricated in a 5 V 0.13 μm CMOS process.

Enhancing Carrier Mobility in Monolayer MoS2 Transistors with Process-Induced Strain.

Two-dimensional electronic materials are a promising candidate for beyond-silicon electronics due to their favorable size scaling of electronic performance. However, a major challenge is the heterogeneous integration of 2D materials with CMOS processes while maintaining their excellent properties. In particular, there is a knowledge gap in how thin film deposition and processes interact with 2D materials to alter their strain and doping, both of which have a drastic impact on device properties. In this study, we demonstrate how to utilize process-induced strain, a common technique extensively applied in the semiconductor industry, to enhance the carrier mobility in 2D material transistors. We systematically varied the tensile strain in monolayer MoS2 transistors by iteratively depositing thin layers of high-stress MgOx stressor. At each thickness, we combined Raman spectroscopy and transport measurements to unravel and correlate the changes in strain and doping within each transistor with their performance. The transistors displayed uniform strain distributions across their channels for tensile strains of up to 0.48 ± 0.05%, at 150 nm of stressor thickness. At higher thicknesses, mechanical instability occurred, leading to nonuniform strains. The transport characteristics systematically varied with strain, with enhancement in electron mobility at a rate of 130 ± 40% per % strain and enhancement of the channel saturation current density of 52 ± 20%. This work showcases how established CMOS technologies can be leveraged to tailor the transport in 2D transistors, accelerating the integration of 2D electronics into a future computing infrastructure.

A First-Order Noise-Shaping SAR ADC with PVT-Insensitive Closed-Loop Dynamic Amplifier and Two CDACs

This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables an aggressive noise transfer function while minimizing the power consumption associated with the use of an active filter. In the proposed ADC, the residue is generated by a capacitive digital-to-analog converter (CDAC) employing DWA, which is made possible by employing a second CDAC, which operates after the SAR operation is completed. The proposed ADC is designed with a 28 nm CMOS process with 1 V power supply. The simulation results show that the ADC achieves the SNDR of 71.2 dB and power consumption of 228 μW when operated with a sampling rate of 80 MS/s and oversampling ratio (OSR) of 10. The Schreier figure-of-merit (FoM) is 173.6 dB, and Walden FoM is 9.6 fJ/conversion-step.

An Energy-Efficient 12-Bit VCO-Based Incremental Zoom ADC with Fast Phase-Alignment Scheme for Multi-Channel Biomedical Applications

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support VCM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s.

An energy-efficient reconfigurable 18/12-bit 1 MS/s pipelined-SAR ADC

This paper presents a low-power 18/12-bit 1 MS/s reconfigurable pipelined-successive approximation register analog-to-digital converter (pipelined-SAR ADC). The proposed pipelined-SAR ADC employs a two-stage SAR structure coupled through a residual amplifier, with the forestage performing 12-bit coarse quantization and the poststage handling 7-bit fine quantization, one bit of redundancy is contained in the rear stage. The input signal is sampled by the first stage, SAR ADC, using the upper plate of a capacitor array and is quantized by charge redistribution. This eliminates the need of additional DACs and subtractors, allowing direct acquisition of the residuals. In addition, the residuals can be amplified by reusing the capacitor array as a switching capacitor. To minimize static power consumption, dynamic logic is adopted in each module of the pipelined-SAR ADC. The calibration of comparator offset and capacitor mismatch is carried out using analog front-end calibration techniques. Implemented in a 180 nm CMOS process, the simulation results show an extra-low power consumption of 1.76 mW with 3.3 V supply voltage and 1 MS/s sampling rate, indicating an exceptional Schreier figure of merit (FOMs) at 181.64 dB. By shutting down the modules of the second-stage SAR ADC, the 18-bit ADC can be dynamically configured as a 12-bit ADC with a sampling rate of up to 5 MS/s.

A 65 nm 75 MHz–260 MHz sixth-order Active-RC bandpass filter

-A sixth-order Chebyshev-I active-RC bandpass filter was fabricated in a 65 nm CMOS process. An operational amplifier (OPA) with an improved feedforward compensation structure is achieved, which significantly increases bandwidth and gain while reducing power consumption. The tuning module enables the filter to measure a center frequency of 75 MHz–260 MHz, and the bandwidth, Q-factor and gain can be configured according to different application requirements. The effective area of the filter chip is 0.64 mm2, and it can operate at a voltage of 2.5 V with a current dissipation of 34.3 mA.

A dual threshold adaptation method to dynamic vision sensor pixel

This paper introduces a method for the dynamic vision sensor (DVS) pixel that achieves dual-threshold adaptation based on the interval between adjacent event spikes. The Time-to-Amplitude Converter (TAC) measures the adjacent spike interval per pixel. Based on the output of the TAC and two predefined time limit, the threshold selection circuit automatically chooses between the low threshold ΘL or the high threshold ΘH. The proposed pixel pitch is 33.2μm×34.2μm with 8.1% fill factor in a 0.11μm 1P4M CMOS process. Compared to traditional pixel with fixed threshold temporal contrast Θ = 15%, the behavior model indicates that the proposed structure maintains almost equivalent detection ability while reducing event output by 30% when ΘH = 45% and ΘL = 15%. Compared to the traditional pixel with fixed Θ = 45%, the behavior model indicates that the average gradient of the proposed structure is improved by at least 3 times with ΘH = 45% and ΘL = 15%. This enables the detection of low temporal contrast signals while minimizing the quantity of output events.

A 206.4 dBc/Hz FoMT Class-F23 VCO using nonlinear-capacitance-transforming technique

—In this paper, a class-F23 VCO using nonlinear-capacitance transforming technique to simultaneously achieve low phase noise and a wide tuning range is proposed. The phase noise degradation due to the nonlinearity of the switched capacitor in the class-F23 oscillator is analyzed and quantitatively derived. The phase noise contributed by the nonlinear capacitance can be suppressed by using the proposed nonlinear-capacitance transformation technique. In order to achieve low phase noise over a wide bandwidth, the asymmetric-toggling method is utilized to achieve optimal capacitance ratios across the entire frequency range. Implemented in a 40-nm CMOS process, the proposed oscillator exhibits 41.2 % tuning range from 2.58 GHz to 3.92 GHz while consuming 13.8 mW–14.9 mW power dissipation. The phase noises at 2.58 GHz and 3.92 GHz oscillation frequencies are −136.4 dBc/Hz and −129.6 dBc/Hz at 1-MHz offset. The minimum phase noise is −157.2 dBc/Hz at 10 MHz offset, corresponding to an FoM of 194.1 dBc/Hz and FoMT of 206.4 dBc/Hz.

A polysilicon based bipolar-like avalanche light-emitting diode with an enhanced avalanche breakdown effect

The advantage of silicon-based avalanche N+P junction LEDs is that they are compatible with silicon CMOS processes and facilitate optoelectronic integration, but their relatively high operating voltage limits their applications. In view of this, we propose a polysilicon avalanche LED (light-emitting device) with a bipolar-like structure that has a different avalanche breakdown mechanism from that of a normal PN junction, achieving an operating voltage significantly lower than that of a conventional N+P LED. Five polysilicon avalanche LEDs with base lengths ranging from 4µm to 10µm have been fabricated and tested. They have proven to operate at voltages as low as about 6 to 7V, while the conventional N+P LEDs used for comparison cannot operate below 9V. We also observed that they have higher luminous efficiency than the conventional N+P LED. The luminous intensity of the bipolar-like LED with a base length of 4 μm is about 41% higher than that of the conventional N+P LED at a power consumption of 0.4W. This demonstrates the advantages of bipolar avalanche LEDs in all-silicon monolithic optoelectronic integration applications.

Monotonic Asynchronous Two-Bit Full Adder

Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic over QDI logic for arithmetic circuits such as adders and multipliers. This paper presents a new monotonic asynchronous two-bit full adder (TFA) that can be duplicated and cascaded to form a ripple-carry adder (RCA). While an RCA is a slow adder with respect to synchronous design, with respect to IOM asynchronous design an RCA is a noteworthy adder since it has perhaps the least reverse latency that is not attainable through other IOM asynchronous adders. Conventionally, an RCA is constructed via a cascade of one-bit full adders (OFAs). An OFA adds two input bits along with any carry input and produces a sum bit and any carry output. On the other hand, a TFA simultaneously adds two pairs of input bits along with any carry input and produces two sum bits and any carry output. Using our proposed monotonic TFA, we realized an RCA to compare its performance with RCAs constructed using different asynchronous OFAs, and RCAs constructed using existing TFAs. We considered the popular delay-insensitive dual-rail scheme for encoding the adder inputs and outputs, and two 4-phase handshake protocols, namely return-to-zero handshaking (R0H) and return-to-one handshaking (R1H) for communication separately. We used a 28 nm CMOS process for implementation and considered a 32-bit addition as an example. Based on the design metrics estimated, the following inferences were derived: (i) compared to the RCA using the state-of-the-art monotonic OFA, the RCA incorporating the proposed TFA achieved a 26% reduction in cycle time for R0H and a 28.5% reduction in cycle time for R1H while dissipating almost the same power; the cycle time governs the data application rate in an IOM asynchronous circuit, and (ii) compared to the RCA comprising an early output QDI TFA, the RCA incorporating the proposed TFA achieved a 22.3% reduction in cycle time for R0H and a 25.4% reduction in cycle time for R1H while dissipating moderately less power. Also, compared to the existing early output QDI TFA, the proposed TFA occupies 40.9% less area for R0H and 42% less area for R1H.

A Low-Voltage Self-Starting Boost Converter Using MPPT with Pulse Multiplication for Energy Harvesting

A single-inductor, low-voltage, three-step self-starting boost converter is proposed for photovoltaic (PV) energy harvesting. In order to enhance energy transfer efficiency, a variable-step Perturb and Observe (P&O) Maximum Power Point Tracking (MPPT) scheme has been devised based on a novel pulse multiplication technique. Upon overcoming the speed and accuracy limitations, the maximum power point (MPP) of the PV model is accurately tracked. In the boost converter, the average inductor current is utilized to implement closed-loop control of the MPPT loop, enhancing the stability of the tracking process and enabling efficient energy transmission. Finally, the boost converter is implemented using a 0.18 μm CMOS process, which is capable of self-starting and maintaining stable operations at input voltages ranging from 90 mV to 300 mV, achieving a peak efficiency of 93%.

A Novel Bootstrapped CMOS Switch with Minimized Sampling and Holding Error Using Sampling Window Error Analysis

This study proposes a novel 6-transistor bootstrapped switch with minimized sampling and holding error obtained through sampling window error analysis for SAR ADC design. The proposed switch design strategically mitigates channel charge injection and minimizes the input signal dependency of on-resistance by optimizing its sizing parameters. To counteract channel charge effects, dummy NMOS and PMOS components are judiciously employed, culminating in a substantial improvement in the effective number of bits (ENOB). The complete analysis of the proposed circuit is done using the Cadence Virtuoso SCL 0.18[Formula: see text][Formula: see text]m CMOS process. For a 51.514[Formula: see text]kHz sinusoidal 1[Formula: see text]V peak-to-peak differential input signal with a 1[Formula: see text]MSPs clock speed, the proposed circuit achieves 2.0141[Formula: see text]mV maximum sampling window error, 0.131[Formula: see text][Formula: see text]W power consumption, 84.67 dB signal-to-noise ratio (SNR), 84.67 signal-to-noise and distortion (SINAD) ratio and 86.02 dB spurious-free dynamic range (SFDR), which produces 13.77 bits ENOB. For the impacts of process variations and mismatch on switch performance, a comprehensive 500-point Monte Carlo (MC) simulation of the proposed bootstrap switch is conducted in this study. Post-layout results show that the proposed circuit is suitable for IoT applications.

A Hybrid Scheme for TX I/Q Imbalance Self-Calibration in a Direct-Conversion Transceiver

A generic transmitter (TX) I/Q imbalance self-calibration method, which was designed based on a hybrid analog and digital structure, is proposed in this paper. The whole calibration scheme was implemented using low-complexity digital–analog circuits based on a zero-force feedback loop. In order to eliminate the negative effect of local oscillator (LO) harmonics on the calibration, we used a variable-delay line (VDL) in the analog domain instead of the digital phase compensator. The prototype chip was fabricated within a 0.2∼5.0 GHz direct-conversion transmitter in a 65 nm CMOS process, and measurements found an image rejection ratio (IRR) of 65 dBc.

A 0.73 mW low power 9.6 GHz LC voltage-controlled oscillator achieves constant KVCO and −189.2 FOM

This article introduces a novel approach of LC voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications and proposes a 9.6 GHz VCO based on gm-boosted structure. By utilizing a transformer and gain variation calibration technique, the proposed VCO reduces the losses caused by MOSFET’s operation in triode region, thereby improving phase noise. And KVCO remains relatively constant, fluctuating up and down by approximately 5 MHz around 100 MHz/V, which is suitable to be used in phase-locked-loops (PLL). The oscillator is fabricated in 22 nm CMOS process occupying 0.25 mm × 0.55 mm area and consuming 0.73 mW from 0.5 V supply voltage. The measured phase noise achieves −114.3 dBc/Hz at 1 MHz offset with a carrier frequency of 4.75 GHz, and the figure of merit (FoM) is −189.2 dBc/Hz. The results clearly demonstrate that the proposed design could work under low power consumption and achieve constant KVCO, making it well suitable for high-frequency PLL applications.

A 1.2 V, 92 dB Dynamic-Range Delta-Sigma Modulator Based on an Output Swing-Enhanced Gain-Boost Inverter

This article presents a third-order, feedforward, single-bit Delta-Sigma analog-to-digital modulator (DSM) based on an output swing-enhanced gain-boost inverter for low-voltage low-power applications such as wearable devices, mobile health, and the Internet of Things (IoTs). The proposed output swing-enhanced structure addresses the output-swing reduction in the conventional structure while achieving high DC gain and large output swing simultaneously. Implemented in a 180 nm CMOS process, the entire chip is comprised of a delta-sigma modulator, an oscillator, and a current reference. It achieves 86.1 dB peak SNR and 92 dB dynamic range (DR) with 1.95 kHz signal bandwidth. The whole chip dissipates 54.5 μW, leading to a 167.6 dB Schreier Figure of Merit (FoMs).

A 2 μm Wavelength Band Low-Loss Spot Size Converter Based on Trident Structure on the SOI Platform.

A 2 μm wavelength band spot size converter (SSC) based on a trident structure is proposed, which is coupled to a lensed fiber with a mode field diameter of 5 μm. The cross-section of the first segment of the tapered waveguide structure in the trident structure is designed as a right-angled trapezoidal shape, which can further improve the performance of the SSC. The coupling loss of the SSC is less than 0.9 dB in the wavelength range of 1.95~2.05 μm simulated by FDTD. According to the experimental results, the lowest coupling loss of the SSC is 1.425 dB/facet at 2 μm, which is close to the simulation result. The device is compatible with the CMOS process and can provide a good reference for the development of 2 μm wavelength band integrated photonics.

A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse

A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 μm CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply.

Design and Evaluation of a Double-Gate Tunnel Field Effect Transistor for the Detection of Breast Cancer Cells

This research paper investigates the application of a Double Gate (DG) Tunnel Field-Effect Transistor (DG-TFET) for the detection of cell lines derived from breast cancer tissue, namely Hs578T, MDA-MB-231, MCF-7, and T47D. The device incorporates two nanocavities positioned beneath the two gate electrodes, significantly enhancing detection capabilities. The study emphasizes the differentiation between healthy non-tumorigenic cells (MCF-10A) and breast cancer-derived cell lines by incorporating gate engineering into the TFET. Furthermore, the research explores the impact of changes in dielectric values specific to different breast malignant cell types on the biosensor's detection capabilities. Additionally, the investigation delves into the influence of variations in device geometry, including cavity dimensions and dielectric layer thickness, on critical parameters such as drain current sensitivity, transconductance sensitivity, and ION/IOFF sensitivity. Sensitivity analysis concerns drive current, ION/IOFF ratio, threshold voltage (Vth), and transconductance. The structural design of the device is tailored to facilitate array-based diagnosis and screening of cell lines derived from breast cancer tissue. This design offers several advantages, including a simplified transduction process, compatibility with CMOS processes, cost-effectiveness, reproducibility, and adjustable electrical responses. The researchers employed ATLAS, a two-dimensional (2D) device simulator from Silvaco, to model and define the device structure. The numerical simulations validate the device's performance, demonstrating favorable ON-OFF transition profiles.