CMOS Preamplifier Research Articles

A Microelectrode/Microelectronic Hybrid Device for Brain Implantable Neuroprosthesis Applications

We have designed, fabricated, and characterized a microminiaturized "neuroport" for brain implantable neuroprosthesis applications, using an analog CMOS integrated circuit and a silicon based microelectrode array. An ultra-low power, low-noise CMOS preamplifier array with integral multiplexing was designed to accommodate stringent thermal and electrophysiological requirements for implantation in the brain, and a hybrid integration approach was developed to fabricate a functional microminiaturized neuroprobe device. Measurements showed that our fully scalable 16-channel CMOS amplifier chip had an average gain of 44 dB, bandwidth from 10 Hz to 7.3 kHz, and an equivalent input noise of approximately 9 microVrms with an average power consumption per preamplifier of 52 microW, which is consistent with simulation results. As a proof-of-concept demonstration, we have measured local field potentials from thalamocortical brain slices of rats, showing oscillatory behavior with an amplitude about 0.5 mV and a period ranging 80-120 ms. The results suggest that the hybrid integrated neuroport can form a prime platform for the development of a next level microminiaturized neural interface to the brain in a single implantable unit.

Analysis of 1/f noise in CMOS preamplifier with CDS circuit

The noise of a CMOS charge-sensitive preamplifier (CSA) and correlated double sample-and-hold (CDS) circuit matching a capacitive source is calculated to analyze the relative portions of thermal and 1/f noise. In most radiation detector systems, a PMOS transistor is used as the input device because its 1/f noise is lower than that of the NMOS. However, to study the 1/f noise reduction action of a CDS circuit in the 1/f noise dominant condition, an NMOS transistor is deliberately chosen as the input transistor of the CSA. The theoretical minimum number of equivalent noise charge (ENC) that can be achieved in this system is about 1700 electrons rms for a 5-pF detector capacitance. To demonstrate the theoretical analysis, a chip of CSA and CDS was designed in a 0.5-/spl mu/m CMOS technology. The main amplifier is a differential input single-ended folded cascode, and its measured gain bandwidth is more than 5 MHz. The measured ENCs of the CSA shaper and the CSA-CDS systems are 2105 and 3046 electrons rms, respectively.

Novel cell-AGC technique for burst-mode CMOS preamplifier with wide dynamic range and high sensitivity for ATM-PON system

We propose a novel cell-AGC technique for an ATM-cell-based burst optical receiver on a 156-Mb/s subscriber system. The cell-AGC controls transimpedance gain according to the burst-cell power and enables reception of burst signals with low extinction ratio. In addition, to realize high sensitivity, we developed an amplifier that is stable under changes in ambient conditions and deviations of transistor characteristics on IC. By adopting these techniques in a CMOS preamplifier IC, the detectable power difference between burst cells was enlarged to more than 30 dB, and the minimum sensitivity was improved to less than -39.3 dBm. These performances show that our new IC fully satisfies the high-sensitivity specification of an ATM-PON system, and incorporating this IC in the system makes it more flexible and economical.

Performance analysis of phoswich/APD detectors and low-noise CMOS preamplifiers for high-resolution PET systems

An integrated 0.8-/spl mu/ CMOS charge-sensitive preamplifier previously designed for LSO/APD-based positron emission tomography (PET) systems has been further investigated for use with multicrystal/avalanche photodiode (APD) PET detectors. In addition to low-noise wide-band performance and power efficiency, high dynamic range and good signal-to-noise ratio over a broad range of shaping times are required to process the signals from crystals being used in phoswich detectors, which have a wide range of scintillation decay time and light output characteristics. The preamplifier equivalent noise charge (N/sub eq/) was measured as a function of input capacitance and amplifier-shaping time constant. The performance of the preamplifier was also assessed using APDs coupled to a variety of scintillators. Measurements were obtained at a preamplifier input-device current of 2 and 4 mA. The higher bias led to marginal improvements of the timing performance but had no effect on energy resolution. The very low noise of the preamplifier allows optimum timing performance to be obtained at lower APD gain and improves crystal identification by pulse shape discrimination with phoswich detectors.

A 455-Mb/s MR preamplifier design in a 0.8-μm CMOS process

In this paper, we present a CMOS preamplifier for use with magnetoresistive (MR) read elements in disk drives. The performance of the CMOS design is competitive with the more expensive current generation of BiCMOS MR preamplifiers. The measured gain for the preamplifier is 43 dB and the measured 3-dB bandwidth is greater than 273 MHz corresponding to a 455-Mb/s data rate. Likewise, the measured input-referred voltage noise is less than 0.57 nV//spl radic/Hz, and measured input-referred current noise is less than 10.54 pA//spl radic/Hz at an MR bias current of 10 mA, The preamplifier has been implemented in a 0.8-/spl mu/m 5 V CMOS process and occupies a die area of 1.78/spl times/1.78 mm/sup 2/ In this paper, we introduce a new scheme to reduce current noise below that contributed by a single MOS device, This technique has the potential for even more impact for future submicron processes. We also showed that voltage amplifiers offer lower noise than transimpedance amplifiers for similar gain and bandwidth constraints.

A power-efficient, low-noise, wideband, integrated CMOS preamplifier for LSO/APD PET systems

A power-efficient, low-noise, wideband, 0.8-/spl mu/ CMOS charge-sensitive preamplifier has been designed and optimized for LSO/APD based PET systems. Low-noise, wideband performance is needed to achieve 1-ns FWHM timing resolution available from LSO/APD detectors, and power efficiency is needed since thousands of preamplifiers are required in a LSO/APD based PET tomograph. A methodology for optimizing wideband timing performance is presented to minimize dominant, frequency-turn-up, input-noise current associated with input noise voltage and total capacitance at the input. The methodology suggests the use of a nMOS input device operating in moderate inversion for high transconductance and low input white-noise voltage consistent with moderate input capacitance. Measured preamplifier input-referred, white-noise voltage is 0.65 mV//spl radic/Hz and risetime is 6 ns (58 MHz 3-dB bandwidth). Measured timing resolution is 1.15 ns FWHM and energy resolution is 12.1% FWHM for 511-keV gamma rays detected by a 4/spl times/4/spl times/10 mm LSO crystal coupled to an APD. Measurements include the APD capacitance of 30 pF and are obtained at a preamplifier input-device current of only 2 mA.

Noise performance design of CMOS preamplifier for the active semiconductor neural probe

A systematic design guideline is presented for the noise performance of preamplifier for semiconductor neural probe which contains on-chip electronic circuitry. The overall signal-to-noise ratio (SNR) is calculated considering the spectral characteristics of the measured extracellular action potential and the low-frequency noise spectrum of the CMOS device from typical fabrication processes. An analytical expression of the output noise power is derived, and utilized to tailor the frequency response and device parameters which are controllable by the circuit designer. An analysis of the output SNR of a two-stage CMOS differential amplifier is given and the major factors which have significant effects on the SNR are determined. We showed that a little deviation of the input device sizes and transconductance ratio from the optimal values can significantly deteriorate the SNR. Quantitative information of the preamplifier circuit parameters for satisfactory noise performance is provided.

A high CMRR current mode CMOS preamplifier for magnetic recording systems

This paper presents a high CMRR current mode CMOS preamplifier for a dual stripe magnetoresistive (DSMR) read head for magnetic recording systems. The current mode design approach a avoids high impedance nodes in the circuit and helps in achieving a high bandwidth. The differential circuit topology and the common mode negative feedback greatly improve the CMRR and PSRR. The preamplifier is designed using a 0.5 /spl mu/m CMOS technology. The achieved 3-dB bandwidth is 120 MHz at a gain of 45 dB, the CMRR and PSRR are 62 and 74 dB respectively. The equivalent input noise voltage is 1.83 nV//spl radic/Hz.

Ultra Low Noise CMOS preamplifier-shaper for X-ray spectroscopy

We report here an Ultra Low Noise CMOS charge-sensitive amplifier (CSA) and a CSA-Shaper for X-ray spectroscopy, suitable for a small anode capacitance, low leakage current solid state detector. The continuously sensitive CSA and CSA-Shaper use a MOS transistor MF to discharge the integration capacitance; a novel self-bias circuit biases MF in the GΩ region (subthreshold region) while tracking process, temperature and supply voltage variations. A T-Network in the DC-feedback improves the CSA gain linearity (within 0.1% up to 1.8fC input charge).The CSA-Shaper features a novel Adaptive Pole-Zero cancellation scheme: the Zero in the Shaper adapts itself statically and dynamically to cancel the CSA Pole.The noise performance of the CSA has been measured: with no detector connected and MF pinched, the room-temperature equivalent noise charge (ENC) is 9erms at 12μs shaping time. When connected to a cooled detector (T=−75°C), with MF in pinch off, an ENC of 13erms is achieved (FHWM=111eV) at 2.4μs shaping time. This is the best reported energy resolution ever obtained with a CMOS preamplifier.

8-channel CMOS preamplifier and shaper with adjustable peaking time and automatic pole-zero cancellation

An 8-channel preamplifier-shaper circuit for use with detectors having a capacitance in the range 20–50pF has been designed in 1.2μ CMOS AMS technology. The shaper is designed so that the peaking time can be adjusted, by steps, in the range 200ns–2μs by simple digital control. The pole-zero cancellation circuit uses an original method of sensing the preamplifier feedback capacitor discharging current and producing an identical current to discharge the capacitance of the pole-zero cancellation circuit. The series noise resistance rs=415Ω has been measured (270Ω of which is the protection resistor). The input capacitance of the preamplifier is 10pF + the strays of the test box 10pF for a total of 20pF. The input PMOS transistor has a gm of 5mA/V (from simulation) at 210μA drain current. The cross-talk between channels is less than 1%.

SIMMWIC rectennas on high-resistivity silicon and CMOS compatibility

Rectifying antennas (rectennas) are realized on high-resistivity silicon substrates using silicon monolithic millimeter-wave integrated circuit (SIMMWIC) technology. Monolithically integrated coplanar Schottky barrier diodes are used as rectifying elements embedded in different antenna structures. Both p- and n-type Schottky barrier diodes are realized with cutoff frequencies up to 1 THz. The rectennas are combined with a CMOS preamplifier mounted as a multichip module (MCM) next to the rectenna on a high-resistivity silicon substrate. An amplification of 32 dB is measured. Maximum sensitivity of the detector circuit including preamplification is 1600 mV/mW/spl middot/cm/sup -2/ at 94.6 GHz. For a monolithic integration of high-frequency circuits with low-frequency control and signal-processing electronics, the monolithic integration of CMOS circuitry on high-resistivity silicon is discussed.

CMOS preamplifier with high linearity and ultra low noise for X-ray spectroscopy

We report here an ultra low noise charge sensitive monolithic CMOS amplifier (CSA) suitable for small anode capacitance (200 fF), low leakage current solid state detectors. The CSA is continuously sensitive, the charge from the input node being drained by a feedback transistor Mf biased as a resistor with effective values in the G/spl Omega/ range. This very high value was achieved by a novel scheme which tracks threshold variations, and power supply and temperature fluctuations. A good linearity of the CSA conversion gain is achieved (<0.1% up to 1.8 fC input charge) by inserting a voltage divider between the output of the CSA and the source of Mf. The equivalent noise charge (ENC) of the CSA is equal to the theoretical lower limit imposed by the flicker noise. The circuit has been fabricated in two different CMOS technologies. With no detector connected, we measure a room-temperature ENC of 9 e/sup -/ rms at 12 /spl mu/sec shaping time. When coupled to a cooled detector a FWHM of 111 eV is obtained at 2.4 /spl mu/sec shaping, corresponding to an ENC of 13 e/sup -/ rms. This is the best reported energy resolution ever obtained with a CMOS preamplifier.

CMOS preamplifier for low-capacitance detectors

We present a new CMOS preamplifier and shaper, optimized for charge measurements with detectors of 0.1–1 pF capacitance. A self-adaptive biasing scheme with nonlinear pole-zero cancellation allows us to use an MOS device operated in the triode region as the DC feedback element while eliminating nonlinearity and sensitivity to supply, temperature, and process variations and accepting up to several μA leakage current. The circuit is continuously sensitive and requires no external adjustments to set the feedback resistance. Secondary sources of noise are minimized subject to a power dissipation constraint. Implemented in a 1.2 μm CMOS process, the preamplifier achieves an ENC of 35 e − + 58 e −/pF at 23 μs shaping time at a power consumption of about 3.2 mW. The integrated preamp/shaper has 50 ns shaping time and the ENC is 120 e −. It has 0.3% nonlinearity over an input dynamic range of 0–5 fC.

Study of common-mode noise of the SMA 2SH - 64 A preamplifier array

Employing a 64-channel CMOS preamplifier array, SMA 2SH - 64 A, we studied its signal-to-noise ratio. Single-channel noise was substantially contaminated with a base-line shift, which was common for all neighboring channels. Subtracting the common base-line shift, we found that the noise level decreased to be acceptable in terms of the design parameters as well as for practical use.

Construction and test of a fine-grained liquid argon preshower prototype

A separate liquid argon preshower detector consisting of two layers featuring a fine granularity of 2.5 × 10 −3 was studied by the RD3 collaboration. A prototype covering approximately 0.8 in pseudo-rapidity and 9° in azimuth was built and tested at CERN in July 94. CMOS and GaAs VLSI preamplifiers were designed and tested for this occasion. The combined response of this detector and an accordion electromagnetic calorimeter prototype to muons, electrons and photons is presented. For minimum ionizing tracks a signal-to-noise ratio of 4.5 per preshower layer was measured. Above 150 GeV the space resolution for electrons is better than 250 μm in both directions. The precision on the electromagnetic shower direction, determined together with the calorimeter, is better than 4 mrad above 50 GeV. It is concluded that the preshower detector would adequately fulfil its role for future operation at CERN Large Hadron Collider.

Scaleable CMOS Current-Mode Preamplifier Design for an Optical Receiver

We have designed a process-insensitive preamplifier for an optical receiver, fabricated it in several different minimum feature sizes of standard digital CMOS, and demonstrated design scaleability of this analog integrated circuit design. The same amplifier was fabricated in a 1.2 µm and two different 0.8 µm processes through the MOSIS foundry [1]. The amplifier uses a multi-stage, low-gain-per-stage approach. It has a total of 5 identical cascaded stages. Each stage is essentially a current mirror with a current gain of 3. Three of these preamplifiers have been integrated with a GaAs Metal-Semiconductor-Metal (MSM) photodetector and one with an InGaAs MSM detector by using a thin-film epilayer device separation and bonding technology [2]. This quasi-monolithic front-end of an optical receiver virtually eliminates the parasitics between the photodetector and the silicon CMOS preamplifier. We have demonstrated speed and power dissipation improvement as the minimum feature size of the transistors shrink.

Design of a low noise, low power consumption CMOS preamplifier shaper for readout of microstrip detectors in the DMILL radiation hardened process and irradiation measurements

One of the proposed schemes of microstrip detector readout in the future LHC collider experiments is the use of a slow preamplifier with subsequent analog pulse shape processing (deconvolution) to recover initial time information. Following this idea a CMOS preamplifier shaper (CR-RC active filter) with 75 ns shaping time has been designed using a radiation hardened process DMILL. The tests of a prototype chip show a noise performance of ENC = 330 e− + 51 e−pF for a peaking time of 100 ns, gain of 30 mV/MIP and a power consumption of 1.1 mW per channel. Measurements after irradiation by γ photons, electrons and neutrons are also presented in this paper.

Charge-partitioning study of a wide-pitch silicon micro-strip detector with a 64-channel CMOS preamplifier array

Abstract The wider pitch readout operation of a 50 μm-pitch double-sided silicon micro-strip detector has been studied specifically concerning its ohmic side. Every second readout and ganged configuration was examined by employing a newly developed 64-channel preamplifier array. The observed charge responses for collimated IR light were compared with a numerical model.

Single-channel prototype of a CMOS SVD preamplifier for the B-factory experiment, BELLE

A single-channel CMOS preamplifier circuit was fabricated as a part of R&D efforts to design a 128-channel preamplifier chip for a silicon vertex detector of the BELLE collaboration. The prototype chip was evaluated in detail with special emphasis being placed on its analog circuit design and performance. An eight-stage digital/analog pipe-line, and a quadruple-correlated noise filter with a low-noise preamplifier circuit include key technologies for the design.

Assessment for the stabilization of a front-end circuit

An assessment for the stabilization of a front-end circuit is described in terms of a scattering matrix, where the key issue is unconditional stability. A CMOS preamplifier, designed for a silicon microstrip detector, is evaluated concerning its quality of unconditional stability.