CMOS Preamplifier Research Articles

A cryogenic low-background low-noise CMOS preamplifier for HPGe detectors

A cryogenic low-noise CMOS preamplifier has been successfully developed for HPGe detectors in low-background experiments. Commonly used auxiliary off-chip devices, such as decoupling capacitors and resistors, were removed to control the radioactive emission. The prototype chip was implemented in XFAB 350 nm CMOS process and was fully evaluated. A minimum ENC of 8.9 electrons was obtained at a 12 μs shaping time at 77 K, and the rise time was measured to be 60 ns through a 1-meter-long cable. The performances with and without decoupling capacitors for the power supply and bias voltages were compared, and there was no evident difference between these cases. The performance upon connection to a 0.5 kg point-contact HPGe detector was also measured. A minimum ENC of 15.5 electrons was achieved. The energy spectrum of the 57Co radiation source was obtained, and the FWHM of the 122 keV energy peak was measured to be 0.6 keV.

Hexagonal Pad Multichannel Ge X-Ray Spectroscopy Detector Demonstrator: Comprehensive Characterization

One of the major limitations of X-ray Absorption Spectroscopy (XAS) experiment at synchrotron facilities is the performance of the detectors. In order to be able to measure more challenging samples and to cope with the very high photon flux of the current and future (diffraction limited) sources, technological developments of detectors are necessary. This article reports on the construction and characterization of a monolithic 19-channel germanium detector demonstrator fitted with CMOS preamplifiers. The detector was characterized in the laboratory with radioactive sources and with the X-ray synchrotron beam. Characteristics such as energy resolution, linearity, counting rate capabilities, and stability of the detector were thoroughly evaluated. In addition, it was proved that by using an advanced pulse processor such as Xspress4, it was possible to improve the performance of the detector system by eliminating the crosstalk among channels and by suppressing the charge-shared events. This work could pave the way to enhanced germanium fluorescence detectors for high-throughput X-ray spectroscopy.

Pixel Drift Detector (PixDD) – SIRIO: an X-ray spectroscopic system with high energy resolution at room temperature

An X-ray spectroscopic system composed of a novel Pixel Drift Detector (PixDD) and SIRIO charge sensitive preamplifier is presented. The PixDD prototype is a 4 × 4 matrix of 500μm×500μm pixels, manufactured on a 450μm thick, 9kΩcm silicon wafer. The anode current of a pixel is 0.7 pA at +20 °C and decreases down to tens of fA for temperatures lower than 0 °C. The low current together with the low pixel capacitance (30 fF independent of the pixel area), make PixDD an extremely low noise detector. When PixDD is coupled to the ultra-low noise SIRIO CMOS preamplifier, intrinsic spectral line widths (pulser) of 51 eV FWHM (5.9 electrons r.m.s.) and 130 eV FWHM at 5.9 keV (55Fe) are obtained at +20 °C. If the system is slightly cooled down to 0 °C, the FWHMs decrease down to 38.5 eV (4.5 electrons r.m.s) and 127 eV for the pulser and the 5.9 keV line respectively. The high energy resolution of PixDD joined with its intrinsic position sensitivity and the possibility to sustain high photon fluxes open new perspectives in X-ray spectroscopic imaging in the 0.1 keV–20 keV energy range.

Characterization of ARDESIA: a 4-channel SDD X-ray spectrometer for synchrotron measurements at high count rates

ARDESIA is an SDD-based, X-ray spectrometer, optimized for synchrotron measurements that require high count rates (>1 Mcounts/s/channel) and good energy resolution (<130 eV of FHWM Mn-Kα line at optimum shaping time, ⩽ 200 eV at short shaping times). The main target applications are XRF and XAFS techniques. The detection module consists of 2×2 pixel monolithic SDD (5 mm pitch) coupled with a 4-channel version of the CUBE CMOS preamplifier. The mechanical structure of the instrument has been realized to fit inside a sample chamber with a finger-like structure. The system grants proper cooling (-40oC) and operation in vacuum. ARDESIA is also equipped with two auxiliary electronic boards: one for SDD powering and biasing and the other for closed-loop driving of two Peltier TECs. The output signals of the instrument are processed by digital pulse processors using short pulse processing times in order to achieve good spectroscopic performance at high count rates. Two different measurement campaigns were performed at synchrotron beamlines to assess the performance of the instrument. At the LNF DAΦNE-Light DXR1 soft X-ray beamline, XRF measurements on low atomic number elements (down to C-K line, 277 eV) demonstrated the good energy resolution of the spectrometer and made possible to acquire the first XAFS spectrum of Silicon K-edge in a PyrexTM glass sample. At the LISA CRG beamline at ESRF—Grenoble, XAFS measurements on different samples, such as kesterite and protochabourn'eite, were performed, demonstrating the high count rate capability and stability of the instrument over time.

SFERA: An Integrated Circuit for the Readout of X and &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\gamma $ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Ray Detectors

In this work we present SFERA, a low-noise fully-programmable 16 channel readout ASIC designed for both X- and $\gamma $ -ray spectroscopy and imaging applications. The chip is designed to process signals coming from solid-state detectors and CMOS preamplifiers. The design has been guided by the use of Silicon Drift Detectors (SDDs) and CUBE charge sensitive amplifiers (CSAs), although we consider the ASIC sufficiently versatile to be used with other types of detectors. Five different gains are implemented, namely $2800~e^{-}$ , $4400~e^{-}$ , $10000~e^{-}$ , $14000~e^{-}$ and $20000~e^{-}$ , considering the input connected to a 25 fF feedback capacitance CMOS preamplifier. Filter peaking times ( $\mathrm {t}_{P}$ ) are also programmable among 0.5, 1, 2, 3, 4 and 6 $\mu \mathrm {s}$ . Each readout channel is the cascade of a 9th order semi-Gaussian shaping-amplifier (SA) and a peak detector (PKS), followed by a dedicated pile-up rejection (PUR) digital logic. Three data multiplexing strategies are implemented: the so-called polling X , intended for high-rate X-ray applications, the polling $\gamma $ , for scintillation light detection and the sparse , for signals derandomization. The spectroscopic characterization has shown an energy resolution of 122.1 eV FWHM on the Mn- $\mathrm {K}_{\alpha }$ line of an 55Fe X-ray source using a $10~\mathrm {mm}^{2}$ SDD cooled at −35 °C at $4~\mu \mathrm {s}$ filter peaking time. The measured resolution is 130 eV at the peaking time of 500 ns. At 1 Mcps input count rate and 500 ns peaking time, we have measured 42% of processed events at the output of the ASIC after the PUR selection. Output data can be digitized on-chip by means of an embedded 12-bit successive-approximation ADC. The effective resolution of the data converter is 10.75-bit when operated at 4.5 MS/s. The chosen technology is the AMS $0.35~\mu \mathrm {m}$ CMOS and the chip area occupancy is $5\times 5~\mathrm {mm}^{2}$ .

A new detector system for low energy X-ray fluorescence coupled with soft X-ray microscopy: First tests and characterization

The last decades have witnessed substantial efforts in the development of several detector technologies for X-ray fluorescence (XRF) applications. In spite of the increasing trend towards performing, cost-effective and reliable XRF systems, detectors for soft X-ray spectroscopy still remain a challenge, requiring further study, engineering and customization in order to yield effective and efficient systems. In this paper we report on the development, first characterization and tests of a novel multielement detector system based on low leakage current silicon drift detectors (SDD) coupled to ultra low noise custom CMOS preamplifiers for synchrotron-based low energy XRF. This new system exhibits the potential for improving the count rate by at least an order of magnitude resulting in ten-fold shorter dwell time at an energy resolution similar to that of single element silicon drift detectors.

Development of arrays of Silicon Drift Detectors and readout ASIC for the SIDDHARTA experiment

This work deals with the development of new Silicon Drift Detectors (SDDs) and readout electronics for the upgrade of the SIDDHARTA experiment. The detector is based on a SDDs array organized in a 4×2 format with each SDD square shaped with 64mm2 (8×8) active area. The total active area of the array is therefore 32×16mm2 while the total area of the detector (including 1mm border dead area) is 34×18mm2. The SIDDHARTA apparatus requires 48 of these modules that are designed and manufactured by Fondazione Bruno Kessler (FBK). The readout electronics is composed by CMOS preamplifiers (CUBEs) and by the new SFERA (SDDs Front-End Readout ASIC) circuit. SFERA is a 16-channels readout ASIC designed in a 0.35μm CMOS technology, which features in each single readout channel a high order shaping amplifier (9th order Semi-Gaussian complex-conjugate poles) and a high efficiency pile-up rejection logic. The outputs of the channels are connected to an analog multiplexer for the external analog to digital conversion. An on-chip 12-bit SAR ADC is also included. Preliminary measurements of the detectors in the single SDD format are reported. Also measurements of low X-ray energies are reported in order to prove the possible extension to the soft X-ray range.

Monolithic arrays of SDDs and low noise CMOS readout for X-ray spectroscopy measurements in nuclear physics experiments

This work deals with the development of Silicon Drift Detectors (SDDs) of different sizes and low noise CMOS read-out preamplifiers in view of their use in nuclear physics experiments, like the SIDDHARTA upgrade supported by Italian INFN. In this work we report about the recent SDDs and CMOS preamplifiers development, with particular emphasis on X-ray measurements at cryogenic temperatures. The SDDs presented are designed as single square shaped units of different areas 64 mm2 (8mm × 8mm) or 144 mm2 (12mm × 12mm) and also as monolithic arrays of 9 elements (8mm × 8mm each, total area 26mm × 26mm) in a3 × 3 format. The detectors have been designed and manufactured by the Fondazione Bruno Kessler (FBK). The read-out of the SDDs is based on the CMOS preamplifier (CUBE) for both the single unit and the 3 × 3 array. The CMOS technology is intrinsically more robust at lower temperatures with respect to the more conventional JFET transistor used in SDDs readout. A measured resolution of 123 eV on the Mn-Kα line with the optimum shaping time and a resolution of 126.4 eV with 250 ns shaping time have been obtained with round shaped 10 mm2 SDDs detectors. This last result leads to excellent spectroscopy performances even with very high input count rates making the SDD+CUBE combination very attractive also for synchrotron applications. The nine detectors array in addition to the preamplifiers the use of a multichannel ASIC for signal shaping and peak detection of all the units and of a custom Data Acquisition System. Also preliminary measurements of low energies lines are reported in order to prove the possibility of soft X-ray detection.

Monolithic Multi-Element HPGe Detector Equipped With CMOS Preamplifiers: Construction and Characterization of a Demonstrator

Multi-element germanium detectors for X-ray fluorescence are widely used in synchrotron experiments and in particular in XAFS experiments. This paper presents the construction and characterization of a demonstrator built to investigate the viability of multi-element monolithic germanium detectors equipped with CMOS front-end electronics. Semikon Detector GmbH fabricated a germanium sensor segmented with a pad pattern with pad size 1×1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . 16 channels were instrumented with the CUBE preamplifiers developed at XGLab Srl. The detector was tested with radioactive sources and with the synchrotron X-ray beam of Diamond. The results showed spectra with energy resolution satisfactory for XAFS experiments but with a considerable tail. The low energy tail was proved to be due to charge sharing. In addition the spectra showed the peak stability as a function of counting rate better than 1% for rate up to 838 kcps. The non-linearity of the peak position vs. energy was estimated to be a maximum of 0.13% No evidence of charge loss in the crystal was identified. This work proved that this technology is a viable option to improve the throughput of germanium fluorescence detectors as long as methods to reduce events leading to charge sharing are in place.

Design of Pre-Amplifiers for Photoelectric Detector

This paper presents the design of low noise CMOS pre-amplifiers based on photoelectric detection systems, which can directly affect the detecting precision of the whole systems. The design of pre-amplifier circuit from photoelectric detector was introduced. The photoelectric conversion circuit, amplifier circuit bandwidth, amplifier circuit noise, amplifier circuit stabilization and other questions were mainly discussed, and an amplifier circuit capable of effectively decreasing the noise, the temperature drift and a large dynamic range was designed. This paper analyzes the sources of photoelectric detection circuit internal noise, and gives the formulas of internal noise, designs a variable equivalent load photoelectric conversion circuit, and is verified by experiments. Then the result is used to reduce the noise of CMOS based operational amplifiers and finally implement the design work of pre-amp using 0.5μm CMOS Technology.

A Multichannel Integrated Readout Circuit for High Throughput X-Ray Spectroscopy With Silicon Drift Detectors

In this paper, we describe a front-end ASIC for the readout of multi-elements Silicon Drift Detectors (SDDs) specifically designed for high count-rate X-ray spectroscopy applications. In particular, the focus of this design is on the maximization of the event throughput and, at the same time, keeping a high energy resolution. The readout of a detector array by means of 8 separate channels allows increasing the maximum count-rate of the system. The use of one or more of these front-end ASICs allows the management of several readout channels required by a multi-SDD detector within a very compact detection system, as well as maintaining excellent noise performance. The use of a very-fast high-order processing filter and of an efficient pile-up rejection strategy allows minimizing the pile-up probability and maximizing the event throughput of the single channels for a given processing time. The use of a 3-phase peak-stretcher, together with a fast output multiplexer, permits to minimize the dead-time during the valid-data acquisition, practically to a value limited by the pure overlap of the shaped pulses. The ASIC is designed with the possibility of operating with the input JFET integrated on the detector itself as well as to operate in combination with an external preamplifier. The measured noise-contribution added by the front-end ASIC is only 2.9 electrons at 1.8 μs shaping time and just 4.1 electrons at the shortest 600 ns peaking time, exploiting at best the speed capability. In X-ray spectroscopy measurements, the ASIC connected to an SDD coupled to a CMOS preamplifier has allowed to achieve an energy resolution of 126 eV at 1.5 μs peaking time and 115 kcps/channel input rate, and 144 eV at 600 ns peaking time and 800 kcps/channel input rate.

Design and characterization of a CMOS preamplifier for quantum well infrared photodetectors

A preamplifier based on the source-follower direct injection (SFDI) topology for use in read-out integrated circuits (ROIC) of quantum-well infrared photodetectors focal plane arrays (QWIP-FPA) is demonstrated. The fabricated circuit shows high linearity, high integration time (from hundreds of μs to few ms) and low current detection capabilities for a wide range of input current (order of few pA). This performance was achieved through the use of a Poly1-Poly2 capacitor that, although presenting some penalties in area consumption, provides a higher linearity, lower leakage current and higher temperature stability than all others capacitors found in literature. Secondary effects such as charge injection and clock feed-through are observed in the experimental results and classical techniques, like the use of DUMMY transistor, are shown to be effective in minimizing these effects and maximizing the linearity of the response. The overall results indicate that this circuit architecture has a great potential to be practically integrated in larger QWIP-FPA ROICs, showing an improved performance relating to previous works in literature.

High-Bandwidth Solid-State Nanopore Sensors

Nanopores are attractive electrochemical sensors for their single-molecule sensitivity and simple experimental setup. Many of the electronic systems used for nanopore measurements are inherited from electrophysiology applications, and as a result they are primarily optimized for current levels of 50pA or less, at bandwidths below 10kHz. However, state-of-the-art solid-state nanopore sensors now commonly produce signals in the nanoampere range, for which common patch clamp amplifiers are no longer ideal. We present a new experimental platform which integrates a custom CMOS preamplifier with nanopores in thin silicon nitride membranes. The low parasitic capacitance of the integrated platform reduces noise at high frequencies, allowing nanopore measurements at finer temporal resolution than supported by popular instruments. We demonstrate the viability of this system with high-bandwidth electrical recordings of the passage of short DNA molecules through nanopores. This new platform will improve the signal-to-noise ratios of nanopore sensors, enabling further single-molecule studies of fast biophysical processes.

Development of integrated preamplifier for high-frequency ultrasonic transducers and low-power handheld receiver

This paper describes the design of a front-end circuit consisting of an integrated preamplifier with a Sallen-Key Butterworth filter for very-high-frequency ultrasonic transducers and a low-power handheld receiver. This preamplifier was fabricated using a 0.18-μm 7WL SiGe bi-polar complementary metal oxide semiconductor (BiCMOS) process. The Sallen-Key filter is used to increase the voltage gain of the front-end circuit for high-frequency transducers which are generally low in sensitivity. The measured peak voltage gain of the frontend circuits for the BiCMOS preamplifier with the Sallen-Key filter was 41.28 dB at 100 MHz with a-6-dB bandwidth of 91%, and the dc power consumption of the BiCMOS preamplifier was 49.53 mW. The peak voltage gain of the front-end circuits for the CMOS preamplifier with the Sallen-Key filter was 39.52 dB at 100 MHz with a-6-dB bandwidth of 108%, and the dc power consumption of the CMOS preamplifier was 43.57 mW. Pulse-echo responses and wire phantom images with a single-element ultrasonic transducer have been acquired to demonstrate the performance of the front-end circuit.

0.5-V Low-$V _{\rm T}$ CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays

A novel low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of a sense amplifier (SA) with the proposed preamplifier and its activation schemes at a data-line voltage of 0.5 V was 6 ns, which is 62% shorter than that of an SA using a conventional preamplifier. By activating the proposed preamplifier temporarily during the write cycle, the writing time was 16.3 ns, which is 72% shorter than the case without activation of the proposed preamplifier, and this time is short enough to apply a DRAM array using the proposed preamplifier to 1.6-Gbit/s/pin DDR3 SDRAM. The operating current of the memory array and its peripheral circuit including the proposed preamplifier was reduced by 12% by reducing the data-line voltage from 0.8 to 0.5 V.

Advances in silicon carbide X-ray detectors

Abstract The latest advances in SiC X-ray detectors are presented: a pixel detector coupled to a custom ultra low noise CMOS preamplifier has been characterized at room and high temperature. An equivalent noise energy (ENE) of 113 eV FWHM, corresponding to 6.1 electrons r.m.s., has been achieved with the detector/front-end system operating at +30 °C. A Fano factor of F =0.10 has been estimated from the 55 Fe spectrum. When the system is heated up to +100 °C, the measured ENE is 163 eV FWHM (8.9 electrons r.m.s.). It is determined that both at room and at high temperature the performance are fully limited by the noise of the front-end electronics. It is also presented the capability of SiC detectors to operate in environments under unstable temperature conditions without any apparatus for temperature stabilization; it has been proved that a SiC detector can acquire high resolution X-ray spectra without spectral line degradation while the system temperature changes between +30 and +75 °C.

2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

This paper reports an optical preamplifier intended for low-cost fiber-optic receivers. The preamplifier is based on a resistive shunt-feedback topology, is power-optimized and employs two different frequency compensation techniques, phantom zeros and shunt-peaking. The circuit is designed in a 1.8 V 0.18 μm CMOS technology. Experimental results report a transresistance of 58 dB? and a bandwidth of 1.5 GHz, respectively. Eye diagrams obtained at 2.5 Gb/s show a total jitter of 18 ps and a bit error rate (BER) of 10?12 when the input current amplitude (Iin) is equal to or higher than 8.5 μA. Higher bit rates up to 3 Gb/s also have been tested achieving a BER of 10?12 when Iin ?9.5 μA. The power consumption and die active area are 23.7 mW and 0.017 mm2, respectively.

Low-noise low-power CMOS preamplifier for multisite extracellular neuronal recordings

This paper reports the design and the experimental results of a fully integrated, low-noise, low-power standard CMOS preamplifier circuit used to record the extracellular electrophysiological activity of in vitro biological neuronal cultures. Our goal is to use the preamplifier in a fully integrated, multi-channel, bi-directional neuro-electronic interface.Among others, two main requirements must be addressed when designing such kind of integrated recording systems: noise performance and very low frequency disturbance rejection. These two requirements need to be satisfied together with a small silicon area design, to be able to integrate a large number of recording channels (i.e. up to thousands) onto a single die. A prototype preamplifier circuit has been designed and implemented; in this paper we report the experimental results.While satisfying the above requirements, our circuit offers state-of-the-art smallest area occupation (0.13mm2) and consumes 4.5μW. Sub-threshold-biased lateral pnp transistors, used to implement very high resistance value integrated resistors, have been characterized to determine the resistance spread.The fabricated prototype, coupled with a commercial Micro-Electrode Array (MEA), has been successfully employed to record the extracellular electrophysiological spontaneous activity, both of muscular cardiac cells (cardiomyocytes) and of spinal cord neurons from murines.

A Fully On-Chip Gm-Opamp-RC Based Preamplifier for Electret Condenser Microphones

An on-chip CMOS preamplifier for direct signal readout from an electret capacitor microphone has been designed with high immunity to common-mode and supply noise. The Gm-Opamp-RC based high impedance preamplifier helps to remove all disadvantages of the conventional JFET based amplifier and can drive a following switched-capacitor sigma-delta modulator in order to realize a compact digital electret microphone. The proposed chip is designed based on 0.18µm CMOS technology, and the simulation results show 86dB of dynamic range with 4.5µVrms of input-referred noise for an audio bandwidth of 20kHz and a total harmonic distortion (THD) of 1% at 90mVrms input. Power supply rejection ratio (PSRR) and common-mode rejection ration (CMRR) are more than 95dB at 1kHz. The proposed design dissipates 125µA and can operate over a wide supply voltage range of 1.6V to 3.3V.

DRAGO chip: a low-noise CMOS preamplifier shaper for silicon detectors with integrated front-end JFET

We present a CMOS preamplifier-shaper circuit designed to be used with low-noise solid-state detectors, like silicon drift detectors (SDDs), in X-ray Spectroscopy and /spl gamma/-ray imaging applications. The circuit is composed of a low-noise preamplifier and by a sixth-order semi-Gaussian shaping amplifier with four selectable peaking times from 1.7 /spl mu/s up to 6 /spl mu/s. The integrated time constants used for the shaping are implemented by means of a recently proposed "RC" cell. This cell is based on the demagnification of the current flowing in a resistor R thanks to the use of current mirrors. The particular solution adopted here allows a precise and stable implementation of the desired time constant, for given values of R and C , and guarantees low-noise performances of the shaping amplifier when used with a cooled SDDs or other solid-state detectors with low leakage current. In this work, the main features of the circuit are first presented. The experimental results obtained with a prototype realized in the 0.35-/spl mu/m 3.3-V CMOS austriamicrosystems technology are then reported and discussed. The energy resolution measured using the chip with a SDD cooled at -10/spl deg/C is 150 eV at 6 keV which corresponds to an electronics noise of 10.8 e-rms.