CMOS Pass Transistor Logic Research Articles

HYBRID-CMOS LOGIC STYLE DESIGN FOR FAST SELF-CHECKING ADDERS DATA PATHS

In this paper we present an efficient design for self-checking fast adders data paths. We investigate the implementation of concurrent error detection fast adders: carry look-ahead, Carry skip, Carry-select and Conditional-Sum adders. To achieve a low overhead, low power design, we use hybrid-CMOS logic style and combine Conventional CMOS and CMOS Pass transistor Logic (CPL). The proposed schemes are Totally Self-Checking (TSC). They are fully differential and checked by dual-rail and parity codes.

A novel differential XOR-based self-checking adder

Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage and reduced hardware cost with reduced design effort. The aim of this study is to contribute to reach these requirements for the design of self-checking adders/arithmetic logic units. In this article, we present efficient self-checking implementations for adder schemes using the dual duplication code. Among the known self-checking adder designs, the dual duplicated scheme has the advantage to be totally self-checking for single faults. The drawback of this scheme is that it requires generally the maximum hardware overhead. In this study, we propose a low cost implementation for self-checking adder. The proposed design is based on a novel differential XOR gate implemented in CMOS pass transistor logic, and performed with only four transistors.

Cell-based top-down design methodology for RSFQ digital circuits

We propose a cell-based top-down design methodology for rapid single flux quantum (RSFQ) digital circuits. Our design methodology employs a binary decision diagram (BDD), which is currently used for the design of CMOS pass-transistor logic circuits. The main features of the BDD RSFQ circuits are the limited primitive number, dual rail nature, non-clocking architecture, and small gate count. We have made a standard BDD RSFQ cell library and prepared a top-down design CAD environment, by which we can perform logic synthesis, logic simulation, circuit simulation and layout view extraction. In order to clarify problems expected in large-scale RSFQ circuits design, we have designed a small RSFQ microprocessor based on simple architecture using our top-down design methodology. We have estimated its system performance and compared it with that of the CMOS microprocessor with the same architecture. It was found that the RSFQ system is superior in terms of the operating speed though it requires extremely large chip area.

Differential pass transistor logic in CMOS technology

Differential pass transistor logic is described in the letter. This configuration results in better silicon area efficiency and higher speed of operation than conventional CMOS pass transistor logic.