CMOS Oscillator Research Articles

Fully active and highly reliable combined ring voltage controlled CMOS oscillator

Leveraging two types of enhanced delay stages to form an oscillation loop, results in a highly reliable CMOS ring oscillator versus external interventions. The idea is investigated via symbolic delay calculations and the HSPICE circuit simulator while 0.18 μm CMOS is exploited. Based on two described inverters, three-ring oscillators are presented. The two ones use only one type of delay stage while the third is combined using two basic inverters and a single current-starved inverter. The basic type inverter is the fastest while is sensitive to power supply and temperature variations. On the other hand, the sensitivity of the current starved inverter is acceptable but this delay stage shows a large delay time, reducing oscillation frequency. This work tries to address this tradeoff between speed and sensitivity by proposing an oscillation loop. The delay times analysis and simulation results verify the robust performance of the proposed oscillator.

A 4H-SiC CMOS Oscillator-Based Temperature Sensor Operating from 298 K up to 573 K.

In this paper, we propose a temperature sensor based on a 4H-SiC CMOS oscillator circuit and that is able to operate in the temperature range between 298 K and 573 K. The circuit is developed on Fraunhofer IISB's 2 μm 4H-SiC CMOS technology and is designed for a bias voltage of 20 V and an oscillation frequency of 90 kHz at room temperature. The possibility to relate the absolute temperature with the oscillation frequency is due to the temperature dependency of the threshold voltage and of the channel mobility of the transistors. An analytical model of the frequency-temperature dependency has been developed and is used as a starting point for the design of the circuit. Once the circuit has been designed, numerical simulations are performed with the Verilog-A BSIM4SiC model, which has been opportunely tuned on Fraunhofer IISB's 2 μm 4H-SiC CMOS technology, and their results showed almost linear frequency-temperature characteristics with a coefficient of determination that was higher than 0.9681 for all of the bias conditions, whose maximum is 0.9992 at a VDD = 12.5 V. Moreover, we considered the effects of the fabrication process through a Monte Carlo analysis, where we varied the threshold voltage and the channel mobility with different values of the Gaussian distribution variance. For example, at VDD = 20 V, a deviation of 17.4% from the nominal characteristic is obtained for a Gaussian distribution variance of 20%. Finally, we applied the one-point calibration procedure, and temperature errors of +8.8 K and -5.8 K were observed at VDD = 15 V.

A 28-nm 368-fJ/Cycle, 0.43%/V Supply-Sensitivity, FLL-Based RC Oscillator Featuring Positive-TC-Only Resistors and ΔΣM-Based Trimming

This Brief presents a process-scaling-friendly frequency-locked-loop (FLL)-based RC oscillator. It features an R-R-C frequency-to-voltage converter that entails resistors with only the same-sign temperature coefficients. Together with a low-leakage switched-capacitor resistor and a delta-sigma-modulator-based trimming, our 71.8-MHz RC oscillator in 28-nm CMOS achieves a frequency inaccuracy of 77.6 ppm/0C, a 0.43%/V supply sensitivity, and an 11-psrms period jitter. The energy efficiency is 368 fJ/cycle.

A Tuning Range Extension Technique for Waveform-Shaping Single-Core CMOS Oscillators With No Dedicated Harmonic Tuning

This brief presents a tuning range extension technique for output voltage waveform-shaping single-core CMOS oscillators. First, the parasitic capacitors in previous waveform-shaping oscillators that limit the tuning range are analyzed. Next, a triple coupled LC resonator (TCLCR) is proposed to separate the differential-mode and common-mode (CM) resonance path which improves the tuning range significantly. The TCLCR is also able to establish the harmonically tuned impedance without using dedicated harmonic tuning both at CM 2rd harmonic and 3rd harmonic for oscillator’s implicit CM resonance or class-F23 operation to suppress the white noise and flicker noise conversion to phase noise. Finally, as a proof of concept, a 2.79-to-4.9 GHz class-F23 oscillator prototype covering a wide tuning range of 54.9% is designed and fabricated in a 130-nm CMOS technology. The oscillator achieves figure-of-merit with tuning range (FOMT) of 199.4/202.2 dBc/Hz, 196.3/200.9 dBc/Hz and 195/199.7 dBc/Hz at 100-kHz/1-MHz offset from 2.79, 3.83 and 4.9 GHz.

Near-field sensor array with 65-GHz CMOS oscillators can rapidly and comprehensively evaluate drug susceptibility of Mycobacterium

Multidrug-resistant tuberculosis (MDR-TB) is a major clinical problem. Because Mycobacterium, the causative agent of tuberculosis, are slow-growing bacteria, it takes 6–8 weeks to complete drug susceptibility testing, and this delay contributes to the development of MDR-TB. Real-time drug resistance monitoring technology would be effective for suppressing the development of MDR-TB. In the electromagnetic frequency from GHz to THz regions, the spectrum of the dielectric response of biological samples has a high dielectric constant owing to the relaxation of the orientation of the overwhelmingly contained water molecule network. By measuring the change in dielectric constant in this frequency band in a micro-liquid culture of Mycobacterium, the growth ability can be detected from the quantitative fluctuation of bulk water. The 65-GHz near-field sensor array enables a real-time assessment of the drug susceptibility and growth ability of Mycobacterium bovis (BCG). We propose the application of this technology as a potential new method for MDR-TB testing.

Analysis of Layout Arrangement for CMOS Oscillators to Reduce Overall Variation on Silicon

Analysis of Layout Arrangement for CMOS Oscillators to Reduce Overall Variation on Silicon

High Resolution CMOS Frequency-to-digital Converter for a Fine Dust Sensor using a MEMS Resonator

A high resolution, low power CMOS oscillator and frequency-to-digital converter for a fine dust sensor using a MEMS resonator is proposed. The proposed frequency-to-digital converter is realized based on dual-loop hybrid delay-locked loop to distinguish fine frequency variations according to very small fine dust concentrations, and simultaneously applied binary and square search algorithms to obtain accurate digital codes indicating frequency changes. An oscillator and frequency-to-digital converter for a fine dust sensor is implemented using the 0.18-μm CMOS process. The core size of the fabricated MEMS oscillator and frequency-to-digital converter is 0.9 mm² and consumes about 16 mW of power at 1.8 V supply voltage. The proposed frequency-to-digital converter covers the input frequency range of 1.7 GHz to 2.3 GHz with 1 bit resolution of about 3 MHz.

Even-Harmonic Class-E CMOS Oscillator

This article proposes the theory and implementation of an even-harmonic class-<inline-formula> <tex-math notation="LaTeX">$E$ </tex-math></inline-formula> CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high-<inline-formula> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and current waveforms of the transistor that increases the power efficiency of the oscillator. Furthermore, it widens the flat span of the semi half-sinusoidal voltage waveform, where the impulse sensitivity function (ISF) is negligible. Therefore, the conversion of the core transistor noise to phase noise is reduced. These features improve the oscillator&#x2019;s figure of merit (FoM) in comparison with state-of-the-art CMOS oscillators. The prototype of the even-harmonic class-<inline-formula> <tex-math notation="LaTeX">$E$ </tex-math></inline-formula> oscillator is implemented in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. At 4 GHz, it exhibits a phase noise of &#x2212;152.75 dBc/Hz at a 10-MHz offset while providing a 10.6% tuning range. The corresponding FoM is 197.9 dBc/Hz. The circuit draws 7 mA from a 0.7-V supply, and the die area is 0.23 mm².

Overview of Sub-100 mV Oscillators

This paper presents a comprehensive review of the state of the art for oscillators operating at reduced supply voltage. The analysis and implementation examples of differ-ent types of oscillators, such as LC oscillators, transformer-based oscillators, and CMOS oscillators are presented. Expres-sions for the oscillation frequency and the minimum supply voltage limit are provided. The characteristics, advantages, and constrains of different topologies are discussed, providing a reference guideline for the choice of the best topology for a given application.

Efficient 6.5 dBm 55 GHz CMOS VCO with simultaneous phase noise and tuning range optimization

Abstract This paper presents the design and characterization of an efficient high-output-power 55 GHz fundamental oscillator. The performance parameters of the oscillator are analysed as a function of the contributors of the tank capacitance, and the design choices in the varactor for phase noise and for tuning range are exemplified. The circuit was implemented in 22 nm FD-SOI CMOS technology and occupies 0.046 mm2 area including the matching network. On-wafer measurement results have demonstrated 6.5 dBm peak output power, 22% peak DC-to-RF efficiency and −98.3 dBc/Hz phase noise at 1 MHz offset frequency, while the core draws 8.3 mW power. To the best knowledge of the authors, the efficiency is the best, while the output power is the second best among CMOS oscillators in the same frequency range, and the phase noise is the best result for V-band fundamental CMOS oscillators reported to date.

Performance Comparison of CNFET, CMOS and Hybrid CMOS-CNFET Oscillator Circuits

Performance Comparison of CNFET, CMOS and Hybrid CMOS-CNFET Oscillator Circuits

A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS

This letter presents a circuit solution to extract the fourth harmonic from a class-C voltage-controlled oscillator (VCO). The tail capacitor in the class-C oscillator is replaced by a dual-resonance network that allows the extraction of the fourth harmonic, while yielding low impedance at even harmonics, which is key to maintaining transistor operation in class-C. The validity of the proposed approach is demonstrated on a 20-GHz 28-nm CMOS oscillator. The circuit achieves a phase noise as low as −111 dBc/Hz at 3-MHz offset from a 78-GHz carrier while consuming 57 mW, with a figure of merit (FoM) of −182 dBc/Hz, 12% tuning range, and a dc to RF conversion of 0.7%. The undesired harmonics are suppressed by more than 70 dB.

Wireless Multiplexing Agile Antenna-Based Control System

Multiplexing and Multiple access technologies are becoming vital components for high-performance wireless communication system. Whereas multiplexing techniques employing either multiple antennas or multiband/wideband antennas for multiplexing are commonly used, these techniques have inherent drawbacks. A feasible solution to this is to employ frequency reconfigurable or frequency agile antennas. This approach has advantages from both multiple antenna and multiband/wideband antenna designs. In this paper, a hardware implementation of a proposed biasing and control circuit/system for wireless multiplexing that utilizes a frequency reconfigurable or frequency agile antenna is reported. The device comprises a microcontroller, DAC, CMOS oscillator, power module and a USB interface for communication with a custom-built software installed on a PC. The device has functions for control, digital signal processing and de-multiplexing. The device is fed with an input multiplexed signal, and the de-multiplexed output signals are extracted and displayed on the graphical user interface of the software. Due to the re-configurability and programmability of the device, it presents a flexible, cost effective solution for a variety of real-world applications.

Balanced Drive and Sense CMOS Thermal Piezoresistive Resonators and Oscillators

In this work, we report a novel fully balanced drive and sense thermal-piezoresistive resonator (TPR) in 2P-4M 0.35μm CMOS technology with maskless post-release process. Through the use of the Wheatstone bridge arrangement for both the thermal drive heater resistors and sense piezoresistors, the proposed design greatly simplifies the overall system by removing the need for bias-tee or noisy and power consuming current sink/source. This ensures that the differential terminals of drive and sense ports are at the same DC potential, thus allowing the use of standard differential amplifiers as interface circuits. In addition, this design utilizes bimorph like actuation which enables in-plane motion. An in-plane clamped-clamped beam (CCB) TPR was fabricated, demonstrating a quality factor (Q) of 1,600 at 2 MHz with transconductance (gm) of 46.8 μS for a dc-power of 1.7 mW in a vacuum (1 mTorr). To go one step further, a double-ended tuning fork (DETF) TPR was designed, featuring a transconductance of 62.7 μS with Q of 4,400 at 1.9 MHz under the same conditions as CCB. The CCB thermal-piezoresistive oscillator (TPO) implemented using a discrete interface circuit had phase noise of -89 dBc/Hz and -100 dBc/Hz at 1 kHz and 1 MHz respectively while that for DETF TPO was -100 dBc/Hz at 1 kHz and -100 dBc/Hz at 1 MHz in air. Frequency stability was found to be 180 ppb and 125 ppb for CCB and DETF TPOs respectively in air.

Design of low power VCO using FinFET technology for biomedical applications

A voltage controlled oscillator (VCO) is one of the most significant essential structure obstructs in simple and advanced circuit (CKT). In Biomedical applications the nature of the biomedical connection is resolved in huge part by the qualities of the VCO and in the present biomedical applications more prominent recurrence goes is required by the VCOs. Generally, VCOs utilizing CMOS innovation have been utilized for low recurrence applications, however 18 nm forms have permitted CMOS oscillators to accomplish frequency in the gigahertz extend. This range is made conceivable with the utilization of programmed swing control. VCO can be fabricated utilizing many CKT strategies. VCO can be built using many CKT techniques. To design improved performance VCO’s explicitly low power different techniques using latest cadence software to obtain high density and low leakage current. To optimize and design the VCs, carry out analysis and enhance the performance. To design VCO with four different techniques using latest cadence software, optimize their performance and measure it in cadence software environment.

58 GHz CMOS VCO with 16% efficiency

This Letter presents a millimetre-wave CMOS oscillator, which achieves 4.9 dBm output power with 16% peak power efficiency. A phase noise of − 98 dBc / Hz at 1 MHz offset frequency and 26.7% tuning range around 57.5 GHz centre frequency were verified experimentally. To the best knowledge of the authors, the output power, efficiency, and phase noise performance are the best among fundamental CMOS oscillators in the frequency range of interest, while the tuning range is the third highest result reported to date. The circuit occupies a silicon area of ∼ 9000 μ m 2 without the matching inductors on a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS technology.

A 5 GHz 0.5 V Hybrid Class-B/F−1 CMOS Oscillator With −147 dBc/Hz Phase Noise at 10 MHz Offset Using Body-Biased 22 nm FDSOI

This work presents a self-biased 5 GHz hybrid class-B/F−1 oscillator for low phase noise and robust startup. The design exploits the concurrent conduction of nMOS and pMOS, when placed on differential sides, to form a differential-mode (DM) high-quality-factor second-harmonic resonator for low phase noise. The same resonator is shared between the main core (class-F−1) and the startup core (class-B), to allow phase noise reduction. The hybrid CMOS oscillator is fabricated in 22 nm fully depleted silicon-on-insulator (FDSOI) using thin-oxide-only devices, operated from 0.5 V supply, and achieves a phase noise <−147 dBc/Hz at 10 MHz offset across 11% tuning range. The peak figure of merit (FoM) is 190 dBc/Hz, and the supply frequency pushing ranges from 20–44 MHz/V, whereas the power consumption is from 15 to 18 mW. To the authors’ knowledge, the hybrid class-B/F−1 oscillator delivers the lowest phase noise using a 0.5 V supply at 5 GHz.

SiC Strained nMOSFETs With Enhanced High- Frequency Performance and Impact on Flicker Noise and Random Telegraph Noise

Silicon–carbon (SiC) strained nMOSFETs with sub-35-nm gate length in a 40-nm CMOS technology can realize superior cutoff frequency ( $f_{T}$ ) up to 405 GHz, attributed to more than 20% enhancement of the mobility and transconductance. This super-400-GHz $f_{T}$ makes SiC strained nMOS an attractive high mobility device aimed at millimeter-wave (mm-wave) CMOS circuits design. However, the SiC nMOSFETs reveal a dramatic increase in flicker noise and random telegraph noise (RTN), which may cause worse phase noise and detrimental impact on CMOS oscillator stability. The complex RTN features abnormally long capture and emission time constants ( $\tau _{c}$ and $\tau _{e}$ ) and suggests electron-phonon coupling responsible for the anomalously slow trapping and detrapping, due to a significant increase of relaxation energy from SiC strain. This critical tradeoff between high-frequency performance and low-frequency noise becomes a key factor to be considered for the most appropriate adoption of high mobility devices and design optimization adapted to various circuits.

A High Fundamental Frequency Sub-THz CMOS Oscillator With a Capacitive Load Reduction Circuit

This article presents a high fundamental frequency subterahertz (sub-THz) CMOS oscillator with a single core. The proposed structure with a capacitive load reduction circuit increases the fundamental oscillation frequency by decreasing the parasitic capacitances of the buffer transistor and inductor and minimizing the loss caused by the gate resistance of the buffer stage. To achieve high output power, the proposed oscillator combines the differential output signals through a differential-to-single (DTS) transformer. A push-push oscillator based on the high fundamental frequency oscillator is also introduced to increase the operating frequency further. The proposed oscillators are implemented in a 65-nm CMOS process. Measurements of the fundamental oscillator reveal an output power of 0.285 mW at 251 GHz, while consuming 21 mA from a 1.3-V supply voltage. The measured operating frequency of the push-push oscillator is 432 GHz.

High Power and High Frequency CMOS Oscillator With Source-to-Drain Coupling and Capacitive Load Reduction Circuit

A design for a high-output-power, high-frequency CMOS oscillator is presented in this paper. The proposed oscillator can increase the output power by coupling the signal at the source of the core transistor to the drain of the buffer transistor. In addition, the source-to-drain coupling generates an optimum negative transconductance at the desired operating frequency. A capacitive load reduction circuit is also applied to increase the fundamental oscillation frequency. Using these techniques, the fundamental and push-push oscillators were implemented using 65 nm CMOS technology. The measurement results of the fundamental and push-push oscillators showed 2.7 and -25 dBm of peak differential output power at 194 and 394 GHz, respectively. In the 200 GHz frequency band, the proposed fundamental oscillator shows the highest output power among recently reported state-of-the-art CMOS oscillators.